ANALOG DEVICES AD9911 Service Manual

500 MSPS Direct Digital Synthesizer

FEATURES

Patented SpurKiller technology Multitone generation Test-tone modulation Up to 800 Mbps data throughput Matched latencies for frequency/phase/amplitude changes Linear frequency/phase/amplitude sweeping capability Up to 16 levels of FSK, PSK, ASK Programmable DAC full-scale current 32-bit frequency tuning resolution 14-bit phase offset resolution 10-bit output amplitude-scaling resolution Software-/hardware-controlled power-down Multiple device synchronization Selectable 4× to 20× REF_CLK multiplier (PLL) Selectable REF_CLK crystal oscillator 56-lead LFCSP

APPLICATIONS

Agile local oscillator Test and measurement equipment Commercial and amateur radio exciter Radar and sonar Test-tone generation Fast frequency hopping Clock generation

with 10-Bit DAC

AD9911

GENERAL DESCRIPTION

The AD9911 is a complete direct digital synthesizer (DDS). This device includes a high speed DAC with excellent wideband and narrowband three auxiliary DDS cores without assigned digital-to-analog converters (DACs). These auxiliary channels are used for spur reduction, multitone generation, or test-tone modulation.

The AD9911 is the first DDS to incorporate SpurKiller technology and multitone generation capability. Multitone mode enables the generation up to four concurrent carriers; frequency, phase and amplitude can be independently programmed. Multitone generation can be used for system tests, such as inter-modulation distortion and receiver blocker sensitivity. SpurKilling enables customers to improve SFDR performance by reducing the magnitude of harmonic components and/or the aliases of those harmonic components.

Test-tone modulation efficiently enables sine wave modulation of amplitude on the output signal using one of the auxiliary DDS cores.

The AD9911 can perform modulation of frequency, phase, or amplitude (FSK, PSK, ASK). Modulation is implemented by storing profiles in the register bank and applying data to the profile pins. In addition, the AD9911 supports linear sweep of frequency, phase, or amplitude for applications such as radar and instrumentation.

spurious-free dynamic range (SFDR) as well as

500MSPS

DDS CORE

SYSTEM

CLOCK

SOURCE

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

MODULATION CONTROL

REF CLOCK

INPUT CIRCUITRY

USER INTERFACE

Figure 1. Basic Block Diagram

TIMING AND

CONTROL

(continued on Page 3)

10-BIT DAC

SPUR REDUCTION/

MULTITONE

RECONSTRUCTED SINE WAVE

05785-002

AD9911

REVISION HISTORY

5/06—Revision 0: Initial Version

Rev. 0 | Page 2 of 44

AD9911

GENERAL DESCRIPTION

The DDS acts as a high resolution frequency divider with the REF_CLK as the input and the DAC providing the output. The REF_CLK input can be driven directly or used in combination with an integrated REF_CLK multiplier (PLL). The REF_CLK input also features an oscillator circuit to support an external crystal as the REF_CLK source. The crystal can be used in combination with the REF_CLK multiplier.

The AD9911 I/O port offers multiple configurations to provide significant flexibility. The I/O port offers an SPI-compatible mode of operation that is virtually identical to the SPI operation found in earlier Analog Devices DDS products.

FUNCTIONAL BLOCK DIAGRAM

Flexibility is provided by four data pins (Pin SDIO_0, Pin SDIO_1, Pin SDIO_2, and Pin SDIO_3) that allow four programmable modes of I/O operation.

The DAC output is supply referenced and must be terminated into AVDD b y a r e si s tor a n d an AVDD c ent e r-t a ppe d tr ansformer. The DAC has its own programmable reference to enable different full-scale currents.

The DDS core (the AVDD pins and the DVDD pins) is powered by a 1.8 V supply. The digital I/O interface (SPI) operates at

3.3 V and requires that the Pin DVDD_I/O (Pin 49) be connected to 3.3 V.

AD9911

IOUT

DAC_RSET

PWR_DWN_CT L

MASTER_RESET

SCLK CS

SDIO_0 SDIO_1 SDIO_2 SDIO_3

05785-001

SYNC_IN

SYNC_OUT

I/O_UPDATE

SYNC_CLK

REF_CLK

32

FTW/

ΔFTW

BUFFER/

XTAL

OSCILLATOR

CLK_MODE_SE L

÷4

Σ

32

REF CLOCK MULTIPLIER

4× TO 20×

LOOP FILTER

Σ

PHASE/

ΔPHASE

TIMING AND CONTROL L OGIC

COS(X)

Σ Σ

DDS

CORE

SYSTEM

CLK

MUX

1.8V

AVDD DVDD

1.8V

1015

ΔAMP

10

AMP/

1014

SPURKILLER/

MULTI-TONE

MUX

DDS

CORE

CONTROL

REGISTERS

C

H

A

N

E

R

I

E

G

E

S

T

R

PROFILE

REGISTERS

P0 P1 P2 P3 DVDD_I/O

CORE

L

S

DDS

MUX

SCALABLE

DAC REF

CURRENT

PORT

BUFFER

DAC

I/O

3.3V

Figure 2. Functional Block Diagram

Rev. 0 | Page 3 of 44

AD9911

SPECIFICATIONS

AVDD and DVDD = 1.8 V ± 5%; DVDD_I/O = 3.3 V ± 5%; R multiplier bypassed), unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

REF CLOCK INPUT CHARACTERISTICS

Frequency Range

REF_CLK Multiplier Bypassed 1 500 MHz REF_CLK Multiplier Enabled 10 125 MHz Internal VCO Output Frequency Range

VCO Gain Bit Set

Internal VCO Output Frequency Range

VCO Gain Bit Cleared

Crystal REF_CLK Source Range 20 30 MHz

Input Power Sensitivity

Input Voltage Bias Level 1.15 V Input Capacitance 2 pF Input Impedance 1500 Ω Duty Cycle with REF_CLK Multiplier Bypassed 45 55 % Duty Cycle with REF_CLK Multiplier Enabled 35 65 % CLK Mode Select (Pin 24) Logic 1 V 1.25 1.8 V 1.8 V digital input logic CLK Mode Select (Pin 24) Logic 0 V 0.5 V 1.8 V digital input logic

DAC OUTPUT CHARACTERISTICS Must be referenced to AVDD

Full-Scale Output Current 10 mA 10 mA is set by R Gain Error

Output Current Offset 1 25 μA Differential Nonlinearity ±0.5 LSB Integral Nonlinearity ±1.0 LSB Output Capacitance 3 pF Voltage Compliance Range

WIDEBAND SFDR

1 MHz to 20 MHz Analog Output

20 MHz to 60 MHz Analog Output

60 MHz to 100 MHz Analog Output

100 MHz to 150 MHz Analog Output

150 t MHz to 200 MHz Analog Output

WIDEBAND SFDR Improvement

Spur Reduction Enabled

60 MHz to 100 MHz Analog Output 8 dBc 100 MHz to 150 MHz Analog Output 15 dBc 150 MHz to 200 MHz Analog Output 12 dBc

1

255 500 MHz

100 160 MHz

−5

−10

AVDD –

0.50

= 1.91 kΩ; external reference clock frequency = 500 MSPS (REF_CLK

SET

+3 dBm Measured at the pin (single-ended)

= 1.91 kΩ

SET

+10 %FS

−65

−62

−59

−56

−53

AVDD +

0.50

dBc

V

The frequency range for wideband SFDR is defined as dc to Nyquist

Programs devices on an individual basis to enable spur reduction. See the SpurKiller/Multitone Mode section.

Rev. 0 | Page 4 of 44

AD9911

Parameter Min Typ Max Unit Test Conditions/Comments

NARROWBAND SFDR

1.1 MHz Analog Output (±10 kHz)

1.1 MHz Analog Output (±50 kHz)

1.1 MHz Analog Output (±250 kHz)

1.1 MHz Analog Output (±1 MHz)

15.1 MHz Analog Output (±10 kHz)

15.1 MHz Analog Output (±50 kHz)

15.1 MHz Analog Output (±250 kHz)

15.1 MHz Analog Output (±1 MHz)

40.1 MHz Analog Output (±10 kHz)

40.1 MHz Analog Output (±50 kHz)

40.1 MHz Analog Output (±250 kHz)

40.1 MHz Analog Output (±1 MHz)

75.1 MHz Analog Output (±10 kHz)

75.1 MHz Analog Output (±50 kHz)

75.1 MHz Analog Output (±250 kHz)

75.1 MHz Analog Output (±1 MHz)

100.3 MHz Analog Output (±10 kHz)

100.3 MHz Analog Output (±50 kHz)

100.3 MHz Analog Output (±250 kHz)

100.3 MHz Analog Output (±1 MHz)

200.3 MHz Analog Output (±10 kHz)

200.3 MHz Analog Output (±50 kHz)

200.3 MHz Analog Output (±250 kHz)

200.3 MHz Analog Output (±1 MHz)

−90

−88

−86

−85

−90

−87

−85

−83

−90

−87

−84

−82

−87

−85

−83

−82

−87

−85

−83

−81

−87

−85

−83

−81

PHASE NOISE CHARACTERISTICS

Residual Phase Noise @ 15.1 MHz (f

)

OUT

1 kHz Offset –150 dBc/Hz 10 kHz Offset –159 dBc/Hz 100 kHz Offset –165 dBc/Hz 1 MHz Offset –165 dBc/Hz

Residual Phase Noise @ 40.1 MHz (f

)

OUT

1 kHz Offset –142 dBc/Hz 10 kHz Offset –151 dBc/Hz 100 kHz Offset –160 dBc/Hz 1 MHz Offset –162 dBc/Hz

Residual Phase Noise @ 75.1 MHz (f

)

OUT

1 kHz Offset –135 dBc/Hz 10 kHz Offset –146 dBc/Hz 100 kHz Offset –154 dBc/Hz 1 MHz Offset –157 dBc/Hz

Residual Phase Noise @ 100.3 MHz (f

)

OUT

1 kHz Offset –134 dBc/Hz 10 kHz Offset –144 dBc/Hz 100 kHz Offset –152 dBc/Hz 1 MHz Offset –154 dBc/Hz

dBc

dBc dBc

dBc

dBc dBc

dBc

dBc dBc

dBc

Rev. 0 | Page 5 of 44

AD9911

Parameter Min Typ Max Unit Test Conditions/Comments

Residual Phase Noise @ 15.1 MHz (f

OUT

) with

REF_CLK Multiplier Enabled 5× 1 kHz Offset –139 dBc/Hz 10 kHz Offset –149 dBc/Hz 100 kHz Offset –153 dBc/Hz 1 MHz Offset –148 dBc/Hz

Residual Phase Noise @ 40.1 MHz (f

OUT

)

with REF_CLK Multiplier Enabled 5× 1 kHz Offset –130 dBc/Hz 10 kHz Offset –140 dBc/Hz 100 kHz Offset –145 dBc/Hz 1 MHz Offset –139 dBc/Hz

Residual Phase Noise @ 75.1 MHz (f

OUT

) with

REF_CLK Multiplier Enabled 5× 1 kHz Offset –123 dBc/Hz 10 kHz Offset –134 dBc/Hz 100 kHz Offset –138 dBc/Hz 1 MHz Offset –132 dBc/Hz

Residual Phase Noise @ 100.3 MHz(f

OUT

) with

REF_CLK Multiplier Enabled 5× 1 kHz Offset –120 dBc/Hz 10 kHz Offset –130 dBc/Hz 100 kHz Offset –135 dBc/Hz 1 MHz Offset –129 dBc/Hz

Residual Phase Noise @ 15.1 MHz (f

OUT

)

with REF_CLK Multiplier Enabled 20× 1 kHz Offset –127 dBc/Hz 10 kHz Offset –136 dBc/Hz 100 kHz Offset –139 dBc/Hz 1 MHz Offset –138 dBc/Hz

Residual Phase Noise @ 40.1 MHz (f

OUT

)

with REF_CLK Multiplier Enabled 20× 1 kHz Offset –117 dBc/Hz 10 kHz Offset –128 dBc/Hz 100 kHz Offset –132 dBc/Hz 1 MHz Offset –130 dBc/Hz

Residual Phase Noise @ 75.1 MHz (f

OUT

)

with REF_CLK Multiplier Enabled 20× 1 kHz Offset –110 dBc/Hz 10 kHz Offset –121 dBc/Hz 100 kHz Offset –125 dBc/Hz 1 MHz Offset –123 dBc/Hz

Residual Phase Noise @ 100.3 MHz (f

OUT

) with

REF_CLK Multiplier Enabled 20× 1 kHz Offset –107 dBc/Hz 10 kHz Offset –119 dBc/Hz 100 kHz Offset –121 dBc/Hz 1 MHz Offset –119 dBc/Hz

Rev. 0 | Page 6 of 44

AD9911

Parameter Min Typ Max Unit Test Conditions/Comments

I/O PORT TIMING CHARACTERISTICS

Maximum Frequency Clock (SCLK) 200 MHz Minimum SCLK Pulse Width Low (t Minimum SCLK Pulse Width High (t Minimum Data Set-Up Time (tDS) 2.2 ns Minimum Data Hold Time 0 ns Minimum CSB Set-Up Time (t Minimum Data Valid Time for Read Operation 12 ns

MISCELLANEOUS TIMING CHARACTERISTICS

Master_Reset Minimum Pulse Width 1 Minimum pulse width = 1 sync clock period I/O_Update Minimum Pulse Width 1 Minimum pulse width = 1 sync clock period Minimum Set-Up Time (I/O_Update to

SYNC_CLK)

Minimum Hold Time (I/O_Update to

SYNC_CLK)

Minimum Set-Up Time (Profile Inputs to

SYNC_CLK)

Minimum Hold Time (Profile Inputs to

SYNC_CLK)

Minimum Set-Up Time (SDIO Inputs to

SYNC_CLK)

Minimum Hold Time (SDIO Inputs to

SYNC_CLK)

Propagation Delay Between REF_CLK and

SYNC_CLK

CMOS LOGIC INPUT

VIH 2.0 V VIL 0.8 V Logic 1 Current 3 12 μA Logic 0 Current

Input Capacitance 2 pF

CMOS LOGIC OUTPUTS (1 mA Load)

V

OH

VOL 0.4 V

POWER SUPPLY

Total Power Dissipation—Single-Tone Mode 241 mW Dominated by supply variation Total Power Dissipation—With Sweep

Accumulator

Total Power Dissipation—3 Spur

Reduction/Multitone Channels Active

Total Power Dissipation—Test-Tone

Modulation Total Power Dissipation—Full Power Down 1.8 mW IAVDD—Single-Tone Mode 73 mA IAVDD— Sweep Accumulator, REF_CLK

Multiplier, and 10-Bit Output Scalar Enabled IDVDD—Single-Tone Mode 50 mA IDVDD—Sweep Accumulator, REF_CLK

Multiplier, and 10-Bit Output Scalar Enabled IDVDD_I/O 40 mA IDVDD = read

IDVDD_I/O 30 mA IDVDD = write IAVDD Power-Down Mode 0.7 mA IDVDD Power-Down Mode 1.1 mA

) 1.6 ns

PWL

) 2.2 ns

PWH

) 1.0 ns

PRE

4.8 ns Rising edge to rising edge

0 ns Rising edge to rising edge

5.4 ns

0 ns

2.5 ns

0 ns

2.25 3.5 5.5 ns

−12

μA

2.7 V

241 mW Dominated by supply variation

351 mW Dominated by supply variation

264 mW Dominated by supply variation

73 mA

50 mA

Rev. 0 | Page 7 of 44

AD9911

Parameter Min Typ Max Unit Test Conditions/Comments

DATA LATENCY (PIPELINE DELAY) SINGLE-

TONE MODE

2, 3

Frequency, Phase, and Amplitude Words to

DAC Output with Matched Latency Enabled

Frequency Word to DAC Output with

Matched Latency Disabled

Phase Offset Word to DAC Output with

Matched Latency Disabled

Amplitude Word to DAC Output with

Matched Latency Disabled

DATA LATENCY (PIPELINE DELAY)

MODULATION MODE

4

Frequency Word to DAC Output 34 SYSCLK

Phase Offset Word to DAC Output 29 SYSCLK

Amplitude Word to DAC Output 21 SYSCLK

DATA LATENCY (PIPELINE DELAY) LINEAR

SWEEP MODE

4

Frequency Rising/Falling Delta Tuning Word

to DAC Output

Phase Offset Rising/Falling Delta Tuning

Word to DAC Output

Amplitude Rising/Falling Delta Tuning Word

to DAC Output

1

For the VCO frequency range of 160 MHz to 255 MHz, the appropriate setting for the VCO gain bit is dependent upon supply, temperature and process. Therefore, in a

production environment this frequency band must be avoided.

2

Data latency is reference to the I/O_UPDATE pin.

3

Data latency is fixed and the units are system clock (SYSCLK) cycles

4

Data latency is referenced to a profile change.

29 SYSCLK

cycles

29 SYSCLK

cycles

25 SYSCLK

cycles

17 SYSCLK

cycles

Cycles

41 SYSCLK

Cycles

37 SYSCLK

Cycles

29 SYSCLK

Cycles

Rev. 0 | Page 8 of 44

AD9911

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Maximum Junction Temperature 150°C DVDD_I/O (Pin 49) 4 V AVDD, DVDD 2 V Digital Input Voltage (DVDD_I/O = 3.3 V) −0.7 V to +4 V Digital Output Current 5 mA Storage Temperature –65°C to +150°C Operating Temperature –40°C to +85°C Lead Temperature (10 sec Soldering) 300°C

θ

JA

21°C/W

θJC 2°C/W

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

EQUIVALENT INPUT AND OUTPUT CIRCUITS

DAC OUTPUTS

CMOS

DIGITAL INPUTS

DVDD_I/O = 3.3V

INPUT OUTPUT

NOTES

1. AVOID OVERDRIVING DI GITAL INPUTS.

Figure 3. CMOS Digital Inputs

05785-003

IOUT

NOTES

1. TERMINATE OUTPUTS INTO AVDD.

2. DO NOT EXCEED OUTPUTS VOLTAGE COMPLIANCE.

IOUT

Figure 4. DAC Outputs

REF_CLK INPUTS

AVD D

REF_CLK REF _CLK

AVD D

NOTES

1. REF_CLK INPUTS ARE INTE RNALLY BIASED AND NEED TO BE AC-CO UPLED.

05785-004

2. OSC INPUT S ARE DC-COUPLE D.

1.5kΩ

Z Z

AMP

1.5kΩ

AVD D

OSC

05785-005

Figure 5. REF_CLK Inputs

Rev. 0 | Page 9 of 44

AD9911

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

K

_0

22

REF_CLK23REF_C

DVDD46I/O_UPDATE47CS48SCLK49DVDD_I/O50SDIO

DGND43P3

44

45

24

25

26

27

28

LK

NC

AVDD

AGND

LOOP_FILTER

CLK_MODE_SEL

SDIO_152SDIO_253SDIO_354SYNC_CL

DVDD56DGND

55

51

PIN 1

AVD D

AVD D AVD D AVD D

AVD D

AVD D AVD D

NC

1 2 3 4 5 6 7 8

9 10 11 12 13 14

INDICATOR

AD9911

TOP VIEW

(Not to Scale)

16NC17

19

20

18

15

DD AV

AVDD21AVDD

AGND

DAC_RSET

NC = NO CONNECT

SYNC_IN

SYNC_OUT

MASTER_RESET

PWR_DWN_CTL

NOTES

1. THE EXPO SED EPAD ON BOTTOM SIDE O F PACKAGE IS AN ELECTRICAL CONNECTION AND MUST BE SOLDERED TO GROUND.

2. PIN 49 IS DVDD_I/O AND IS TIED TO 3.3V.

Figure 6. Pin Configuration

42 41 40 39 38 37 36 35 34 33 32 31 30 29

P2 P1 P0 AVD D AGND AVD D IOUT IOUT AGND AVD D NC AVD D AVD D AVD D

05785-006

Table 3. Pin Function Descriptions

Pin No. Mnemonic I/O Description

1 SYNC_IN I

Synchronizes Multiple AD9911 Devices. Connects to the SYNC_OUT pin of the master AD9911 device.

2 SYNC_OUT O

Synchronizes Multiple AD9911 Devices. Connects to the SYNC_IN pin of the slave AD9911 device.

3 MASTER_RESET I

Active High Reset Pin. Asserting this pin forces the internal registers to the default state shown in the

Register Map section. 4 PWR_DWN_CTL I External Power-Down Control. See the Power Down Functions section for details. 5, 7, 8, 9, 11, 13, 14,

AVDD I Analog Power Supply Pins (1.8 V). 15, 19, 21, 26, 29, 30, 31, 33, 37, 39

18, 20, 25, 34, 38 AGND I Analog Ground Pins. 45, 55 DVDD I Digital Power Supply Pins (1.8 V). 44, 56 DGND I Digital Power Ground Pins. 35

IOUT

O Complementary DAC Output. Terminates into AVDD.

36 IOUT O True DAC Output. Terminates into AVDD. 17 DAC_RSET I

Establishes the Reference Current for the DAC. A 1.91 kΩ resistor (nominal) is connected from Pin 17 to AGND.

22

REF_CLK

I

Complementary Reference Clock/Oscillator Input. When the REF_CLK is operated in single-ended mode, this pin should be decoupled to AVDD or AGND with a

0.1 μF capacitor.

23 REF_CLK I

Reference Clock/Oscillator Input. When the REF_CLK operates in single-ended mode, Pin 23 is the input. See the

Modes of Operation section for the reference clock

configuration.

24 CLK_MODE_SEL I

Control Pin for the Oscillator. CAUTION: Do not drive this pin beyond 1.8 V. When high (1.8 V), the oscillator is enabled to accept a crystal as the REF_CLK source. When low, the oscillator is bypassed.

27 LOOP_FILTER I

Connects to the External Zero Compensation Network of the PLL Loop Filter. Typically, the network consists of a 0 Ω resistor in series with a 680 pF capacitor tied to AVDD.

Rev. 0 | Page 10 of 44

AD9911

Pin No. Mnemonic I/O Description

6, 10, 12, 16, 28, 32 NC N/A No Connection. Analog Devices recommends leaving these pins floating. 40, 41, 42, 43 P0, P1, P2, P3 I

46 I/O_UPDATE I

47 48 SCLK I

49 DVDD_I/O I 3.3 V Digital Power Supply for SPI Port and Digital I/O. 50 SDIO_0 I/O Data pin SDIO_0 is dedicated to the I/O port only. 51, 52, 53

54 SYNC_CLK O

CS

SDIO_1, SDIO_2, SDIO_3

I The active low chip select allows multiple devices to share a common I/O bus (SPI).

I/O

These data pins are used for modulation (FSK, PSK, ASK), start/stop for the sweep accumulator, and ramping up/down the output amplitude. Any toggle of these data inputs is equivalent to an I/O_UPDATE. The data is synchronous to the SYNC_CLK (Pin

54). The data inputs must meet the set-up and hold time requirements to the SYNC_CLK. This guarantees a fixed pipeline delay of data to the DAC output; otherwise, a ±1 SYNC_CLK period of uncertainty occurs. The functionality of these pins is controlled by profile pin configuration (PPC) bits in Register FR1 <12:14>.

A rising edge triggers data transfer from the I/O port buffer to active registers. I/O_UPDATE is synchronous to the SYNC_CLK (Pin 54). I/O_UPDATE must meet the set-up and hold time requirements to the SYNC_CLK to guarantee a fixed pipeline delay of data to DAC output. If not, a ±1 SYNC_CLK period of uncertainty occurs. The minimum pulse width is one SYNC_CLK period.

Data Clock for I/O Operations. Data bits are written on the rising edge of SCLK and read on the falling edge of SCLK.

Data pins SDIO_1:3 can be used for the I/O port or to initiate a ramp up/ramp down (RU/RD) of the DAC output amplitude.

The SYNC_CLK, which runs at ¼ the system clock rate, can be disabled. I/O_UPDATE and profile changes (Pin 40 to Pin 43) are synchronous to the SYNC_CLK. To guarantee a fixed pipeline delay of data to DAC output, I/O_UPDATE and profile changes (Pin 40 to Pin 43) must meet the set-up and hold time requirements to the rising edge of SYNC_CLK. If not, a ±1 SYNC_CLK period of uncertainty exists.

Rev. 0 | Page 11 of 44

AD9911

B

TYPICAL PERFORMANCE CHARACTERISTICS

DELTA 1 (T1) –71.73dB

4.50901804MHz

0

REF LVL 0dBm

1

–10

–20

–30

–40

–50

(dB)

–60

–70

1

–80

–90

–100

START 0Hz STO P 250MHz25MHz/DIV

Figure 7. f

= 1.1 MHz, f

OUT

RBW 20kHz RF ATT 20d VBW 20kHz SWT 1.6s UNIT d B

= 500 MSPS, Wideband SFDR

CLK

A

1AP

05785-007

0

REF LVL 0dBm

1

DELTA 1 (T1) –69.47dB

30.06012024MHz

–10

–20

–30

–40

–50

(dB)

–60

–70

1

–80

–90

–100

START 0Hz STOP 250MHz25MHz/DIV

Figure 10. f

= 15.1 MHz, f

OUT

RBW 20kHz RF ATT 20d VBW 20kHz SWT 1.6s UNIT dB

= 500 MSPS, Wideband SFDR

CLK

1AP

A

05785-010

0

REF LVL 0dBm

1

DELTA 1 (T1) –62.84dB

40.08016032MHz

–10

–20

–30

–40

–50

(dB)

–60

1

–70

–80

–90

–100

START 0Hz STOP 250Hz25MHz/DIV

Figure 8. f

REF LVL 0dBm

0

= 40.1 MHz, f

OUT

DELTA 1 (T1) –59.04dB

100.70140281MHz

–10

–20

–30

–40

–50

(dB)

–60

–70

–80

–90

–100

START 0Hz ST OP 250MHz25MHz/DIV

Figure 9. f

= 100.3 MHz, f

OUT

RBW 20kHz RF ATT 20dB VBW 20kHz SWT 1.6s UNIT dB

= 500 MSPS, Wideband SFDR

CLK

RBW 20kHz RF ATT 20d VBW 20k Hz SWT 1.6s UNIT dB

1

= 500 MSPS, Wideband SFDR

CLK

A

1AP

RBW 20kHz RF ATT 20d VBW 20kHz SWT 1.6s UNIT dB

A

0

REF Lv] 0dBm

DELTA 1 (T1) –60.13dB

75.15030060MHz

1

–10

–20

1AP

–30

–40

–50

(dB)

–60

1

–70

–80

–90

–100

05785-008

A

START 0Hz STOP 250MHz25MHz/DIV

Figure 11. f

REF LVL 0dBm

0

= 75.1 MHz, f

OUT

DELTA 1 (T1) –53.84dB –101.20240481MHz

–10

= 500 MSPS, Wideband SFDR

CLK

RBW 20kHz RF ATT 20d VBW 20kHz SWT 1.6s UNIT dB

1

–20

1AP

05785-011

A

–30

–40

–50

(dB)

–60

1

–70

–80

–90

05785-009

–100

START 0Hz STOP 250MHz25MHz/DIV

Figure 12. f

= 200.3 MHz, f

OUT

= 500 MSPS, Wideband SFDR

CLK

05785-012

Rev. 0 | Page 12 of 44

AD9911

B

REF LVL 0dBm

0

–10

–20

–30

–40

–50

(dB)

–60

–70

–80

–90

–100

CENTER 1.1MHz SPAN 1MHz100kHz/DI V

Figure 13. f

REF LVL 0dBm

0

–10

–20

–30

–40

–50

(dB)

–60

–70

–80

–90

–100

CENTER 40.1MHz SPAN 1MHz100kHz/DIV

Figure 14. f

DELTA 1 (T1) –84.73dB

254.50901604kHz

= 1.1 MHz, f

OUT

DELTA 1 (T1) –84.10dB

120.24048096kHz

= 40.1 MHz, f

OUT

RBW 500Hz RF ATT 20d VBW 500Hz SWT 20s UNIT dB

1

= 500 MSPS, NBSFDR, ±1 MHz

CLK

RBW 500 Hz RF ATT 20dB VBW 500Hz SWT 20s UNI T dB

1

= 500 MSPS, NBSFDR, ±1 MHz

CLK

1AP

REF LVL 0dBm

A

0

DELTA 1 (T1) –84.86dB –200.40080160kHz

RBW 500Hz RF ATT 20d VBW 500Hz SWT 20s UNIT dB

1

A

–10

–20

1AP

–30

–40

–50

(dB)

–60

–70

–80

–90

–100

05785-013

CENTER 15.1MHz

Figure 16. f

REF LVL 0dBm

A

0

= 15.1 MHz, f

OUT

DELTA 1 (T1) –86.03dB

262.56513026kHz

1

SPAN 1MHz100kHz/DIV

= 500 MSPS, NBSFDR, ±1 MHz

CLK

RBW 500 Hz RF ATT 20dB VBW 500 Hz SWT 20s UNI T dB

1

05785-016

A

–10

–20

1AP

–30

–40

–50

(dB)

–60

–70

–80

–90

–100

05785-014

CENTER 75.1MHz SPAN 1MHz100kHz/DIV

Figure 17. f

= 75.1 MHz, f

OUT

CLK

= 500 MSPS, NBSFDR, ±1 MHz

1

05785-017

0

REF LVL 0dBm

DELTA 1 (T1) –82.63dB

400.80160321kHz

–10

–20

–30

–40

–50

(dB)

–60

–70

–80

–90

–100

CENTER 100.3MHz SPAN 1MHz100kHz/DIV

Figure 15. f

= 100.3 MHz, f

OUT

RBW 500Hz RF ATT 20d VBW 500Hz SWT 20s UNIT dB

1

= 500 MSPS, NBSFDR, ±1 MHz

CLK

A

1AP

05785-015

Rev. 0 | Page 13 of 44

–10

0

REF LVL 0dBm

DELTA 1 (T1) –83.72dB –400.80160321kHz

RBW 500Hz RF ATT 20dB VBW 500Hz SWT 20s UNIT dB

1

–20

–30

–40

–50

(dB)

–60

–70

–80

–90

–100

1

CENTER 200.3MHz SPAN 1MHz

Figure 18. f

= 200.3MHz, f

OUT

100kHz/DIV

= 500 MSPS, NBSFDR, ±1 MHz

CLK

1AP

A

05785-018

AD9911

–

100

235

–110

–120

–130

–140

–150

PHASE NOISE (dBc/Hz)

–160

–170

Figure 19. Residual Phase Noise (SSB) with f

75.1 MHz, 100.3 MHz, f

–80

–90

–100

–110

–120

–130

–140

PHASE NOISE (dBc/Hz)

–150

–160

–170

Figure 20. Residual Phase Noise (SSB) with f

75.1 MHz, 100.3 MHz, f

75.1MHz

100.3MHz

40.1MHz

15.1MHz

10 100 1k 10k 100k 1M 10M

FREQUENCY O FFSET (Hz)

= 15.1 MHz, 40.1 MHz,

= 500 MHz with REF_CLK Multiplier Bypassed

CLK

70

100.3MHz

75.1MHz

40.1MHz

15.1MHz

100 1k 10k 100k 1M

10 10M

FREQUENCY OFFSET (Hz)

= 500 MHz with REF_CLK Multiplier = 5×

CLK

OUT

= 15.1 MHz, 40.1 MHz,

OUT

215

195

175

155

POWER (mW)

135

115

95

75

100 500

150 200 250 300 350 400 450

05785-019

CLOCK FREQUENCY (MHz)

5785-022

Figure 22. Power vs. System Clock Frequency

0

–10

–20

–30

–40

–50

(dB)

–60

–70

–80

–90

–100

05785-020

CENTER 50.17407705MHz SPAN 15MHz

1

1.5MHz/

05785-057

Figure 23. Amplitude Modulation Using Primary Channel

(CH1 = 50 MHz) and One Auxiliary Channel (CH0 = 1 MHz)

70

–80

–90

–100

–110

–120

–130

–140

PHASE NOISE (dBc/Hz)

–150

–160

–170

10 10M

40.1MHz

100 1k 10k 100k 1M

100.3MHz

15.1MHz

FREQUENCY OFFSET (Hz)

Figure 21. Residual Phase Noise(SSB) with f

75.1 MHz, 100.3 MHz, f

= 500 MHz with REF_CLK Multiplier = 20×

CLK

75.1MHz

= 15.1 MHz, 40.1 MHz,

OUT

05785-021

Figure 24. Two-Tone Generation Using Primary Channel (CH1 = 10.1 MHz)

Rev. 0 | Page 14 of 44

0

–10

–20

–30

–40

–50

(dB)

–60

–70

–80

–90

–100

CENTER 10.2MHz SPAN 750kHz

1

75kHz/

and One Auxiliary Channel (CH0 = 10.3 MHz)

05785-058

ANALOG DEVICES AD9911 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

FUNCTIONAL BLOCK DIAGRAM

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

EQUIVALENT INPUT AND OUTPUT CIRCUITS

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS