ANALOG DEVICES AD9910 Service Manual

Direct Digital Synthesizer

AD9910

Rev. D

Analog Devices is believed to be accurate and reliable. However, no

Trademarks and registered trademarks are the property of their respective owners.

14-BIT DAC

1GSPS DDS CO RE

LINEAR

RAMP

GENERATOR

1024-

ELEMENT

RAM

HIGH SPEED PARALLEL

DATA INTERFACE

TIMINGAND CONTROL

SERIAL CONTROL

DATA PORT

REFCLK

MULTIPLIER

06479-001

AD9910

Data Sheet

FEATURES

1 GSPS internal clock speed (up to 400 MHz analog output) Integrated 1 GSPS, 14-bit DAC

0.23 Hz or better frequency resolution Phase noise ≤ −125 dBc/Hz @ 1 kHz offset (400 MHz carrier) Excellent dynamic performance with

>80 dB narrow-band SFDR Serial input/output (I/O) control Automatic linear or arbitrary frequency, phase, and

amplitude sweep capability 8 frequency and phase offset profiles Sin(x)/(x) correction (inverse sinc filter)

1.8 V and 3.3 V power supplies Software and hardware controlled power-down 100-lead TQFP_EP package Integrated 1024 word × 32-bit RAM PLL REFCLK multiplier Parallel datapath interface Internal oscillator can be driven by a single crystal Phase modulation capability Amplitude modulation capability Multichip synchronization

1 GSPS, 14-Bit, 3.3 V CMOS

APPLICATIONS

Agile local oscillator (LO) frequency synthesis Programmable clock generators FM chirp source for radar and scanning systems Test and measurement equipment Acousto-optic device drivers Polar modulators Fast frequency hopping

FUNCTIONAL BLOCK DIAGRAM

Information furnishe d by responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Figure 1.

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www.analog.com

AD9910 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

External PLL Loop Filter Components ............................... 27

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 4

General Description ......................................................................... 5

Specifications ..................................................................................... 6

Electrical Specifications ............................................................... 6

Absolute Maximum Ratings ............................................................ 9

Equivalent Circuits ....................................................................... 9

ESD Caution .................................................................................. 9

Pin Configuration and Function Descriptions ........................... 10

Typical Performance Characteristics ........................................... 13

Application Circuits ....................................................................... 16

Theory of Operation ...................................................................... 17

Single Tone Mode ....................................................................... 17

RAM Modulation Mode ............................................................ 18

PLL Lock Indication .................................................................. 27

Output Shift Keying (OSK) ....................................................... 27

Manual OSK ............................................................................ 27

Automatic OSK ....................................................................... 28

Digital Ramp Generator (DRG) ............................................... 28

DRG Overview ....................................................................... 28

DRG Slope Control ................................................................ 30

DRG Limit Control ................................................................ 30

DRG Accumulator Clear ....................................................... 30

Normal Ramp Generation .................................................... 30

No-Dwell Ramp Generation ................................................. 32

DROVER Pin .......................................................................... 32

RAM Control .............................................................................. 33

RAM Overview....................................................................... 33

Load/Retrieve RAM Operation ............................................ 33

Digital Ramp Modulation Mode .............................................. 19

Parallel Data Port Modulation Mode ....................................... 20

Parallel Data Clock (PDCLK) ............................................... 20

Transmit Enable (TxENABLE) ............................................. 21

Mode Priority .............................................................................. 22

Functional Block Detail ................................................................. 23

DDS Core ..................................................................................... 23

14-Bit DAC Output .................................................................... 23

Auxiliary DAC ........................................................................ 24

Inverse Sinc Filter ....................................................................... 24

Clock Input (REF_CLK/

REF_CLK/

Crystal Driven REF_CLK/

Direct Driven REF_CLK/

Phase-Locked Loop (PLL) Multiplier .................................. 25

REF_CLK

Overview ........................................... 24

) ........................................ 24

REF_CLK

.................................. 25

.................................... 25

RAM Playback Operation (Waveform Generation) .......... 33

RAM_SWP_OVR (RAM Sweep Over) Pin ........................ 34

Overview of RAM Playback Modes .................................... 34

RAM Direct Switch Mode ..................................................... 34

RAM Direct Switch Mode with Zero Crossing .................. 35

RAM Ramp-Up Mode ........................................................... 35

RAM Ramp-Up Internal Profile Control Mode ................ 36

Internal Profile Control Continuous Waveform Timing

Diagram ................................................................................... 38

RAM Bidirectional Ramp Mode .......................................... 38

RAM Continuous Bidirectional Ramp Mode .................... 39

RAM Continuous Recirculate Mode ................................... 41

Additional Features ........................................................................ 42

Profiles ......................................................................................... 42

I/O_UPDATE, SYNC_CLK, and System Clock

Relationships ............................................................................... 42

PLL Charge Pump .................................................................. 26

Rev. D | Page 2 of 64

Automatic I/O Update ............................................................... 43

Data Sheet AD9910

Power-Down Control ................................................................. 43

SDO—Serial Data Out ........................................................... 48

Synchronization of Multiple Devices ............................................ 44

Power Supply Partitioning ............................................................. 47

3.3 V Supplies .............................................................................. 47

DVDD_I/O (3.3 V) (Pin 11, Pin 15, Pin 21, Pin 28, Pin 45,

Pin 56, and Pin 66) .................................................................. 47

AVDD (3.3 V) (Pin 74 to Pin 77 and Pin 83) ...................... 47

1.8 V Supplies .............................................................................. 47

DVDD (1.8 V) (Pin 17, Pin 23, Pin 30, Pin 47, Pin 57, and

Pin 64) ...................................................................................... 47

AVDD (1.8 V) (Pin 3)............................................................. 47

AVDD (1.8 V) (Pin 6)............................................................. 47

AVDD (1.8 V) (Pin 89 and Pin 92) ....................................... 47

Serial Programming ........................................................................ 48

Control Interface—Serial I/O .................................................... 48

General Serial I/O Operation .................................................... 48

Instruction Byte ........................................................................... 48

Instruction Byte Information Bit Map ................................. 48

Serial I/O Port Pin Descriptions ............................................... 48

SCLK—Serial Clock................................................................ 48

—Chip Select Bar ............................................................... 48

SDIO—Serial Data Input/Output ......................................... 48

I/O_RESET—Input/Output Reset ........................................ 49

I/O_UPDATE—Input/Output Update ................................ 49

Serial I/O Timing Diagrams ...................................................... 49

MSB/LSB Transfers ..................................................................... 49

Control Function Register 1 (CFR1)—Address 0x00 ........ 55

Control Function Register 2 (CFR2)—Address 0x01 ........ 57

Control Function Register 3 (CFR3)—Address 0x02 ........ 58

Auxiliary DAC Control Register—Address 0x03 ............... 58

I/O Update Rate Register—Address 0x04 ........................... 59

Frequency Tuning Word Register (FTW)—Address 0x07 ..... 59

Phase Offset Word Register (POW)—Address 0x08 ......... 59

Amplitude Scale Factor Register (ASF)—Address 0x09 .... 59

Multichip Sync Register—Address 0x0A ............................. 60

Digital Ramp Limit Register—Address 0x0B...................... 60

Digital Ramp Step Size Register—Address 0x0C ............... 60

Digital Ramp Rate Register—Address 0x0D ....................... 60

Profile Registers ...................................................................... 61

Outline Dimensions ........................................................................ 62

Ordering Guide ........................................................................... 62

Rev. D | Page 3 of 64

AD9910 Data Sheet

REVISION HISTORY

5/12—Rev. C to Rev. D

Changes to Table 1 ............................................................................ 8

Changes to Table 3 .......................................................................... 12

Changes to Figure 39 ...................................................................... 31

Changes to Synchronization of Multiple Devices Section ........ 45

Changes to Table 18 ........................................................................ 55

Changes to Table 20 ........................................................................ 58

Changes to Table 26 ........................................................................ 60

8/10—Rev. B to Rev. C

Changes to XTAL_SEL Input Parameter in Table 1 ..................... 8

Changes to Table 2 ............................................................................ 9

Changes to Transmit Enable (TxENABLE) Section .................. 21

12/08—Rev. A to Rev. B

Changes to Figure 2 .......................................................................... 5

Changes to I/O_UPDATE Pulse Width Parameter and

Minimum Profile Toggle Period Parameter in Table 1 ................ 7

Added XTAL_SEL Input Parameter in Table 1............................. 8

Changes to Table 3 .......................................................................... 11

Changes to Figure 20 ...................................................................... 16

Changes to Figure 22 ...................................................................... 17

Changes to Figure 23 ...................................................................... 18

Changes to Figure 24 ...................................................................... 19

Changes to Figure 25 ...................................................................... 20

Changes to REF_CLK/ Changes to Crystal Driven REF_CLK/ Changes to PLL Lock Indication Section and Output Shift

Keying (OSK) Section .................................................................... 27

Changes to DRG Slope Control Section and Normal Ramp

Generation Section ......................................................................... 30

Changes to Drover Pin Section ..................................................... 32

Changes to Figure 43 ...................................................................... 35

Changes to Figure 45 and Internal Profile Control Continuous

Waveform Timing Diagram Section ............................................ 38

Changes to Figure 47 ...................................................................... 40

Changes to Figure 48 ...................................................................... 41

REF_CLK

Overview Section ................. 24

REF_CLK

Section ........ 25

Deleted I/O_UPDATE Pin Section .............................................. 41

Changes to Profiles Section ........................................................... 42

Added I/O_UPDATE, SYNC_CLK, and System Clock

Relationships Section ..................................................................... 42

Added Figure 49; Renumbered Sequentially .............................. 42

Changes to Synchronization of Multiple Devices Section ........ 44

Changes to DVDD (1.8V) (Pin 17, Pin 23, Pin 30, Pin 47, Pin 57, and Pin 64) Section and AVDD (1.8V) (Pin 89 and

Pin 92) Section ................................................................................ 47

Changes to Control Interface—Serial I/O Section .................... 48

Changes to Table 17 ....................................................................... 50

Changes to Table 19 ....................................................................... 57

Changes to Table 20 and Table 21 ................................................ 58

2/08—Rev. 0 to Rev. A

Changes to Features .......................................................................... 1

Changes to REFCLK Multiplier Specification in Table 1 ............. 5

Changes to Minimum Setup Time to SYNC_CLK ....................... 6

Changes to I/O Update/Profile[2:0] Timing Characteristics ...... 6

Changes to TxENABLE/Data Setup Time (to PDCLK) and

TxENABLE/Data Hold Time (to PDCLK) .................................... 6

Changes to Miscellaneous Timing Characteristics ....................... 6

Changes to Table 3 .......................................................................... 10

Changes to Figure 9, Figure 10, Figure 11, Figure 12, Figure 13,

and Figure 14 ................................................................................... 12

Changes to Figure 30 and Table 7................................................. 24

Changes to Automatic I/O Update Section................................. 41

Added Table 16, Renumbered Sequentially ................................ 41

Changes to Figure 49 to Figure 53 ................................................ 43

Added Power Supply Partitioning Section .................................. 46

Changes to General Serial I/O Operation Section ..................... 47

Changes to Table 17 ....................................................................... 49

Changes to Table 19 ....................................................................... 56

Changes to Table 20 ....................................................................... 57

Added Table 32 ............................................................................... 60

5/07—Revision 0: Initial Version

Rev. D | Page 4 of 64

Data Sheet AD9910

06479-002

PARALLEL

INPUT

PDCLK

SCLK

SDIO

I/O_RESET

PROFILE[2:0]

I/O_UPDATE

RAM

POWER-

DOWN

CONTROL

EXT_PWR_DWN

DAC_RSET

IOUT IOUT

TxENABLE

DAC FSC

OSK

RAM_SWP_OVR

INVERSE

SINC

FILTER

CLOCK

AMPLIT UDE ( A)

FREQUENCY (ω)

PHASE (θ)

DIGITAL

RAMP

GENERATOR

DAC FSC

DRCTL

DRHOLD DROVER

MULTICHIP

SYNCHRONIZATION

SYSCLK

PLL

÷2

CLOCK MODE

REF_CLK REF_CLK

REFCLK_OUT

XTAL_SEL

PARALLEL DATA

TIMINGAND

CONTROL

SERIAL I/O PORT

AD9910

PROGRAMMING

REGISTERS

OUTPUT

SHIFT

KEYING

DATA

ROUTE

AND

PARTITION

CONTROL

INTERNAL CLOCK TIMING

AND CONTROL

Acos (ωt + θ)

Asin (ωt + θ)

SYNC_SMP_ERR

SYNC_CLK

SYNC_OUT

SYNC_IN

PLL_LOCK

PLL_LOOP_FILTER

MASTER_RESET

DAC

14-BIT

DDS

AUX DAC

8-BIT

GENERAL DESCRIPTION

The AD9910 is a direct digital synthesizer (DDS) featuring an integrated 14-bit DAC and supporting sample rates up to 1 GSPS. The AD9910 employs an advanced, proprietary DDS technology that provides a significant reduction in power consumption without sacrificing performance. The DDS/DAC combination forms a digitally programmable, high frequency, analog output synthesizer capable of generating a frequency agile sinusoidal waveform at frequencies up to 400 MHz.

The user has access to the three signal control parameters that control the DDS: frequency, phase, and amplitude. The DDS provides fast frequency hopping and frequency tuning resolution with its 32-bit accumulator. With a 1 GSPS sample rate, the tuning resolution is ~0.23 Hz. The DDS also enables fast phase and amplitude switching capability.

The AD9910 is controlled by programming its internal control registers via a serial I/O port. The AD9910 includes an integrated static RAM to support various combinations of frequency, phase, and/or amplitude modulation. The AD9910 also supports a user defined, digitally controlled, digital ramp mode of operation. In this mode, the frequency, phase, or amplitude can be varied linearly over time. For more advanced modulation functions, a high speed parallel data input port is included to enable direct frequency, phase, amplitude, or polar modulation.

The AD9910 is specified to operate over the extended industrial temperature range (see the Absolute Maximum Ratings section for details).

Figure 2. Detailed Block Diagram

Rev. D | Page 5 of 64

AD9910 Data Sheet

REFCLK Input Level

Single-ended

50 1000

mV p-p

Differential

100 2000

mV p-p

OUT

Enabled @ 20×

−140

dBc/Hz

±12.5 kHz

–95 dBc

SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

AVDD (1.8 V) and DVDD (1.8 V) = 1.8 V ± 5%, AVDD (3.3 V) = 3.3 V ± 5%, DVDD_I/O (3.3 V) = 3.3 V ± 5%, T = 25°C, R I

= 20 mA, external reference clock frequency = 1000 MHz with reference clock (REFCLK) multiplier disabled, unless otherwise noted.

OUT

Table 1.

Parameter Conditions/Comments Min Typ Max Unit

REFCLK INPUT CHARACTERISTICS

Frequency Range

REFCLK Multiplier Disabled 60 1000 MHz Enabled 3.2 60 MHz Maximum REFCLK Input Divider Frequency Full temperature range 1500 1900 MHz

Minimum REFCLK Input Divider Frequency Full temperature range 25 35 MHz External Crystal 25 MHz Input Capacitance 3 pF Input Impedance Differential 2.8 kΩ Single-ended 1.4 kΩ Duty Cycle REFCLK multiplier disabled 45 55 % REFCLK multiplier enabled 40 60 %

= 10 kΩ,

SET

REFCLK MULTIPLIER VCO CHARACTERISTICS

VCO Gain (KV) @ Center Frequency VCO range Setting 0 429 MHz/V

VCO range Setting 1 500 MHz/V VCO range Setting 2 555 MHz/V VCO range Setting 3 750 MHz/V VCO range Setting 4 789 MHz/V VCO range Setting 51 850 MHz/V REFCLK_OUT CHARACTERISTICS

Maximum Capacitive Load 20 pF Maximum Frequency 25 MHz

DAC OUTPUT CHARACTERISTICS

Full-Scale Output Current 8.6 20 31.6 mA Gain Error −10 +10 % FS Output Offset 2.3 µA Differential Nonlinearity 0.8 LSB Integral Nonlinearity 1.5 LSB Output Capacitance 5 pF Residual Phase Noise @ 1 kHz offset, 20 MHz A

REFCLK Multiplier Disabled −152 dBc/Hz

Enabled @ 100× −140 dBc/Hz Voltage Compliance Range −0.5 +0.5 V Wideband SFDR See the Typical Performance

Characteristics section

Narrow-Band SFDR

50.1 MHz Analog Output ±500 kHz –87 dBc

±125 kHz –87 dBc

±12.5 kHz –96 dBc

101.3 MHz Analog Output ±500 kHz –87 dBc

±125 kHz –87 dBc

Rev. D | Page 6 of 64

Data Sheet AD9910

±125 kHz

–86 dBc

Maximum SCLK Rise/Fall Time

2 ns

Minimum Setup Time to SYNC_CLK

Minimum Hold Time to SYNC_CLK

0 ns

I/O_UPDATE Pulse Width

High

SYNC_CLK cycle

Minimum Profile Toggle Period

2 SYNC_CLK cycles

Wake-Up Time2

Fast Recovery

8 SYSCLK cycles3

Full Sleep Mode

REFCLK multiplier enabled

1 ms

REFCLK multiplier disabled

150

μs

Frequency, Phase-to-DAC Output

Matched latency enabled/disabled

91 SYSCLK cycles3

Parameter Conditions/Comments Min Typ Max Unit

201.1 MHz Analog Output ±500 kHz –87 dBc ±125 kHz –87 dBc ±12.5 kHz –91 dBc

301.1 MHz Analog Output ±500 kHz –86 dBc

±12.5 kHz –88 dBc

401.3 MHz Analog Output ±500 kHz –84 dBc ±125 kHz –84 dBc ±12.5 kHz –85 dBc

SERIAL PORT TIMING CHARACTERISTICS

Maximum SCLK Frequency 70 Mbps Minimum SCLK Clock Pulse Width Low 4 ns

High 4 ns

Minimum Data Setup Time to SCLK 5 ns Minimum Data Hold Time to SCLK 0 ns Maximum Data Valid Time in Read Mode 11 ns

I/O_UPDATE/PROFILE[2:0] TIMING

CHARACTERISTICS

1.75

TxENABLE and 16-BIT PARALLEL (DATA) BUS TIMING

Maximum PDCLK Frequency 250 MHz TxENABLE/Data Setup Time (to PDCLK) 1.75 ns TxENABLE/Data Hold Time (to PDCLK) 0 ns

MISCELLANEOUS TIMING CHARACTERISTICS

Minimum Reset Pulse Width High 5 SYSCLK cycles3

DATA LATENCY (PIPELINE DELAY )

Data Latency, Single Tone or Using Profiles

Frequency, Phase, Amplitude-to-DAC Output Matched latency enabled and OSK

enabled

Frequency, Phase-to-DAC Output Matched latency enabled and OSK

disabled Matched latency disabled 79 SYSCLK cycles3 Amplitude-to-DAC Output Matched latency disabled 47 SYSCLK cycles3

Data Latency Using RAM Mode

Frequency, Phase-to-DAC Output Matched latency enabled/disabled 94 SYSCLK cycles3 Amplitude-to-DAC Output Matched latency enabled 106 SYSCLK cycles3 Matched latency disabled 58 SYSCLK cycles3

Data Latency, Sweep Mode

Amplitude-to-DAC Output Matched latency enabled 91 SYSCLK cycles3 Matched latency disabled 47 SYSCLK cycles3

Data Latency, 16-Bit Input Modulation Mode

Frequency, Phase-to-DAC Output Matched latency enabled 103 SYSCLK cycles3 Matched latency disabled 91 SYSCLK cycles3

91 SYSCLK cycles3

79 SYSCLK cycles3

Rev. D | Page 7 of 64

AD9910 Data Sheet

Logic 0 Current

150

µA

CMOS LOGIC OUTPUTS

1 mA load

AVDD

DVDD

Full Sleep Mode

Parameter Conditions/Comments Min Typ Max Unit

CMOS LOGIC INPUTS

Logic 1 Voltage 2.0 V Logic 0 Voltage 0.8 V Logic 1 Current 90 150 µA

Input Capacitance 2 pF

XTAL_SEL INPUT

Logic 1 Voltage 1.25 V Logic 0 Voltage 0.6 V Input Capacitance 2 pF

Logic 1 Voltage 2.8 V Logic 0 Voltage 0.4 V

POWER SUPPLY CURRENT

(1.8 V) 110 mA

(3.3 V) 29 mA

(1.8 V) 222 mA

(3.3 V) 11 mA

TOTAL POWER CONSUMPTION

Single Tone Mode 715 950 mW Rapid Power-Down Mode 330 450 mW

The gain value for VCO range Setting 5 is measured at 1000 MHz.

Wake-up time refers to the recovery time from a power-down state. The longest time required is for the reference clock multiplier PLL to relock to the reference. The

wake-up time assumes that the recommended PLL loop filter values are used.

SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency,

the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier is not used, the SYSCLK frequency is the same as the external reference clock frequency.

Rev. D | Page 8 of 64

Data Sheet AD9910

Digital Output Current

5 mA

Lead Temperature (10 sec Soldering)

300°C

06479-003

MUST TERMINATE OUTPUTSTO AGND FOR CURRENT FLOW. DO NOT EXCEED THE OUTPUT VOLTAGE COMPLIANCE RATING.

IOUT IOUT

DAC OUTPUTS

AVDD

AVOID OVERDRIVING DIGITAL INPUTS. FORWARD BIASING ESD DIODES M AY COUPLE DIGITAL NOISE ONTO POWER PINS.

DIGITAL INPUTS

INPUT

DVDD_I/O

06479-055

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

AVDD (1.8V), DVDD (1.8V) Supplies 2 V AVDD (3.3V), DVDD_I/O (3.3V) Supplies 4 V Digital Input Voltage −0.7 V to +4 V XTAL_SEL −0.7 V TO +2.2 V

Storage Temperature Range −65°C to +150°C Operating Temperature Range −40°C to +85°C θJA 22°C/W θJC 2.8°C/W Maximum Junction Temperature 150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

EQUIVALENT CIRCUITS

Figure 3. Equivalent Input Circuit

Figure 4. Equivalent Output Circuit

ESD CAUTION

Rev. D | Page 9 of 64

AD9910 Data Sheet

2627282930

55 54 53 52 51

TQFP-100 ( E _PAD)

TOP VIEW

(Not to S cal e)

AD9910

D14

D13

DVDD_I/O ( 3.3V)

DGND

DVDD (1.8V)

343536

414243

4445464748

D12

D11

D10

D9D8D7D6D5

PDCLK

TxENABLE

DGND

D3D2D1

DVDD_I/O ( 3.3V)

DVDD (1.8V)

IOUT79AGND78AGND77AVDD (3.3V)76AVDD (3.3V)

AVDD (3.3V)

AGND

I/O_RESET

SCLK

SDO

SDIO

DVDD_I/O ( 3.3V)

DGND

DVDD (1.8V)

DRHOLD

DRCTL

DROVER

OSK

I/O_UPDATE

DGND

DVDD (1.8V)

DVDD_I/O ( 3.3V) SYNC_CLK

PROFILE0 PROFILE1

PROFILE2 DGND

100

99989796959493

929190

8786858483

NCNCNCNCAGND

XTAL_SEL

REFCLK_OUTNCAVDD (1.8V)

REF_CLK

AVDD (1.8V)

AGNDNCNC

AGND

DAC_RSET

AVDD (3.3V)

AGND

IOUT

PLL_LOOP_FILTER

AVDD (1.8V)

AGND AGND

AVDD (1.8V)

SYNC_IN+ SYNC_IN–

SYNC_OUT+

SYNC_OUT–

DVDD_I/O ( 3.3V)

SYNC_SMP_ERR

DGND

MASTER_RESET

DVDD_I/O ( 3.3V)

DGND

DVDD (1.8V)

EXT_PWR_DWN

PLL_LOCK

DVDD_I/O ( 3.3V)

DGND

DVDD (1.8V)

RAM_SWP_OVR

D15

06479-004

PIN 1 INDICATOR

NOTES:

1. EXPOSED PAD SHOULD BE SOLDERED TO GROUND.

2. NC = NO CONNEC T.

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 5. Pin Configuration

Rev. D | Page 10 of 64

Data Sheet AD9910

SYNC_IN+

Synchronization Signal (LVDS), Digital Input (Rising Edge Active). The synchronization

EXT_PWR_DWN

External Power-Down, Digital Input (Active High). A high level on this pin initiates the 41

TxENABLE

Transmit Enable. Digital input (active high). In burst mode communications, a high on this

Table 3. Pin Function Descriptions

Pin No. Mnemonic I/O1 Description

1, 20, 72, 86, 87, 93, 97 to 100

2 PLL_LOOP_FILTER I PLL Loop Filter Compensation Pin. See the External PLL Loop Filter Components section for

3, 6, 89, 92 AVDD (1.8V) I Analog Core VDD, 1.8 V Analog Supplies. 74 to 77, 83 AVDD (3.3V) I Analog DAC VDD, 3.3 V Analog Supplies. 17, 23, 30, 47,

57, 64 11, 15, 21, 28, 45,

56, 66 4, 5, 73, 78, 79, 82,

85, 88, 96 13, 16, 22, 29, 46,

51, 58, 65

8 SYNC_IN− I Synchronization Signal (LVDS), Digital Input. The synchronization signal from the external

9 SYNC_OUT+ O Synchronization Signal (LVDS), Digital Output (Rising Edge Active). The synchronization

10 SYNC_OUT− O Synchronization Signal (LVDS), Digital Output. The synchronization signal from the internal

12 SYNC_SMP_ERR O Synchronization Sample Error, Digital Output (Active High). Sync sample error: a high on

14 MASTER_RESET I Master Reset, Digital Input (Active High). Master reset: clears all memory elements and sets

NC Not Connected. Allow device pins to float.

details.

DVDD (1.8V) I Digital Core VDD, 1.8 V Digital Supplies.

DVDD_I/O (3.3V) I Digital Input/Output VDD, 3.3 V Digital Supplies.

AGND I Analog Ground.

DGND I Digital Ground.

signal from the external master to synchronize internal subclocks. See the Synchronization of Multiple Devices section for details.

master to synchronize internal subclocks. See the Synchronization of Multiple Devices section for details.

signal from the internal device subclocks to synchronize external slave devices. See the Synchronization of Multiple Devices section for details.

device subclocks to synchronize external slave devices. See the Synchronization of Multiple Devices section for details.

this pin indicates that the AD9910 did not receive a valid sync signal on SYNC_IN+/SYNC_IN−.

registers to default values.

currently programmed power-down mode. See the Power-Down Control section for further details. If unused, connect to ground.

19 PLL_LOCK O Clock Multiplier PLL Lock, Digital Output (Active High). A high on this pin indicates that the

Clock Multiplier PLL has acquired lock to the reference clock input.

24 RAM_SWP_OVR O RAM Sweep Over, Digital Output (Active High). A high on this pin indicates that the RAM

sweep profile has completed.

25 to 27, 31 to 39, 42 to 44, 48

49, 50 F[1:0] I Modulation Format Pins. Digital input to determine the modulation format. 40 PDCLK O Parallel Data Clock. This is the digital output (clock). The parallel data clock provides a

52 to 54 PROFILE[2:0] I Profile Select Pins. Digital inputs (active high). Use these pins to select one of eight

55 SYNC_CLK O Output Clock Divided-By-Four. A digital output (clock). Many of the digital inputs on the

D[15:0] I Parallel Input Bus (Active High).

timing signal for aligning data at the parallel inputs.

pin indicates new data for transmission. In continuous mode, this pin remains high.

phase/frequency profiles for the DDS. Changing the state of one of these pins transfers the current contents of all I/O buffers to the corresponding registers. State changes should be set up on the SYNC_CLK pin.

chip, such as I/O_UPDATE and PROFILE[2:0], need to be set up on the rising edge of this signal.

Rev. D | Page 11 of 64

AD9910 Data Sheet

DRCTL

Digital Ramp Control. Digital input (active high). This pin controls the slope polarity of the

a Clock. Digital clock (rising edge on write, falling edge on read). This pin provides

Pin No. Mnemonic I/O1 Description

59 I/O_UPDATE I/O Input/Output Update. Digital input (active high). A high on this pin transfers the contents

of the I/O buffers to the corresponding internal registers.

60 OSK I Output Shift Keying. Digital input (active high). When the OSK features are placed in either

manual or automatic mode, this pin controls the OSK function. In manual mode, it toggles the multiplier between 0 (low) and the programmed amplitude scale factor (high). In automatic mode, a low sweeps the amplitude down to zero, a high sweeps the amplitude up to the amplitude scale factor.

61 DROVER O Digital Ramp Over. Digital output (active high). This pin switches to Logic 1 whenever the

digital ramp generator reaches its programmed upper or lower limit.

digital ramp generator. See the Digital Ramp Generator (DRG) section for more details. If not using the digital ramp generator, connect this pin to Logic 0.

63 DRHOLD I Digital Ramp Hold. Digital input (active high). This pin stalls the digital ramp generator in

its present state. See the Digital Ramp Generator (DRG) section for more details. If not using a digital ramp generator, connect this pin to Logic 0.

67 SDIO I/O Serial Data Input/Output. Digital input/output (active high). This pin can be either unidirec-

tional or bidirectional (default), depending on the configuration settings. In bidirectional serial port mode, this pin acts as the serial data input and output. In unidirectional mode, it is an input only.

68 SDO O Serial Data Output. Digital output (active high). This pin is only active in unidirectional

serial data mode. In this mode, it functions as the output. In bidirectional mode, this pin is not operational and should be left floating.

69 SCLK I Serial Dat

the serial data clock for the control data path. Write operations to the AD9910 use the rising edge. Readback operations from the AD9910 use the falling edge.

71 I/O_RESET I Input/Output Reset. Digital input (active high). This pin can be used when a serial I/O

81 IOUT O Open-Drain DAC Output Source. Analog output (current mode). Connect through a 50 Ω

84 DAC_RSET O Analog Reference Pin. This pin programs the DAC output full-scale reference current.

90 REF_CLK I Reference Clock Input. Analog input. When the internal oscillator is engaged, this pin can

91 94 REFCLK_OUT O Crystal Output. Analog output. See the REF_CLK/ Overview section for more details.

95 XTAL_SEL I Crystal Select (1.8 V Logic). Analog input (active high). Driving the XTAL_SEL pin high,

EPAD Exposed Paddle

I = input, O = output.

I Chip Select. Digital input (active low). This pin allows the AD9910 to operate on a common

O Open-Drain DAC Complementary Output Source. Analog output (current mode). Connect

IOUT

REF_CLK

(EPAD)

I Reference Clock Input. Analog input. See the REF_CLK/ Overview section for more details.

serial bus for the control data path. Bringing this pin low enables the AD9910 to detect serial clock rising/falling edges. Bringing this pin high causes the AD9910 to ignore input on the serial data pins.

communication cycle fails (see the I/O_RESET—Input/Output Reset section for details). When not used, connect this pin to ground.

through a 50 Ω resistor to AGND.

resistor to AGND.

Attach a 10 kΩ resistor to AGND.

be driven by either an external oscillator or connected to a crystal. See the REF_CLK/ Overview section for more details.

the AVDD (1.8V) pin enables the internal oscillator to be used with a crystal resonator. If unused, connect it to AGND.

The EPAD should be soldered to ground.

Rev. D | Page 12 of 64

Data Sheet AD9910

–50

–55

–60

–65

–75

–70

06479-034

SFDR (dBc)

OUTPUT FREQUENCY (MHz )

SFDR WITHOUT PLL

SFDR WITH PLL

0 50 100 150 200 250 300 350 400

400 450300250 350200150100500

06479-046

SFDR (dBc)

OUTPUT FREQUENCY (MHz )

–75

–70

–65

–60

–55

–45

–50

LOW SUPPLY

HIGH SUPPLY

400 450300250 350200150100500

06479-047

SFDR (dBc)

OUTPUT FREQUENCY (MHz )

–75

–70

–65

–60

–55

–50

–40°C

+85°C

START 0Hz

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

50MHz/DIV ST OP 500MHz

06479-035

SFDR (dBc)

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

START 0Hz 50MHz/DIV ST OP 500MHz

06479-036

SFDR (dBc)

06479-037

START 0Hz

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

50MHz/DIV ST OP 500MHz

SFDR (dBc)

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 6. Wideband SFDR vs. Output Frequency

(PLL with Reference Clock = 15.625 MHz × 64)

Figure 7. Wideband SFDR vs. Output Frequency and Supply (±5%),

REFCLK = 1 GHz

Figure 9. Wideband SFDR at 10 MHz, REFCLK = 1 GHz

Figure 10. Wideband SFDR at 204 MHz, REFCLK = 1 GHz

Figure 8. Wideband SFDR vs. Output Frequency and Temperature,

REFCLK = 1 GHz

Figure 11. Wideband SFDR at 403 MHz, REFCLK = 1 GHz

Rev. D | Page 13 of 64

AD9910 Data Sheet

06479-038

CENTER 10.32MHz

–120

–108

–96

–84

–72

–60

–48

–36

–24

–12

2.5kHz/DIV SPAN 25kHz

SFDR (dBc)

06479-039

CENTER 204.36MHz

–120

–108

–96

–84

–72

–60

–48

–36

–24

–12

2.5kHz/DIV SPAN 25kHz

SFDR (dBc)

06479-040

CENTER 403.78MHz

–120

–108

–96

–84

–72

–60

–48

–36

–24

–12

2.5kHz/DIV SPAN 25kHz

SFDR (dBc)

–90

–100

–120

–110

–140

–150

–130

–170

–160

10 100 1k

10k 100k 100M1M 10M

06479-042

MAGNITUDE ( dBc/Hz)

FREQUENCY OFFSET (Hz)

OUT

= 20.1MHz

OUT

= 98.6MHz

OUT

= 201.1MHz

OUT

= 397.8MHz

Figure 12. Narrow-Band SFDR at 10.32 MHz, REFCLK = 1 GHz

Figure 13. Narrow-Band SFDR at 204.36 MHz, REFCLK = 1 GHz

Figure 14. Narrow-Band SFDR at 403.78 MHz, REFCLK = 1 GHz

Figure 15. Residual Phase Noise Plot, 1 GHz Operation with PLL Disabled

Rev. D | Page 14 of 64

Data Sheet AD9910

–90

–100

–110

–120

–130

–140

–150

–160

10 100 1k 10k 100k 1M 10M

100M

06479-043

MAGNITUDE ( dBc/ Hz)

FREQUENCY OFFSET (Hz)

OUT

= 20.1MHz

OUT

= 397.8MHz

OUT

= 98.6MHz

OUT

= 201.1MHz

400

450

300

250

350

200

150

100

100 200 300 400 500 600 700 800 900 1000

06479-044

POWER DISSIPATION (mW)

SYSTEM CLOCK FREQUENCY (MHz)

DVDD 3.3V

AVDD 3.3V

AVDD 1.8V

DVDD 1.8V

400

450

300

250

350

200

150

100

400 500 600 700 800 900 1000

06479-045

POWER DISSIPATION (mW)

SYSTEM CLOCK FREQUENCY (MHz)

DVDD 1.8V

AVDD 1.8V

AVDD 3.3V

DVDD 3.3V

1 GHz Operation Using a 50 MHz Reference Clock with 20× PLL Multiplier

Figure 16. Residual Phase Noise,

Figure 17. Power Dissipation vs. System Clock Frequency (PLL Disabled)

Figure 18. Power Dissipation vs. System Clock Frequency (PLL Enabled)

Rev. D | Page 15 of 64

AD9910 Data Sheet

LOOP

FILTER

PHASE

COMPARATOR

VCO

AD9910

REF_CLK

REFERENCE

CHARGE

PUMP

AD9510,AD9511, ADF4106

06479-056

LPF

AD9910

(SLAVE 1)

AD9910

(MASTER)

CLOCK

SOURCE

AD9910

(SLAVE 2)

AD9910

(SLAVE 3)

FPGA

DATA

SYNC_CLK

REF_CLK

SYNC_CLK

FPGA

DATA

FPGA

DATA

FPGA

SYNC_CLK

A_END

CENTRAL CONTROL

AD9510

CLOCK DISTRIBUTOR

WITH

DELAY EQUALIZATION

SYNC_OUT

AD9510

SYNCHRONIZATION

DELAY EQUALIZATION

06479-058

AD9910

REFCLK

PROGRAMMABLE 1 TO 32

DIVIDER AND DELAYADJUST

CLOCK OUT P UT

SELECTION(S)

n = DEPENDENT ON PRODUCT SELECTIO N.

AD9515 AD9514 AD9513 AD9512

LVPECL

LVDS

CMOS

CH 2

06479-057

LPF

APPLICATION CIRCUITS

Figure 19. DDS in PLL Feedback Locking to Reference, Offering Fine Frequency and Delay Adjust Tuning

Figure 20. Synchronizing Multiple Devices to Increase Channel Capacity Using the AD9510 as a Clock Distributor for the Reference and Synchronization Clock

Figure 21. Clock Generation Circuit Using the AD9512/AD9513/AD9514/AD9515 Series of Clock Distribution Chips

Rev. D | Page 16 of 64

Data Sheet AD9910

06479-005

PARALLEL

INPUT

PDCLK

SCLK

SDIO

I/O_RESET

PROFILE[2:0]

I/O_UPDATE

RAM

POWER-

DOWN

CONTROL

EXT_PWR_DWN

DAC_RSET

IOUT IOUT

TxENABLE

DAC FSC

OSK

INVERSE

SINC

FILTER

CLOCK

AMPLIT UDE ( A)

FREQUENCY (ω)

PHASE (θ)

DIGITAL

RAMP

GENERATOR

DAC FSC

MULTICHIP

SYNCHRONIZATION

SYSCLK

PLL

÷2

CLOCK MODE

REF_CLK REF_CLK

REFCLK_OUT

XTAL_SEL

PARALLEL DATA

TIMINGAND

CONTROL

SERIAL I/O PORT

AD9910

PROGRAMMING

REGISTERS

OUTPUT

SHIFT

KEYING

DATA

ROUTE

AND

PARTITION

CONTROL

INTERNAL CLOCK TIMING

AND CONTROL

Acos (ωt + θ)

Asin (ωt + θ)

SYNC_SMP_ERR

SYNC_OUT

SYNC_IN

PLL_LOCK

PLL_LOOP_FILTER

MASTER_RESET

AUX DAC 8-BIT

DAC

14-BIT

DDS

RAM_SWP_OVR

DRCTL DRHOLD DROVER

SYNC_CLK

THEORY OF OPERATION

The AD9910 has four modes of operation.

• Single tone

• RAM modulation

• Digital ramp modulation

• Parallel data port modulation

The modes relate to the data source used to supply the DDS with its signal control parameters: frequency, phase, or amplitude. The partitioning of the data into different combinations of frequency, phase, and amplitude is handled automatically based on the mode and/or specific control bits.

In single tone mode, the DDS signal control parameters come directly from the programming registers associated with the serial I/O port. In RAM modulation mode, the DDS signal control parameters are stored in the internal RAM and played back upon command. In digital ramp modulation mode, the DDS signal control parameters are delivered by a digital ramp generator. In parallel data port modulation mode, the DDS signal control parameters are driven directly into the parallel port.

A separate output shift keying (OSK) function is also available. This function employs a separate digital linear ramp generator that only affects the amplitude parameter of the DDS. The OSK function has priority over the other data sources that can drive the DDS amplitude parameter. As such, no other data source can drive the DDS amplitude when the OSK function is enabled.

Although the various modes (including the OSK function) are described independently, they can be enabled simultaneously. This provides an unprecedented level of flexibility for generating complex modulation schemes. However, to avoid multiple data sources from driving the same DDS signal control parameter, the device has a built-in priority protocol (see Ta b l e 5 in the Mode Priority section).

SINGLE TONE MODE

In single tone mode, the DDS signal control parameters are supplied directly from the programming registers. A profile is an independent register that contains the DDS signal control parameters. Eight profile registers are available.

The various modulation modes generally operate on only one of the DDS signal control parameters (two in the case of the polar modulation format). The unmodulated DDS signal control parameters are stored in their appropriate programming registers and automatically route to the DDS based on the selected mode.

Each profile is independently accessible. Use the three external profile pins (PROFILE[2:0]) to select the desired profile. A change in the state of the profile pins with the next rising edge on SYNC_CLK updates the DDS with the parameters specified by the selected profile.

Figure 22. Single Tone Mode

Rev. D | Page 17 of 64

AD9910 Data Sheet

06479-006

PARALLEL

INPUT

PDCLK

SCLK

SDIO

I/O_RESET

PROFILE[2:0]

I/O_UPDATE

RAM

EXT_PWR_DWN

DAC_RSET

IOUT IOUT

TxENABLE

DAC FSC

OSK

INVERSE

SINC

FILTER

CLOCK

AMPLIT UDE ( A)

FREQUENCY (ω)

PHASE (θ)

DIGITAL

RAMP

GENERATOR

DAC FSC

MULTICHIP

SYNCHRONIZATION

SYSCLK

PLL

÷2

CLOCK MODE

REF_CLK REF_CLK

REFCLK_OUT

XTAL_SEL

PARALLEL DATA

TIMINGAND

CONTROL

SERIAL I/O PORT

AD9910

PROGRAMMING

REGISTERS

OUTPUT

SHIFT

KEYING

DATA

ROUTE

AND

PARTITION

CONTROL

INTERNAL CLOCK TIMING

AND CONTROL

Acos (ωt + θ)

Asin (ωt + θ)

SYNC_SMP_ERR

SYNC_OUT

SYNC_IN

PLL_LOCK

PLL_LOOP_FILTER

MASTER_RESET

DDS

AUX DAC

8-BIT

DAC

14-BIT

RAM_SWP_OVR

DRCTL

DRHOLD DROVER

SYNC_CLK

POWER-

DOWN

CONTROL

RAM MODULATION MODE

The RAM modulation mode (see Figure 23) is activated via the RAM enable bit and assertion of the I/O_UPDAT E pin (or a profile change). In this mode, the modulated DDS signal control parameters are supplied directly from RAM.

The RAM consists of 32-bit words and is 1024 words deep. Coupled with a sophisticated internal state machine, the RAM provides a very flexible method for generating arbitrary, time dependent waveforms. A programmable timer controls the rate at which words are extracted from the RAM for delivery to the DDS. Thus, the programmable timer establishes a sample rate at which 32-bit samples are supplied to the DDS.

The selection of the specific DDS signal control parameters that serve as the destination for the RAM samples is also programmable through eight independent RAM profile registers. Select a particular profile using the three external profile pins (PROFILE[2:0]). A change in the state of the profile pins with the next rising edge on SYNC_CLK activates the selected RAM profile.

In RAM modulation mode, the ability to generate a time dependent amplitude, phase, or frequency signal enables modulation of any one of the parameters controlling the DDS carrier signal. Furthermore, a polar modulation format is available that partitions each RAM sample into a magnitude and phase component; 16 bits are allocated to phase and 14 bits are allocated to magnitude.

Figure 23. RAM Modulation Mode

Rev. D | Page 18 of 64

Data Sheet AD9910

06479-007

PARALLEL

INPUT

PDCLK

SCLK

SDIO

I/O_RESET

PROFILE[2:0]

I/O_UPDATE

RAM

EXT_PWR_DWN

DAC_RSET

IOUT IOUT

TxENABLE

DAC FSC

OSK

INVERSE

SINC

FILTER

CLOCK

AMPLIT UDE ( A)

FREQUENCY (ω)

PHASE (θ)

DIGITAL

RAMP

GENERATOR

DAC FSC

MULTICHIP

SYNCHRONIZATION

SYSCLK

PLL

÷2

CLOCK MODE

REF_CLK REF_CLK

REFCLK_OUT

XTAL_SEL

PARALLEL DATA

TIMINGAND

CONTROL

SERIAL I/O PORT

AD9910

PROGRAMMING

REGISTERS

OUTPUT

SHIFT

KEYING

DATA

ROUTE

AND

PARTITION

CONTROL

INTERNAL CLOCK TIMING

AND CONTROL

Acos (ωt + θ)

Asin (ωt + θ)

SYNC_SMP_ERR

SYNC_OUT

SYNC_IN

PLL_LOCK

PLL_LOOP_FILTER

MASTER_RESET

DDS

AUX DAC

8-BIT

DAC

14-BIT

RAM_SWP_OVR

DRCTL

DRHOLD DROVER

SYNC_CLK

POWER-

DOWN

CONTROL

DIGITAL RAMP MODULATION MODE

In digital ramp modulation mode (see Figure 24), the modulated DDS signal control parameter is supplied directly from the digital ramp generator (DRG). The ramp generation parameters are controlled through the serial I/O port.

The ramp generation parameters allow the user to control both the rising and falling slopes of the ramp. The upper and lower boundaries of the ramp, the step size and step rate of the rising portion of the ramp, and the step size and step rate of the falling portion of the ramp are all programmable.

The ramp is digitally generated with 32-bit output resolution. The 32-bit output of the DRG can be programmed to represent frequency, phase, or amplitude. When programmed to represent frequency, all 32 bits are used. However, when programmed to represent phase or amplitude, only the 16 MSBs or 14 MSBs, respectively, are used.

The ramp direction (rising or falling) is externally controlled by the DRCTL pin. An additional pin (DRHOLD) allows the user to suspend the ramp generator in its present state.

Figure 24. Digital Ramp Modulation Mode

Rev. D | Page 19 of 64

AD9910 Data Sheet

06479-008

PARALLEL

INPUT

PDCLK

SCLK

SDIO

I/O_RESET

PROFILE[2:0]

I/O_UPDATE

RAM

POWER-

DOWN

CONTROL

EXT_PWR_DWN

DAC_RSET

IOUT IOUT

TxENABLE

DAC FSC

OSK

INVERSE

SINC

FILTER

CLOCK

AMPLIT UDE ( A)

FREQUENCY (ω)

PHASE (θ)

DIGITAL

RAMP

GENERATOR

DAC FSC

MULTICHIP

SYNCHRONIZATION

SYSCLK

PLL

÷2

CLOCK MODE

REF_CLK REF_CLK

REFCLK_OUT

XTAL_SEL

PARALLEL DATA

TIMINGAND

CONTROL

SERIAL I/O PORT

AD9910

PROGRAMMING

REGISTERS

OUTPUT

SHIFT

KEYING

DATA

ROUTE

AND

PARTITION

CONTROL

INTERNAL CLOCK TIMING

AND CONTROL

Acos (ωt + θ)

Asin (ωt + θ)

SYNC_SMP_ERR

SYNC_OUT

SYNC_IN

PLL_LOCK

PLL_LOOP_FILTER

MASTER_RESET

DDS

AUX DAC

8-BIT

DAC

14-BIT

RAM_SWP_OVR

DRCTL

DRHOLD DROVER

SYNC_CLK

PARALLEL DATA PORT MODULATION MODE

In parallel data port modulation mode (see Figure 25), the modulated DDS signal control parameter(s) are supplied directly from the 18-bit parallel data port.

The data port is partitioned into two sections. The 16 MSBs make up a 16-bit data-word (D[15:0] pins) and the two LSBs make up a 2-bit destination word (F[1:0] pins). The destination word defines how the 16-bit data-word is applied to the DDS signal control parameters. Table 4 defines the relationship between the destination bits, the partitioning of the 16-bit data-word, and the destination of the data (in terms of the DDS signal control parameters). Formatting of the 16-bit data-word is unsigned binary, regardless of the destination.

When the destination bits indicate that the data-word is destined as a DDS frequency parameter, the 16-bit data-word serves as an offset to the 32-bit frequency tuning word in the FTW register. This means that the 16-bit data-word must somehow be properly aligned with the 32-bit word in the FTW register. This is accomplished by means of the 4-bit FM gain word in the programming registers. The FM gain word allows the user to

apply a weighting factor to the 16-bit data-word. In the default state (0), the 16-bit data-word and the 32-bit word in the FTW register are LSB aligned. Each increment in the value of the FM gain word shifts the 16-bit data-word to the left relative to the 32-bit word in the FTW register, increasing the influence of the 16-bit data-word on the frequency defined by the FTW register by a factor of two. The FM gain word effectively controls the frequency range spanned by the data-word.

Parallel Data Clock (PDCLK)

The AD9910 generates a clock signal on the PDCLK pin that runs at ¼ of the DAC sample rate (the sample rate of the parallel data port). PDCLK serves as a data clock for the parallel port. By default, each rising edge of PDCLK is used to latch the 18 bits of user-supplied data into the data port. The edge polarity can be changed through the PDCLK invert bit. Furthermore, the PDCLK output signal can be switched off using the PDCLK enable bit. However, even though the output signal is switched off, it continues to operate internally using the internal PDCLK timing to capture the data at the parallel port. Note that PDCLK is Logic 0 when disabled.

Figure 25. Parallel Data Port Modulation Mode

Rev. D | Page 20 of 64

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