Analog Devices AD9898 Datasheet

CCD Signal Processor with

™

Precision Timing

Generator

AD9898

FEATURES Correlated Double Sampler (CDS) 6 dB to 40 dB Variable Gain Amplifier (VGA) Black Level Clamp with Variable Level Control Complete On-Chip Timing Generator Precision Timing Core with 1 ns Resolution On-Chip: 2-Channel Horizontal and

1-Channel RG Drivers 2-Phase H-Clock Modes 4-Phase Vertical Transfer Clocks Electronic and Mechanical Shutter Modes On-Chip Sync Generator with External Sync Option Space Saving 48-Lead LFCSP Package

APPLICATIONS Digital Still Cameras Digital Video Camcorders

FUNCTIONAL BLOCK DIAGRAM

AD9898

CDS

6dB TO 40dB

VGA

GENERAL DESCRIPTION

The AD9898 is a highly integrated CCD signal processor for digital still camera and digital video camera applications. It includes a complete analog front end with A/D conversion combined with a full function programmable timing generator. A Precision Timing core allows adjustment of high speed clocks with 1 ns resolution at 20 MHz operation.

The AD9898 is specified at pixel rates as high as 20 MHz. The analog front end includes black level clamping, CDS, VGA, and a 10-bit A/D converter. The timing generator provides all the necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate pulses, substrate clock, and substrate bias pulse. Operation is programmed using a 3-wire serial interface.

Packaged in a space saving 48-Lead LFCSP, the AD9898 is specified over an operating temperature range of –20°C to +85°C.

REFT REFB

VREF

ADC

DOUT

INTERNAL CLOCKS

H1, H2

V1, V2, V3, V4

VSG1, VSG2

HORIZONTAL

DRIVERS

V- H

CONTROL

VSUB SUBCK HD VD SYNC

REV. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.

CLAMP

DCLK1

PRECISION

TIMING

GENERATOR

SYNC

GENERATOR

CLI

INTERNAL

REGISTERS

SL SCK SDATA

FD/DCLK2

MSHUT

STROBE

AD9898

TABLE OF CONTENTS

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1

FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

DIGITAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 3

ANALOG SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 4

TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 5

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 7

SPECIFICATION DEFINITIONS . . . . . . . . . . . . . . . . . . . 8

Differential Nonlinearity (DNL) . . . . . . . . . . . . . . . . . . . . 8

Peak Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Total Output Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Power Supply Rejection (PSR) . . . . . . . . . . . . . . . . . . . . . . 8

EQUIVALENT INPUT CIRCUITS . . . . . . . . . . . . . . . . . . 8

TYPICAL PERFORMANCE CHARACTERISTICS . . . . . 9

SYSTEM OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

CLI INPUT CLOCK DIVIDER . . . . . . . . . . . . . . . . . . . . . 16

GRAY CODE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . 16

SERIAL INTERFACE TIMING . . . . . . . . . . . . . . . . . . . . 17

Control Register Serial Interface . . . . . . . . . . . . . . . . . . . 17

System Register Serial Interface . . . . . . . . . . . . . . . . . . . . 17

Mode_A and Mode_B Register Serial Interface . . . . . . . . 17

VD SYNCHRONOUS AND ASYNCHRONOUS

Asynchronous Register Operation . . . . . . . . . . . . . . . . . . 18

VD Synchronous Register Operation . . . . . . . . . . . . . . . . 18

ANALOG FRONT END DESCRIPTION AND

OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

DC Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Correlated Double Sampler . . . . . . . . . . . . . . . . . . . . . . . 19

PRECISION TIMING HIGH SPEED TIMING

GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Timing Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

High Speed Clock Programmability . . . . . . . . . . . . . . . . . 19

H-Driver and RG Outputs . . . . . . . . . . . . . . . . . . . . . . . . 20

Digital Data Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

EXTERNAL SYNCHRONIZATION (MASTER MODE) 23 HORIZONTAL AND VERTICAL SYNCHRONOUS

TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Special Note About the HDLEN Register . . . . . . . . . . . . 24

HORIZONTAL CLAMPING AND BLANKING . . . . . . . 25

Controlling CLPOB Clamp Pulse Timing . . . . . . . . . . . . 25

Controlling CLPOB Clamp Pulse Outputs . . . . . . . . . . . 26

H1 AND H2 BLANKING . . . . . . . . . . . . . . . . . . . . . . . . . 27

Normal H-Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Selective Positioning for Two H1 and H2 Outputs . . . . . 27

Extended Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

VGATE MASKING OF V1–V4 AND CLPOB

OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

VERTICAL TIMING GENERATION . . . . . . . . . . . . . . . 30

Creating Vertical Sequences . . . . . . . . . . . . . . . . . . . . . . . 30

Special Vertical Sweep Mode Operation . . . . . . . . . . . . . 34

Special Vertical Timing (SPAT) . . . . . . . . . . . . . . . . . . . 35

ELECTRONIC SHUTTER TIMING CONTROL . . . . . . 37

Normal Shutter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

SUBCK Suppression Mode . . . . . . . . . . . . . . . . . . . . . . . 37

High Precision Shutter Mode . . . . . . . . . . . . . . . . . . . . . . 37

Single Pulse Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Multiple Pulse Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

VSG TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

VSUB CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

VSUB Placement and Polarity . . . . . . . . . . . . . . . . . . . . . 41

MSHUT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

MSHUT Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . 42

MSHUT High Precision Operation . . . . . . . . . . . . . . . . . 43

STROBE Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

SLAVE AND MASTER MODE OPERATION . . . . . . . . . 44

Slave Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Master Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 44

VARIABLE GAIN AMPLIFIER . . . . . . . . . . . . . . . . . . . . . 45

Optical Black Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Digital I/O States for Different Operating Conditions . . . 45

POWER-UP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Recommended Power-Up Sequence for Master Mode . . . 46

STANDBY MODE OPERATION . . . . . . . . . . . . . . . . . . . 47

Recommended Standby Mode Sequence . . . . . . . . . . . . . 47

POWER-DOWN MODE OPERATION . . . . . . . . . . . . . . 48

Recommended Power-Down Sequence . . . . . . . . . . . . . . 48

HORIZONTAL TIMING SEQUENCE EXAMPLE . . . . . 49

CIRCUIT LAYOUT INFORMATION . . . . . . . . . . . . . . . 51

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 52

48-Lead LFCSP Package . . . . . . . . . . . . . . . . . . . . . . . . . 52

TABLES

Table I. Control Register Address Map . . . . . . . . . . . . . . . . 10

Table II. System Register Address Map . . . . . . . . . . . . . . . . 12

Table III. Mode_A Register Map . . . . . . . . . . . . . . . . . . . . . 14

Table IV. Mode_B Register Map . . . . . . . . . . . . . . . . . . . . . 15

Table V. Grade Code Registers . . . . . . . . . . . . . . . . . . . . . . 16

Table VI. Type of Serial Interface Registers . . . . . . . . . . . . 17

Table VII. AFE Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table VIII. RG, H1, SHP, SHD, DCLK, and

DOUTPHASE Timing Parameters . . . . . . . . . . . . . . . . . 21

Table IX. Precision Timing Edge Locations for RG, H1, SHP,

SHD, DCLK, and DOUTPHASE . . . . . . . . . . . . . . . . . . 21

Table X. External Synchronization (Master Mode) . . . . . . . 23

Table XI. HD and VD Registers . . . . . . . . . . . . . . . . . . . . . 24

Table XII. CLPOB Registers . . . . . . . . . . . . . . . . . . . . . . . . 25

Table XIII. SCP and CLPEN . . . . . . . . . . . . . . . . . . . . . . . 26

Table XIV. H1 Blanking Registers . . . . . . . . . . . . . . . . . . . . 27

Table XV. V1–V4 Registers to Configure V1–V4 Pulse

for Each VTP Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table XVI. Mode_A and Mode_B Registers for VTPx

Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table XVII. Mode_A and Mode_B Registers for CCD

Region Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table XVIII. Description of SVREP_MODE Register . . . . 34

Table XIX. HD and VD Registers . . . . . . . . . . . . . . . . . . . . 35

Table XX. SPATLOGIC Register . . . . . . . . . . . . . . . . . . . . 35

Table XXI. SUBCK Registers . . . . . . . . . . . . . . . . . . . . . . . 37

Table XXII. Single and Multiple Pulse Mode . . . . . . . . . . . 37

Table XXIII. VSG Registers . . . . . . . . . . . . . . . . . . . . . . . . 40

Table XXIV. VSUB Registers . . . . . . . . . . . . . . . . . . . . . . . 41

Table XXV. MSHUT and STROBE Registers . . . . . . . . . . 42

Table XXVI. I/O Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

REV. 0–2–

AD9898

SPECIFICATIONS

Parameter Min Typ Max Unit

TEMPERATURE RANGE

Operating –20 +85 °C Storage –65 +150 °C

POWER SUPPLY VOLTAGE

AVDD (AFE Analog Supply) 2.7 3.0 3.6 V TCVDD (Timing Core Analog Supply) 2.7 3.0 3.6 V RGVDD (RG Driver) 2.7 3.0 3.6 V HVDD (H1–H2 Drivers) 2.7 3.0 3.6 V DRVDD (Data Output Drivers) 2.7 3.0 3.6 V DVDD (Digital) 2.7 3.0 3.6 V

POWER DISSIPATION

20 MHz, Typical Supply Levels, 100 pF H1–H2 Loading 150 mW

Power from HVDD Only* 36 mW Power-Down Mode (AFE and Digital in Standby Operation) 3 mW

MAXIMUM CLOCK RATE (CLI)

AD9898 20 MHz

*The total power dissipated by the HVDD supply may be approximated using the equation

Total HVDD Power = (CLOAD × HVDD × Pixel Frequency) × HVDD × Number of H-Outputs Used

Actual HVDD power may be slightly higher than the calculated value because of stray capacitance inherent in the PCB layout/routing.

Specifications subject to change without notice.

DIGITAL SPECIFICATIONS

(RGVDD = HVDD = 2.7 V to 3.6 V, DVDD = DRVDD = 2.7 V to 3.6 V, CL = 20 pF, T otherwise noted.)

MIN

to T

MAX

, unless

Parameter Symbol Min Typ Max Unit

LOGIC INPUTS

High Level Input Voltage V Low Level Input Voltage V High Level Input Current I Low Level Input Current I Input Capacitance C

2.1 V

0.6 V 10 µA 10 µA 10 pF

LOGIC OUTPUTS (Except H and RG)

High Level Output Voltage @ IOH = 2 mA V Low Level Output Voltage @ IOL = 2 mA V

2.2 V

0.5 V

RG and H-DRIVER OUTPUTS (H1–H2)

High Level Output Voltage @ Maximum Current V Low Level Output Voltage @ Maximum Current V

VDD – 0.5 V

0.5 V

RG Maximum Output Current (Programmable) 15 mA H1 and H2 Maximum Output Current (Programmable) 30 mA Maximum Load Capacitance 100 pF

Specifications subject to change without notice.

REV. 0

–3–

AD9898

ANALOG SPECIFICATIONS

(AVDD = 3.0 V, f

= 20 MHz, T

CLI

MIN

to T

, unless otherwise noted.)

MAX

Parameter Min Typ Max Unit Comments

CDS

Allowable CCD Reset Transient 500 mV Input Signal Characteristics Maximum Input Range before Saturation* 1.0 V p-p Maximum CCD Black Pixel Amplitude ± 100 mV

VARIABLE GAIN AMPLIFIER (VGA)

Maximum Output Range 2.0 V p-p Gain Control Resolution 1024 Steps Gain Monotonicity Guaranteed Gain Range

Low Gain 6 dB Maximum Gain 40 dB

BLACK LEVEL CLAMP

Clamp Level Resolution 64 Steps Clamp Level LSB LSB is measured at ADC output.

Minimum Clamp Level 0 LSB Maximum Clamp Level 63 LSB

A/D CONVERTER

Resolution 10 Bits Differential Nonlinearity (DNL) ± 0.5 LSB No Missing Codes Guaranteed Full-Scale Input Voltage 2.0 V

VOLTAGE REFERENCE

Reference Top Voltage (REFT) 2.0 V Reference Bottom Voltage (REFB) 1.0 V

SYSTEM PERFORMANCE Includes entire signal chain

Gain Accuracy

Low Gain (VGA Code = 20) 5 6 7 dB Gain = (0.035 × Code) + 5.3 dB

Maximum Gain (VGA Code = 991) 39 40 41 dB Peak Nonlinearity, 500 mV Input Signal 0.1 % 12 dB gain applied Total Output Noise 0.3 LSB rms AC grounded input, 6 dB gain applied Power Supply Rejection (PSR) 40 dB Measured with step change on supply

*Input signal characteristics defined as follows:

500mV TYP

RESET

TRANSIENT

100mV MAX

OPTICAL

BLACK PIXEL

Specifications subject to change without notice.

1V MAX

INPUT

SIGNAL RANGE

REV. 0–4–

AD9898

TIMING SPECIFICATIONS

(CL = 20 pF, AVDD = DVDD = DRVDD = 3.0 V, f

= 20 MHz, unless otherwise noted.)

CLI

Parameter Symbol Min Typ Max Unit

MASTER CLOCK, CLI

CLI Clock Period t

CONV

50 ns CLI High/Low Pulsewidth 20 25 ns Delay from CLI Rising Edge to Internal Pixel Position 0 t

CLIDLY

6ns

AFE CLAMP PULSES*

CLPOB Pulsewidth 4 10 Pixels

AFE SAMPLE LOCATION* (See Figure 13)

SHP Sample Edge to SHD Sample Edge t

20 25 Pixels

DATA OUTPUTS (See Figure 15)

Output Delay from DCLK Rising Edge t

9ns

Pipeline Delay from SHP/SHD Sampling 9 Cycles

SERIAL INTERFACE (See Figures 7 and 8)

Maximum SCK Frequency f SL to SCK Setup Time t SCK to SL Hold Time t SDATA Valid to SCK Rising Edge Setup t SCK Falling Edge to SDATA Valid Hold t SCK Falling Edge to SDATA Valid Read t

*Parameter is programmable.

Specifications subject to change without notice.

SCLK

10 MHz

10 ns

REV. 0

–5–

AD9898

ABSOLUTE MAXIMUM RATINGS*

Parameter With Respect To Min Max Unit

AVDD AVSS –0.3 +3.9 V TCVDD TCVSS –0.3 +3.9 V HVDD HVSS –0.3 +3.9 V RGVDD RGVSS –0.3 +3.9 V DVDD DVSS –0.3 +3.9 V DRVDD DRVSS –0.3 +3.9 V RG Output RGVSS –0.3 RGVDD + 0.3 V H1–H2 Output HVSS –0.3 HVDD + 0.3 V Digital Outputs DVSS –0.3 DVDD + 0.3 V Digital Inputs DVSS –0.3 DVDD + 0.3 V SCK, SL, SDATA DVSS –0.3 DVDD + 0.3 V REFT, REFB AVSS –0.3 AVDD + 0.3 V CCDIN AVSS –0.3 AVDD + 0.3 V Junction Temperature 150 °C Lead Temperature, 10 sec 300 °C

*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;

functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

PACKAGE THERMAL CHARACTERISTICS Thermal Resistance

␪JA = 92°C/W

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9898KCP-20 –20ºC to +85ºC Lead Frame Chip Scale Package (LFCSP) CP-48 AD9898KCPRL-20 –20ºC to +85ºC Lead Frame Chip Scale Package (LFCSP) CP-48

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9898 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

REV. 0–6–

PIN CONFIGURATION

SUBCK

DVSS

DVD D

SYNC/VGATE

VSUB

OUTCONT

VSG2

VSG1V4V3V2V1

HVSS

HVDD

DRVSS

DRVDD

48 47 46 4 5 44 39 38 3743 4 2 41 40

PIN 1

IDENTIFIER

13 14 15 16 17 18 19 20 21 22 23 24

DCLK1

(Not to Scale)

MSHUT

STROBE

FD/DCLK2

AD9898

TOP VIEW

PIN FUNCTION DESCRIPTION

AD9898

SCK

SDATA

REFB

REFT

AVSS

CCDIN

AV DD

CLI

TCVDD

TCVSS

RGVDD

RGVSS

Pin No. Mnemonic Type* Description

1D0DOData Output

2D1DOData Output

3D2DOData Output

4D3DOData Output

5D4DOData Clock Output

6 DRVSS P Data Output Driver Ground

7 DRVDD P Data Output Driver Supply

8D5DOData Output

9D6DOData Output

10 D7 DO Data Output

11 D8 DO Data Output

12 D9 DO Data Output

13 DCLK1 DO Data Clock Output

14 MSHUT DO Mechanical Shutter Pulse

15 STROBE DO Strobe Pulse

16 FD/ DO Field Designator Output

DCLK2 DO DCLK2 Output

17 HD DI Horizontal Sync Pulse

18 VD DI Vertical Sync Pulse

19 HVDD P H1–H2 Driver Supply

20 HVSS P H1–H2 Driver Ground

21 H2 DO CCD Horizontal Clock 2

22 H1 DO CCD Horizontal Clock 1

23 RGVSS P RG Driver Ground

24 RG DO CCD Reset Gate Clock

25 RGVDD P RG Driver Supply

26 TCVSS P Analog Ground for Timing

Core

27 TCVDD P Analog Supply for Timing Core

Pin No. Mnemonic Type* Description

28 CLI DI Reference Clock Input

29 AVDD P Analog Supply for AFE

30 CCDIN AI CCD Input Signal

31 AVSS P Analog Ground for AFE

32 REFT AO Voltage Reference Top Bypass

33 REFB AO Voltage Reference Bottom

Bypass

34 SDATA DI 3-Wire Serial Data Input

35 SL DI 3-Wire Serial Load Pulse

36 SCK DI 3-Wire Serial Clock

37 V1 DO CCD Vertical Transfer Clock 1

38 V2 DO CCD Vertical Transfer Clock 2

39 V3 DO CCD Vertical Transfer Clock 3

40 V4 DO CCD Vertical Transfer Clock 4

41 VSG1 DO CCD Sensor Gate Pulse 1

42 VSG2 DO CCD Sensor Gate Pulse 2

43 OUTCONT DI Output Control

44 VSUB DO CCD Substrate Bias

45 SYNC/ DI External System Sync Input

VGATE DI VGATE Input

46 DVDD P Digital Supply for VSG,

V1–V4, HD, VD, MSHUT, STROBE, and Serial Interface

47 DVSS P Digital Ground

48 SUBCK DO CCD Substrate Clock

(E-Shutter)

*AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital

Output, P = Power.

REV. 0

–7–

AD9898

SPECIFICATION DEFINITIONS Differential Nonlinearity (DNL)

An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus every code must have a finite width. No missing codes guaranteed to 10-bit resolution indicates that all 1024 codes, respectively, must be present over all operating conditions.

Peak Nonlinearity

Peak nonlinearity, a full signal chain specification, refers to the peak deviation of the output of the AD9898 from a true straight line. The point used as zero scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular output code to the true straight line. The error is then expressed as a percentage of the 2 V ADC full-scale signal. The input signal is always appropriately gained up to fill the ADC’s full-scale range.

EQUIVALENT INPUT CIRCUITS

AVDD

Total Output Noise

The rms output noise is measured using histogram techniques. The standard deviation of the ADC output codes is calculated in LSB and represents the rms noise level of the total signal chain at the specified gain setting. The output noise can be converted to an equivalent voltage, using the relationship 1 LSB = (ADC Full Scale/2

codes) where N is the bit resolution of the

ADC. For the AD9898, 1 LSB is 2 mV.

Power Supply Rejection (PSR)

The PSR is measured with a step change applied to the supply pins. The PSR specification is calculated from the change in the data outputs for a given step change in the supply voltage.

DVDD

330



AVSS

Figure 1. CCDIN

DVDD

DATA

THREESTATE

DVSS

Figure 2. Digital Data Outputs

AVSS

DVSS

Figure 3. Digital Inputs

HVDD OR

DRVDD

DRVSS

DOUT

RG,

H1–H2

ENABLE

RGVDD

OUTPUT

HVSS OR RGVSS

Figure 4. H1–H2, RG Drivers

REV. 0–8–

Typical Performance Characteristics–AD9898

180

160

140

120

100

POWER DISSIPATION (mW)

TPC 1. Power vs. Sample Rate

VDD = 3.3V

VDD = 3.0V

VDD = 2.7V

SAMPLE RATE – MHz

0.3

0.15

DNL (LSB)

–0.15

–0.3

2015

200 600 800

400

1000

CODE

TPC 2. Typical DNL Performance

REV. 0

–9–

AD9898

Table I. Control Register Address Map (Register Names Are Subject to Change)

Bit Default Register

Address Content Width Value Name Register Description

00 (23:0) 23 000000 SW_RESET Software Reset = 000000. (Reset all registers to default.)

01 (23:21) 3 0 Unused

20 1 0 Unused. Test Mode. Should be set = 0. (19:18) 2 1 Unused 17 1 1 HBLKMASK Masking Polarity for H1 during blanking period (0 = Low, 1 = High) 16 1 0 SYNCPOL External SYNC Active Polarity (0 = Active Low) (15:14) 2 0 Unused 13 1 0 SUBCKMODE_HP High Precision Shutter Mode Operation (0 = Single Pulse, 1 = Multiple

Pulse)

12 1 0 SUBCKSUPPRESS Suppress First SUBCK after Last VSG Line Pulse (0 = No Suppression,

1 = Suppression of 1 SUBCK) (11:10) 2 0 Unused (9:8) 2 0 MSHUTPAT Selects MSHUT Pattern (See Figure 44) (0 = MSHUTPAT0,

1 = MSHUTPAT1, 2 = MSHUTPAT2, 3 = MSHUTPAT3) 710MSHUT/VGATE_EN MSHUT Masking of VGATE Input (0 = MSHUT does not mask

VGATE, 1 = MSHUT does mask VGATE) 610MSHUT/SUBCK_EN MSHUT Masking of SUBCK (0 = MSHUT does not mask SUBCK,

1 = MSHUT does mask SUBCK) 511CLP_CONT CLPOB Control (0 = CLPOB OFF, 1 = CLPOB ON) 411CLP_MODE CLPOB CCD Region Control (See Table XII) (3:1) 3 0 Unused 010VDMODE VD Synchronous/Asynchronous Mode Setting (0 = VD Synchronous,

1 = VD Asynchronous)

02 (23:22) 2 0 Unused

(21:16) 6 0x34 SHDLOC SHD Sample Location (15:14) 2 0 Unused (13:8) 6 0x18 SHPLOC SHP Sample Location (7:6) 2 0 DCLKPHASE DCLK Pulse Adjustment (5:0) 6 0x0B DOUTPHASE Data Output [9:0] Phase Adjustment

03 (23:17) 7 0x00 Unused

16 1 0 H1BLKRETIME Retimes the H1 HBLK to Internal Clock (15:14) 2 0 Unused (13:8) 6 0x00 H1POSLOC H1 Positive Edge Location (7:6) 2 0 Unused (5:0) 6 0x10 RGNEGLOC RG Negative Edge Location

04 (23:22) 2 0 Unused

(21:16) 6 0x20 REFBLACK Black Clamp Level (14:12) 3 5 H2DRV H2 Drive Strength (0 = Off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA,

4 = 17.2 mA, 5 = 21.5 mA, 6 = 25.8 mA, 7 = 30.1 mA) 11 1 0 Unused (10:8) 3 5 H1DRV H1 Drive Strength (0 = Off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA,

4 = 17.2 mA, 5 = 21.5 mA, 6 = 25.8 mA, 7 = 30.1 mA) (7:3) 5 0x00 Unused (2:0) 3 2 RGDRV RG Drive Strength (0 = Off, 1 = 2.15 mA, 2 = 4.2 mA, 3 = 6.45 mA,

4 = 8.6 mA, 5 = 10.75 mA, 6 = 12.9 mA, 7 = 15.05 mA)

05 (23:10) 14 0x0000 Unused

910AFESTBY AFE Standby (0 = Standby , 1 = Normal Operation) 810DIGSTBY Digital Standby (0 = Standby , 1 = Normal Operation) (7:2) 6 00 Unused 110OUTCONT_REG Internal OUTCONT Signal Control (0 = Digital Outputs held at fixed

dc level, 1 = Normal Operation) 011OUTCONT_ENB External OUTCONT Signal Input Pin 43 Control (0 = Pin Enabled,

1 = Pin Disabled)

REV. 0–10–

AD9898

Table I. Control Register Address Map (Register Names Are Subject to Change)

Bit Default Register

Address Content Width Value Name Register Description

0A 23 1 0 Unused

22 1 0 FDPOL FD Polarity Control (0 = Low, 1 = High) (21:16) 6 0x00 VSGMASK VSG Masking (See Table XXIII) (15:12) 4 0 SYNCCNT External SYNC Setting

(VD (11:10) 2 0 SVREP_MODE Super Vertical Repetition Mode SyncReg)* 910HBLKEXT H Pulse Blanking Extend Control

810HPULSECNT H Pulse Control during Blanking (7:4) 4 C SPATLOGIC SPAT Logic Setting (See Table XX) (3:2) 2 3 SVOS Second V Output Setting (10 = Output Repetition 1) 110SPAT_EN SPAT Control (0 = SPAT Disable, 1 = SPAT Enable) 010MODE Mode Control Bit (0 = Mode_A, 1 = Mode_B)

0B (23:22) 2 0 Unused

21 1 1 SUBCK_EN SUBCK Output Enable Control (0 = Disable, 1 = Enable) 20 1 1 VSG_EN VSG Output Enable Control (0 = Disable, 1 = Enable)

(VD (19:17) 3 0 Unused SyncReg)* 16 1 0 STROBE_EN STROBE Output Control (0 = STROBE Output Held Low,

1 = STROBE Output Enabled) 15 1 0 Unused (14:12) 3 0 SUBCKNUM_HP High Precision Shutter SUBCLK Pulse Position/Number 11 1 0 Unused (10:0) 11 0x7FF SUBCKNUM Total Number of SUBCKs per Field

0C (23:21) 3 0 Unused

20 1 0 MSHUTINIT MSHUT Initialize (1 = Forces MSHUT Low) (19:18) 2 0 Unused

(VD 17 1 0 Unused SyncReg)* 16 1 0 MSHUTEN MSHUT Control ( 0 = MSHUT Held at Last State, 1 = MSHUT Output)

15 1 0 Unused (14:12) 3 0 MSHUTPOS_HP MSHUT Position during High Precision Operation 11 1 0 Unused (10:0) 11 0x000 MSHUTPOS MSHUT Position during Normal Operation

0D (23:17) 7 Unused

16 1 0 VSUBPOL VSUB Active Polarity (0 = Low, 1 = High)

(VD (15:11) 5 Unused SyncReg)* (10:0) 11 0x000 VSUBTOG VSUB Toggle Position. Active starting line in any field.

0E (23:21) 3 0 Unused

20 1 0 Unused. Test Mode. Should be set = 0. (19:18) 2 0 Unused

(VD 17 1 0 Unused. Test Mode. Should be set = 0. SyncReg)* 16 1 0 Unused. Test Mode. Should be set = 0.

(15:10) 6 0x00 Unused (9:0) 10 0x000 VGAGAIN VGA Gain

D5 (23:4) 20 0x00000 Unused

311DCLK2SEL DCLK2 Selector (0 = Select Internal FD Signal to be Output on FD/

DCLK2 Pin 16, 1 = Select CLI to be Output on FD/DCLK2 Pin 16) 210DCLK1SEL DCLK1 Selector (0 = Select DLL Version for DCLK1 Output,

1 = Select CLI for DCLK1 Output) (1:0) 2 0 CLKDIV Input Clock Divider (0 = No Division, 1 = 1/2, 2 = 1/3, 3 = 1/4)

D6 (23:1) 23 0x000000 Unused

011SLAVE_MODE Operating Mode ( 0 = Master Mode, 1 = Slave Mode)

*This register defaults to VD synchronous mode type at power up. VD sync type registers do not get updated until the first falling edge of VD is asserted after the

register has been programmed. VD sync type registers can be programmed to be asynchronous registers by setting VDMODE = 1 (Addr 0x01).

REV. 0

–11–

AD9898

Table II. System Register Address Map (Addr 0x14)

Bit Default

Sys_Reg(0) (31:24) 8 NA System_Reg_Addr System Register Address Is (Addr 0x14)

(23:0) 24 NA System_Number_N Number N Register Writes (0x000000 = Write All Registers)

Sys_Reg(1) (31:23) 9 37 VTPLEN0 Vertical Sequence No. 0: Length between Repetitions

22 1 0 V1STARTPOL0 Vertical Sequence No. 0: V1 Start Polarity 21 1 0 V2STARTPOL0 Vertical Sequence No. 0: V2 Start Polarity 20 1 1 V3STARTPOL0 Vertical Sequence No. 0: V3 Start Polarity 19 1 1 V4STARTPOL0 Vertical Sequence No. 0: V4 Start Polarity (18:10) 9 0 V1TOG1POS0 Vertical Sequence No. 0: V1 Toggle Position 1 (9:1) 9 19 V1TOG2POS0 Vertical Sequence No. 0: V1 Toggle Position 2 010 V2TOG1POS0 [8]

Sys_Reg(2) (31:24) 8 12 V2TOG1POS0 [7:0] Vertical Sequence No. 0: V2 Toggle Position 1

(23:15) 9 31 V2TOG2POS0 Vertical Sequence No. 0: V2 Toggle Position 2 (14:6) 9 0 V3TOG1POS0 Vertical Sequence No. 0: V3 Toggle Position 1 (5:0) 6 V3TOG2POS0 [8:3]

Sys_Reg(3) (31:29) 3 19 V3TOG2POS0 [2:0] Vertical Sequence No. 0: V3 Toggle Position 2

(28:20) 9 12 V4TOG1POS0 Vertical Sequence No. 0: V4 Toggle Position 1 (19:11) 9 31 V4TOG2POS0 Vertical Sequence No. 0: V4 Toggle Position 2 (10:2) 9 104 VTPLEN1 Vertical Sequence No. 1: Length between Repetitions 110 V1STARTPOL1 Vertical Sequence No. 1: V1 Start Polarity 010 V2STARTPOL1 Vertical Sequence No. 1: V2 Start Polarity

Sys_Reg(4) 31 1 1 V3STARTPOL1 Vertical Sequence No. 1: V3 Start Polarity

30 1 1 V4STARTPOL1 Vertical Sequence No. 1: V4 Start Polarity (29:21) 9 18 V1TOG1POS1 Vertical Sequence No. 1: V1 Toggle Position 1 (20:12) 9 58 V1TOG2POS1 Vertical Sequence No. 1: V1 Toggle Position 2 (11:3) 9 47 V2TOG1POS1 Vertical Sequence No. 1: V2 Toggle Position 1 (2:0) 3 V2TOG2POS1 [8:6]

Sys_Reg(5) (31:26) 6 96 V2TOG2POS1 [5:0] Vertical Sequence No. 1: V2 Toggle Position 2

(25:17) 9 0 V3TOG1POS1 Vertical Sequence No. 1: V3 Toggle Position 1 (16:8) 9 76 V3TOG2POS1 Vertical Sequence No. 1: V3 Toggle Position 2 (7:0) 8 V4TOG1POS1 [8:1]

Sys_Reg(6) 31 1 38 V4TOG1POS1 [0] Vertical Sequence No. 1: V4 Toggle Position 1

(30:22) 9 105 V4TOG2POS1 Vertical Sequence No. 1: V4 Toggle Position 2 (21:13) 9 57 VTPLEN2 Vertical Sequence No. 2: Length between Repetitions 12 1 0 V1STARTPOL2 Vertical Sequence No. 2: V1 Start Polarity 11 1 0 V2STARTPOL2 Vertical Sequence No. 2: V2 Start Polarity 10 1 1 V3STARTPOL2 Vertical Sequence No. 2: V3 Start Polarity 911 V4STARTPOL2 Vertical Sequence No. 2: V4 Start Polarity (8:0) 9 0 V1TOG1POS2 Vertical Sequence No. 2: V1 Toggle Position 1

Sys_Reg(7) (31:23) 9 29 V1TOG2POS2 Vertical Sequence No. 2: V1 Toggle Position 2

(22:14) 9 19 V2TOG1POS2 Vertical Sequence No. 2: V2 Toggle Position 1 (13:5) 9 48 V2TOG2POS2 Vertical Sequence No. 2: V2 Toggle Position 2 (4:0) 5 V3TOG1POS2 [8:4]

Sys_Reg(8) (31:28) 4 0 V3TOG1POS2 [3:0] Vertical Sequence No. 2: V3 Toggle Position 1

(27:19) 9 29 V3TOG2POS2 Vertical Sequence No. 2: V3 Toggle Position 2 (18:10) 9 19 V4TOG1POS2 Vertical Sequence No. 2: V4 Toggle Position 1 (9:1) 9 48 V4TOG2POS2 Vertical Sequence No. 2: V4 Toggle Position 2 01 Unused

REV. 0–12–

AD9898

Table II. System Register Address Map (Addr 0x14) (continued)

Bit Default

Sys_Reg(9) (31:23) 9 89 VTPLEN3 Vertical Sequence No. 3: Length between Repetitions

22 1 0 V1STARTPOL3 Vertical Sequence No. 3: V1 Start Polarity 21 1 0 V2STARTPOL3 Vertical Sequence No. 3: V2 Start Polarity 20 1 1 V3STARTPOL3 Vertical Sequence No. 3: V3 Start Polarity 19 1 1 V4STARTPOL3 Vertical Sequence No. 3: V4 Start Polarity (18:10) 9 0 V1TOG1POS3 Vertical Sequence No. 3: V1 Toggle Position 1 (9:1) 9 60 V1TOG2POS3 Vertical Sequence No. 3: V1 Toggle Position 2 01 V2TOG1POS3 [8]

Sys_Reg(10) (31:24) 8 30 V2TOG1POS3 [7:0] Vertical Sequence No. 3: V2 Toggle Position 1

(23:15) 9 90 V2TOG2POS3 Vertical Sequence No. 3: V2 Toggle Position 2 (14:6) 9 0 V3TOG1POS3 Vertical Sequence No. 3: V3 Toggle Position 1 (5:0) 6 V3TOG2POS3 [8:3]

Sys_Reg(11) (31:29) 3 60 V3TOG2POS3 [2:0] Vertical Sequence No. 3: V3 Toggle Position 2

(28:20) 9 30 V4TOG1POS3 Vertical Sequence No. 3: V4 Toggle Position 1 (19:11) 9 90 V4TOG2POS3 Vertical Sequence No. 3: V4 Toggle Position 2 (10:1) 10 0 HBLKHPOS H1 Pulse ON Position during Blanking Period 01 Unused

Sys_Reg(12) (31:20) 12 2283 HDLEN* 12-Bit Gray Code HD Counter Value (Gray Code Number)

(19:10) 10 130 HLEN 10-Bit HL Counter Value (9:1) 9 100 OLEN 9-Bit OL Counter Value 01 BLLEN [8]

Sys_Reg(13) (31:24) 8 0 BLLEN[7:0] 9-Bit BL Counter Value

(23:16) 8 118 MSHUTLEN MSHUT Sequence Length (15:5) 11 1048 VSGTOG1_0 VSG Sequence No. 1 Toggle Position 1 (4:0) 5 VSGTOG1_1 [10:6]

Sys_Reg(14) (31:26) 6 1198 VSGTOG1_1 [5:0] VSG Sequence No. 2 Toggle Position 1

(25:18) 8 60 VSGLEN VSG Pulsewidth (17:9) 9 19 SUBCK1TOG1 SUBCK1 First Toggle Position (8:0) 9 88 SUBCK1TOG2 SUBCK1 Second Toggle Position

Sys_Reg(15) (31:23) 9 19 SUBCK2TOG1 SUBCK2 First Toggle Position

(22:14:) 9 88 SUBCK2TOG2 SUBCK2 Second Toggle Position (13:2) 12 2243 CLPTOG1* CLPOB Toggle Position No. 1 (1:0) 2 CLPTOG2 [11]*

Sys_Reg(16) (31:22) 10 2278 CLPTOG2 [10:0]* CLPOB Toggle Position No. 2

(21:18) 4 9 VDRISE VD Toggle Position No. 1 (17:8) 10 120 HDRISE HD Toggle Position No. 2 (7:0) 8 Unused

*Register value must be a gray code number. (See Gray Code Registers section.)

REV. 0

–13–

AD9898

Table III. Mode_A Register Map (Addr 0x15)

Bit Default

Mode_Reg(0) (31:24) 8 NA Mode_A_Addr Mode_A Address Is (Addr 0x15)

(23:0) 24 NA Mode_A_Number_N Number N Register Writes (0x000000 = Write All Registers)

Mode_Reg(1) (31:21) 11 262 VDLEN VD Counter Value

(20:9) 12 1139 HDLASTLEN Number of Pixels in Last Line (Gray Code Number) 811 VSGSEL0 VSG1 Sequence Selector (See Table XXIII) 710 VSGSEL1 VSG2 Sequence Selector (See Table XXIII) (6:0) 7 0 VSGACTLINE VSG Active Line

Mode_Reg(2) 31 1 0 SUBCKSEL Select one of two SUBCK Patterns

(30:28) 3 0 VTPSEQPTR0 Vertical Transfer Sequence Region No. 0 (27:25) 3 0 VTPSEQPTR1 Vertical Transfer Sequence Region No. 1 (24:22) 3 0 VTPSEQPTR2 Vertical Transfer Sequence Region No. 2 (21:19) 3 0 VTPSEQPTR3 Vertical Transfer Sequence Region No. 3 (18:16) 3 0 VTPSEQPTR4 Vertical Transfer Sequence Region No. 4 15 1 1 CLPEN0 CLPOB Output Control No. 1 14 1 0 CLPEN1 CLPOB Output Control No. 2 13 1 0 CLPEN2 CLPOB Output Control No. 3 12 1 0 CLPEN3 CLPOB Output Control No. 4 11 1 0 CLPEN4 CLPOB Output Control No. 5 (10:3) 8 0 SCP1 Sequence Change Position No. 1 (2:0) 3 SCP2

Mode_Reg(3) (31:27) 5 0 SCP2 Sequence Change Position No. 2

(26:19) 8 0 SCP3 Sequence Change Position No. 3 (18:11) 8 0 SCP4 Sequence Change Position No. 4 (10:9) 2 0 VTPSEL0 Vertical Pattern Selection 0 (8:7) 2 0 VTPSEL1 Vertical Pattern Selection 1 (6:5) 2 0 VTPSEL2 Vertical Pattern Selection 2 (4:3) 2 0 VTPSEL3 Vertical Pattern Selection 3 (2:0) 3 3 VTPREP0 Number of Vertical Pulse Repetitions for Pattern0

Mode_Reg(4) (31:29) 3 0 VTPREP1 Number of Vertical Pulse Repetitions for Pattern1

(28:26) 3 0 VTPREP2 Number of Vertical Pulse Repetitions for Pattern2 (25:23) 3 0 VTPREP3 Number of Vertical Pulse Repetitions for Pattern3 (22:12) 11 0 SVREP0 Vertical Sweep Repetition Number for CCD Region0 (11:1) 11 0 SVREP3 Vertical Sweep Repitition Number for CCD Region3 01 Unused

Mode_Reg(5) (31:19) 13 988 V1SPAT_TOG1 Polarity Change Position Start for V1 SPAT

(18:6) 13 1138 V1SPAT_TOG2 Polarity Change Position End for V1 SPAT (5:0) 6 V2SPAT_TOG1

Mode_Reg(6) (31:25) 7 1078 V2SPAT_TOG1 Polarity Change Position Start for V2 SPAT

(24:12) 13 1168 V2SPAT_TOG2 Polarity Change Position End for V2 SPAT (11:0) 12 V3SPAT_TOG1

Mode_Reg(7) 31 1 958 V3SPAT_TOG1 Polarity Change Position Start for V3 SPAT

(30:18) 13 1138 V3SPAT_TOG2 Polarity Change Position End for V3 SPAT (17:5) 13 988 V4SPAT_TOG1 Polarity Change Position Start for V4 SPAT (4:0) 5 V4SPAT_TOG2

Mode_Reg(8) (31:24) 8 1228 V4SPAT_TOG2 Polarity Change Position End for V4 SPAT

(23:11) 13 1392 SECONDVPOS Second V Pattern Output Position (10:9) 2 3 VPATSECOND Selected Second V Pattern Group for VSG Active Line (8:0) 9 Unused

REV. 0–14–

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Table IV. Mode_B Register Map (Addr 0x16)

Bit Default

Mode_Reg(0) (31:24) 8 NA Mode_B_Addr Mode_B Address Is (Addr 0x16)

(23:0) 24 NA Mode_B_Number_N Number N Register Writes (0x000000 = Write All Registers)

Mode_Reg(1) (31:21) 11 262 VDLEN VD Counter Value

(20:9) 12 1139 HDLASTLEN* Number of Pixels in Last Line (Gray Code Number) 811 VSGSEL0 VSG1 Sequence Selector (See Table XXIII) 710 VSGSEL1 VSG2 Sequence Selector (See Table XXIII) (6:0) 7 0 VSGACTLINE VSG Active Line

Mode_Reg(2) 31 1 0 SUBCKSEL Select One of Two SUBCK Patterns

Mode_Reg(3) (31:27) 5 0 SCP2 Sequence Change Position No. 2

Mode_Reg(4) (31:29) 3 0 VTPREP1 Number of VTP1 Pulse Repetitions for Pattern1

(28:26) 3 0 VTPREP2 Number of VTP2 Pulse Repetitions for Pattern2 (25:23) 3 0 VTPREP3 Number of VTP0 Pulse Repetitions for Pattern3 (22:12) 11 0 SVREP0 Vertical Sweep Repetition Number for CCD Region0 (11:1) 11 0 SVREP3 Vertical Sweep Repetition Number for CCD Region3 01 Unused