ANALOG DEVICES AD9891, AD9895 Service Manual

CCD Signal Processors with

FEATURES AD9891: 10-Bit 20 MHz Version AD9895: 12-Bit 30 MHz Version Correlated Double Sampler (CDS) 4 6 dB Pixel Gain Amplifier ( 2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA) 10-Bit 20 MHz A/D Converter (AD9891) 12-Bit 30 MHz A/D Converter (AD9895) Black Level Clamp with Variable Level Control Complete On-Chip Timing Generator

Precision Timing

Core with 1 ns Resolution On-Chip 5 V Horizontal and RG Drivers 2-Phase and 4-Phase H-Clock Modes 4-Phase Vertical Transfer Clocks Electronic and Mechanical Shutter Modes On-Chip Driver for External Crystal On-Chip Sync Generator with External Sync Option 64-Lead CSPBGA Package

APPLICATIONS Digital Still Cameras Digital Video Camcorders Industrial Imaging

PxGA

)

Precision Timing

™

Generator

AD9891/AD9895

PRODUCT DESCRIPTION

The AD9891 and AD9895 are highly integrated CCD signal processors for digital still camera applications. Both include a complete analog front end with A/D conversion combined with a full-function programmable timing generator. A Precision Timing core allows adjustment of high speed clocks with 1 ns resolution at 20 MHz operation and 700 ps resolution at 30 MHz operation.

The AD9891 is specified at pixel rates of up to 20 MHz, and the AD9895 is specified at 30 MHz. The analog front end includes black level clamping, CDS, PxGA, VGA, and a 10-Bit or 12-Bit A/D converter. The timing generator provides all the necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate pulses, substrate clock, and substrate bias control. Operation is programmed using a 3-wire serial interface.

Packaged in a space-saving 64-lead CSPBGA, the AD9891 and AD9895 are –20°C to +85°C.

specified over an operating temperature range of

FUNCTIONAL BLOCK DIAGRAM

VRT VRB

4dB  6dB

CCDIN

H1–H4

V1–V4

VSG1–VSG8

PxGA is a registered trademark and Precision Timing is a trademark of Analog Devices, Inc.

PxGACDS

CLAMP

HORIZONTAL

DRIVERS

V- H

CONTROL

VSUB SUBCK HD VD SYNC

2dB TO 36dB

VGA

INTERNAL CLOCKS

PRECISION

TIMING

GENERATOR

SYNC

GENERATOR

VREF

AD9891/AD9895

ADC

CLAMP

REGISTERS

CLI

SL SCK DATA

10 OR 12

DOUT

DCLK

CLPOB/PBLK

FD/LD

MSHUT

STROBE

CLO

INTERNAL

REV. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002

AD9891/AD9895

TABLE OF CONTENTS

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

DIGITAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . 3

AD9891 ANALOG SPECIFICATIONS . . . . . . . . . . . . . . 4

AD9895 ANALOG SPECIFICATIONS . . . . . . . . . . . . . . 5

TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . 6

PACKAGE THERMAL CHARACTERISTICS . . . . . . . . 6

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PIN CONFIGURATION-AD9891 . . . . . . . . . . . . . . . . . . . 7

PIN FUNCTION DESCRIPTIONS-AD9891 . . . . . . . . . . . 7

PIN CONFIGURATION-AD9895 . . . . . . . . . . . . . . . . . . . 8

PIN FUNCTION DESCRIPTIONS-AD9895 . . . . . . . . . . . 8

SPECIFICATION DEFINITIONS . . . . . . . . . . . . . . . . . . . 9

EQUIVALENT CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . 9

TYPICAL PERFORMANCE CHARACTERISTICS . . . . 10

SYSTEM OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Typical System Block Diagram . . . . . . . . . . . . . . . . . . . . 11

PRECISION TIMING HIGH SPEED TIMING

GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Timing Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

High Speed Clock Programmability . . . . . . . . . . . . . . . . . .12

H-Driver and RG Outputs . . . . . . . . . . . . . . . . . . . . . . . . .13

Digital Data Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

HORIZONTAL CLAMPING AND BLANKING . . . . . . . . 15

Individual CLPOB, CLPDM, and PBLK Sequences . . . . .15

Individual HBLK Sequences . . . . . . . . . . . . . . . . . . . . . . .15

Horizontal Sequence Control . . . . . . . . . . . . . . . . . . . . . . .15

VERTICAL TIMING GENERATION . . . . . . . . . . . . . . . .17

Individual Vertical Sequences . . . . . . . . . . . . . . . . . . . . . .18

Individual Vertical Regions . . . . . . . . . . . . . . . . . . . . . . . .19

Complete Field: Combining the Regions . . . . . . . . . . . . . .20

Vertical Sequence Alteration . . . . . . . . . . . . . . . . . . . . . . .21

Second Vertical Sequence During VSG Lines . . . . . . . . . .22

Vertical Sweep Mode Operation . . . . . . . . . . . . . . . . . . . .22

Vertical Multiplier Mode . . . . . . . . . . . . . . . . . . . . . . . . . .24

Frame Transfer CCD Mode . . . . . . . . . . . . . . . . . . . . . . 24

Vertical Sensor Gate (Shift Gate) Timing . . . . . . . . . . . . .25

SHUTTER TIMING CONTROL . . . . . . . . . . . . . . . . . . . .26

Normal Shutter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

High Precision Shutter Mode . . . . . . . . . . . . . . . . . . . . . . .26

Low Speed Shutter Mode . . . . . . . . . . . . . . . . . . . . . . . . .26

SUBCK Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Readout After Exposure . . . . . . . . . . . . . . . . . . . . . . . . . . .27

VSUB Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

MSHUT and STROBE Control . . . . . . . . . . . . . . . . . . . .27

Example of Exposure and Readout of Interlaced Frame . . .29 ANALOG FRONT END DESCRIPTION AND

OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

DC Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Correlated Double Sampler . . . . . . . . . . . . . . . . . . . . . . . 30

Input Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

PxGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

PxGA Color Steering Mode Timing . . . . . . . . . . . . . . . . 31

Variable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . 33

PxGA and VGA Gain Curves . . . . . . . . . . . . . . . . . . . . . 33

Optical Black Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

POWER-UP AND SYNCHRONIZATION . . . . . . . . . . . . 34

Recommended Power-Up Sequence for Master Mode . . . .34

SYNC During Master Mode Operation . . . . . . . . . . . . . . .35

Synchronization in Slave Mode . . . . . . . . . . . . . . . . . . . . .35

POWER-DOWN MODE OPERATION . . . . . . . . . . . . . . 35

HORIZONTAL TIMING SEQUENCE EXAMPLE . . . . . 37

VERTICAL TIMING EXAMPLE . . . . . . . . . . . . . . . . . . . 39

CIRCUIT LAYOUT INFORMATION . . . . . . . . . . . . . . . .40

SERIAL INTERFACE TIMING . . . . . . . . . . . . . . . . . . . . .41

Notes About Accessing a Double-Wide Register . . . . . . . 41

NOTES ON REGISTER LISTING . . . . . . . . . . . . . . . . . . 42

COMPLETE REGISTER LISTING . . . . . . . . . . . . . . . . . 43

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 57

REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

REV. A–2–

AD9891/AD9895–SPECIFICATIONS

Parameter Min Typ Max Unit

TEMPERATURE RANGE

Operating –20 +85 °C Storage –65 +150 °C

POWER SUPPLY VOLTAGE

AVDD1, AVDD2 (AFE Analog Supply) 2.7 3.0 3.6 V TCVDD (Timing Core Analog Supply) 2.7 3.0 3.6 V RGVDD (RG Driver) 3.0 5.0 5.25 V HVDD (H1–H4 Drivers) 3.0 5.0 5.25 V DRVDD (Data Output Drivers) 2.7 3.0 3.6 V DVDD (Digital) 2.7 3.0 3.6 V

POWER DISSIPATION–AD9891 (See TPC 1 for Power Curves)

20 MHz, Typ Supply Levels, 100 pF H1–H4 Loading 380 mW Power from HVDD Only Power-Down 1 Mode 42 mW Power-Down 2 Mode 8 mW Power-Down 3 Mode 2.5 mW

POWER DISSIPATION–AD9895 (See TPC 4 for Power Curves)

30 MHz, Typ Supply Levels, 100 pF H1–H4 Loading 600 mW Power from HVDD Only Power-Down 1 Mode 138 mW Power-Down 2 Mode 22 mW Power-Down 3 Mode 2.5 mW

MAXIMUM CLOCK RATE (CLI)

AD9891 20 MHz AD9895 30 MHz

The total power dissipated by the HVDD supply may be approximated using the equation:

Total HVDD Power = [C

Reducing the H-loading, using only two of the outputs, and/or using a lower HVDD supply will reduce the power dissipation. Actual HVDD power may be slightly higher than the calculated value because of stray capacitance inherent in the PCB layout/routing. Specifications subject to change without notice.

 HVDD  Pixel Frequency]

LOAD



HVDD



Number of H-Outputs Used

220 mW

320 mW

DIGITAL SPECIFICATIONS

(RGVDD = HVDD = 4.75 V to 5.25 V, DVDD = DRVDD = 2.7 V to 3.5 V, CL = 20 pF, T unless otherwise noted.)

MIN

to T

MAX

Parameter Symbol Min Typ Max Unit

LOGIC INPUTS

High Level Input Voltage V Low Level Input Voltage V High Level Input Current I Low Level Input Current I Input Capacitance C

2.1 V

0.6 V 10 µA 10 µA 10 pF

LOGIC OUTPUTS (Except H and RG)

High Level Output Voltage @ IOH = 2 mA V Low Level Output Voltage @ IOL = 2 mA V

2.2 V

0.5 V

RG and H-DRIVER OUTPUTS (H1–H4)

High Level Output Voltage @ Max Current V Low Level Output Voltage @ Max Current V

VDD – 0.5 V

0.5 V

Maximum Output Current (Programmable) 24 mA Maximum Load Capacitance (for Each Output) 100 pF

Specifications subject to change without notice.

REV. A –3–

AD9891/AD9895

AD9891–ANALOG SPECIFICATIONS

(AVDD1, AVDD2 = 3.0 V, f

= 20 MHz, T

CLI

MIN

to T

, unless otherwise noted.)

MAX

Parameter Min Typ Max Unit Notes

CDS

Gain 0 dB Allowable CCD Reset Transient 500 mV Input signal characteristics* Max Input Range before Saturation 1.0 V p-p Max CCD Black Pixel Amplitude ± 200 mV

PIXEL GAIN AMPLIFIER (PxGA)

Max Input Range 1.0 V p-p Max Output Range 1.6 V p-p Gain Control Resolution 64 Steps Gain Monotonicity Guaranteed Gain Range

Min Gain (PxGA Code 32) –2.5 dB Med Gain (PxGA Code 0) +3.5 dB Default setting Max Gain (PxGA Code 31) +9.5 dB

VARIABLE GAIN AMPLIFIER (VGA)

Max Input Range 1.6 V p-p Max Output Range 2.0 V p-p Gain Control Resolution 1024 Steps Gain Monotonicity Guaranteed Gain Range

Low Gain (VGA Code 70) 2 dB Max Gain (VGA Code 1023) 36 dB

BLACK LEVEL CLAMP

Clamp Level Resolution 256 Steps Clamp Level Measured at ADC output

Min Clamp Level 0 LSB Max Clamp Level 63.75 LSB

A/D CONVERTER

Resolution 10 Bits Differential Nonlinearity (DNL) ± 0.4 ± 1.0 LSB No Missing Codes Guaranteed Full-Scale Input Voltage 2.0 V

VOLTAGE REFERENCE

Reference Top Voltage (VRT) 2.0 V Reference Bottom Voltage (VRB) 1.0 V

SYSTEM PERFORMANCE Includes entire signal chain

Gain Accuracy Includes 4 dB default PxGA gain

Low Gain (VGA Code 70) 5 6 7 dB Gain = (0.035  Code) + 3.55 dB

Max Gain (VGA Code 1023) 38.5 39.5 40.5 dB Peak Nonlinearity, 500 mV Input Signal 0.2 % 12 dB gain applied Total Output Noise 0.6 LSB rms AC grounded input, 6 dB gain applied Power Supply Rejection (PSR) 40 dB Measured with step change on supply

Input signal characteristics defined as follows:

500mV TYP

RESET

TRANSIENT

200mV MAX

OPTICAL

BLACK PIXEL

Specifications subject to change without notice.

1V MAX

INPUT

SIGNAL RANGE

REV. A–4–

AD9891/AD9895

AD9895–ANALOG SPECIFICATIONS

(AVDD1, AVDD2 = 3.0 V, f

= 30 MHz, T

CLI

MIN

to T

, unless otherwise noted.)

MAX

Parameter Min Typ Max Unit Notes

CDS

Gain 0 dB Allowable CCD Reset Transient 500 mV Input signal characteristics* Max Input Range before Saturation 1.0 V p-p Max CCD Black Pixel Amplitude ± 200 mV

PIXEL GAIN AMPLIFIER (PxGA)

Max Input Range 1.0 V p-p Max Output Range 1.6 V p-p Gain Control Resolution 64 Steps Gain Monotonicity Guaranteed Gain Range

Min Gain (PxGA Code 32) –2.5 dB Med Gain (PxGA Code 0) +3.5 dB Default setting Max Gain (PxGA Code 31) +9.5 dB

VARIABLE GAIN AMPLIFIER (VGA)

Max Input Range 1.6 V p-p Max Output Range 2.0 V p-p Gain Control Resolution 1024 Steps Gain Monotonicity Guaranteed Gain Range

Low Gain (VGA Code 70) 2 dB Max Gain (VGA Code 1023) 36 dB

BLACK LEVEL CLAMP

Clamp Level Resolution 256 Steps Clamp Level Measured at ADC output

Min Clamp Level 0 LSB Max Clamp Level 255 LSB

A/D CONVERTER

Resolution 12 Bits Differential Nonlinearity (DNL) ± 0.5 ± 1.0 LSB No Missing Codes Guaranteed Full-Scale Input Voltage 2.0 V

VOLTAGE REFERENCE

Reference Top Voltage (VRT) 2.0 V Reference Bottom Voltage (VRB) 1.0 V

SYSTEM PERFORMANCE Includes entire signal chain

Gain Accuracy Includes 4 dB default PxGA gain

Low Gain (VGA Code 70) 5 6 7 dB Gain = (0.035  Code) + 3.55 dB

Max Gain (VGA Code 1023) 38.5 39.5 40.5 dB Peak Nonlinearity, 500 mV Input Signal 0.2 % 12 dB gain applied Total Output Noise 0.8 LSB rms AC grounded input, 6 dB gain applied Power Supply Rejection (PSR) 40 dB Measured with step change on supply

Input signal characteristics defined as follows:

500mV TYP

RESET

TRANSIENT

200mV MAX

OPTICAL

BLACK PIXEL

Specifications subject to change without notice.

1V MAX

INPUT

SIGNAL RANGE

REV. A

–5–

AD9891/AD9895

WARNING!

ESD SENSITIVE DEVICE

TIMING SPECIFICATIONS

(CL = 20 pF, AVDD = DVDD = DRVDD = 3.0 V, f otherwise noted.)

= 20 MHz [AD9891] or 30 MHz [AD9895], unless

CLI

Parameter Symbol Min Typ Max Unit

MASTER CLOCK, CLI (Figure 7)

CLI Clock Period, AD9891 t

CONV

50 ns CLI High/Low Pulsewidth, AD9891 20 25 ns CLI Clock Period, AD9895 t

CONV

33.3 ns CLI High/Low Pulsewidth, AD9895 13 16.7 ns Delay from CLI Rising Edge to Internal Pixel Position 0 t

AFE CLAMP PULSES

CLPDM Pulsewidth 410Pixels CLPOB Pulsewidth

AFE SAMPLE LOCATION

(Figure 13)

(Figure 10) SHP Sample Edge to SHD Sample Edge, AD9891 t SHP Sample Edge to SHD Sample Edge, AD9895 t

DATA OUTPUTS (Figure 12)

Output Delay from DCLK Rising Edge

CLIDLY

220Pixels

20 25 ns 13 16.7 ns

6ns

8ns

Pipeline Delay from SHP/SHD Sampling 9 Cycles

SERIAL INTERFACE (Figures 52 and 53)

Maximum SCK Frequency f SL to SCK Setup Time t SCK to SL Hold Time t SDATA Valid to SCK Rising Edge Setup t SCK Falling Edge to SDATA Valid Hold t SCK Falling Edge to SDATA Valid Read t

NOTES

Parameter is programmable.

Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.

SCLK

10 MHz 10 ns 10 ns 10 ns 10 ns 10 ns

ABSOLUTE MAXIMUM RATINGS

With Respect

Parameter To Min Max Unit

AVDD1, AVDD2 AVSS –0.3 +3.9 V

PACKAGE THERMAL CHARACTERISTICS Thermal Resistance

JA = 61°C/W

= 29.7°C/W



ORDERING GUIDE

TCVDD TCVSS –0.3 +3.9 V HVDD HVSS –0.3 +5.5 V RGVDD RGVSS –0.3 +5.5 V DVDD DVSS –0.3 +3.9 V DRVDD DRVSS –0.3 +3.9 V RG Output RGVSS –0.3 RGVDD + 0.3 V

Model Range Description Option

AD9891KBC –20°C to +85°C CSPBGA BC-64 AD9895KBC –20°C to +85°C CSPBGA BC-64

Temperature Package Package

H1–H4 Output HVSS –0.3 HVDD + 0.3 V Digital Outputs DVSS –0.3 DVDD + 0.3 V Digital Inputs DVSS –0.3 DVDD + 0.3 V SCK, SL, SDATA DVSS –0.3 DVDD + 0.3 V VRT, VRB AVSS –0.3 AVDD + 0.3 V BYP1–BYP3, CCDIN AVSS –0.3 AVDD + 0.3 V Junction Temperature 150 °C Lead Temperature, 10 sec 350 °C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9891 and AD9895 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

REV. A–6–

AD9891 PIN CONFIGURATION

A1 CORNER

INDEX AREA

1234567 9108

A B C

AD9891

TOP

VIEW

(Not to Scale)

D E F G H J K

AD9891/AD9895

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Type2Description

A1 VD DO Vertical Sync Pulse

(Input for Slave Mode, Output for Master Mode)

B1 HD DO Horizontal Sync Pulse

(Input for Slave Mode,

Output for Master Mode) C1 SYNCDIExternal System Sync Input C2 LD/FD DO Line or Field Designator

Output D1 DCLK DO Data Clock Output D2 CLPOB/ DO CLPOB or PBLK Output

PBLK E1 NC Not Internally Connected E2 NC Not Internally Connected F2 DO/SDO DO Data Output (LSB)

(also Serial Data Output

) F1 D1 DO Data Output G2 D2 DO Data Output G1 D3 DO Data Output H2 D4 DO Data Output H1 D5 DO Data Output J2 D6 DO Data Output J1 D7 DO Data Output K2 D8 DO Data Output K1 D9 DO Data Output (MSB) K3 DRVDD P Data Output Driver Supply K4 DRVSS P Data Output Driver Ground J3 VSUB DO CCD Substrate Bias J4 SUBCK DO CCD Substrate Clock

(E-Shutter) K5 V1 DO CCD Vertical Transfer Clock 1 J5 V2 DO CCD Vertical Transfer Clock 2 K6 V3 DO CCD Vertical Transfer Clock 3 J6 V4 DO CCD Vertical Transfer Clock 4 K7 VSG1/V5DO CCD Sensor Gate Pulse 1

(also V5 J7 VSG2/V6DO CCD Sensor Gate Pulse 2

(also V6 K8 VSG3/V7DO CCD Sensor Gate Pulse 3

(also V7

)

J8 VSG4/V8DO CCD Sensor Gate Pulse 4

(also V84)

Pin Mnemonic Type2Description

K9 VSG5 DO CCD Sensor Gate Pulse 5 J9 VSG6DOCCD Sensor Gate Pulse 6 K10 VSG7DOCCD Sensor Gate Pulse 7 J10 VSG8 DO CCD Sensor Gate Pulse 8 H10 H1 DO CCD Horizontal Clock 1 H9 H2 DO CCD Horizontal Clock 2 G10 HVDD P H1–H4 Driver Supply G9 HVSS P H1–H4 Driver Ground F10 H3 DO CCD Horizontal Clock 3 F9 H4 DO CCD Horizontal Clock 4 E10 RGVDD P RG Driver Supply E9 RGVSS P RG Driver Ground D9 RG DO CCD Reset Gate Clock D10 CLO DO Reference Clock Output for

Crystal C10 CLI DI Reference Clock Input B10 TCVDD P Analog Supply for Timing Core C9 TCVSS P Analog Ground for Timing

Core A10 AVDD1 P Analog Supply for AFE B9 AVSS1 P Analog Ground for AFE A9 BYP1 AO Analog Circuit Bypass B8 BYP2 AO Analog Circuit Bypass A8 CCDIN AI CCD Signal Input A7 BYP3 AO Analog Circuit Bypass B7 AVDD2 P Analog Supply for AFE B6 AVSS2 P Analog Ground for AFE A6 REFB AO Voltage Reference Bottom

Bypass A5 REFT AO Voltage Reference Top Bypass B5 SL DI 3-Wire Serial Load Pulse A4 SDI DI 3-Wire Serial Data Input B4 SCK DI 3-Wire Serial Clock A3 MSHUT DO Mechanical Shutter Pulse B3 STROBE DO Strobe Pulse B2 DVSS P Digital Ground A2 DVDD P Digital Supply for VSG,

V1–V4, HD, VD, MSHUT,

STROBE, and Serial Interface

NOTES

See Figure 50 for circuit configuration.

AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, DIO = Digital Input/Output, P = Power.

In Register Readback Mode

In Frame Transfer CCD Mode

REV. A

–7–

AD9891/AD9895

AD9895 PIN CONFIGURATION

A1 CORNER

INDEX AREA

1234567 9108

A B C

AD9895

TOP

VIEW

(Not to Scale)

D E F G H J K

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Type2Description

A1 VD DO Vertical Sync Pulse

(Input for Slave Mode, Output for Master Mode)

B1 HD DO Horizontal Sync Pulse

(Input for Slave Mode,

Output for Master Mode) C1 SYNCDIExternal System Sync Input C2 LD/FD DO Line or Field Designator

Output D1 DCLK DO Data Clock Output D2 CLPOB/ DO CLPOB or PBLK Output

PBLK E2 DO DO Data Output (LSB) E1 D1 DO Data Output F2 D2/SDO DO Data Output

(also Serial Data Output

) F1 D3 DO Data Output G2 D4 DO Data Output G1 D5 DO Data Output H2 D6 DO Data Output H1 D7 DO Data Output J2 D8 DO Data Output J1 D9 DO Data Output K2 D10 DO Data Output K1 D11 DO Data Output (MSB) K3 DRVDD P Data Output Driver Supply K4 DRVSS P Data Output Driver Ground J3 VSUB DO CCD Substrate Bias J4 SUBCK DO CCD Substrate Clock

(also V5 J7 VSG2/V6DO CCD Sensor Gate Pulse 2

(also V6 K8 VSG3/V7DO CCD Sensor Gate Pulse 3

(also V7

)

J8 VSG4/V8DO CCD Sensor Gate Pulse 4

(also V84)

Pin Mnemonic Type2Description

Crystal C10 CLI DI Reference Clock Input B10 TCVDD P Analog Supply for Timing Core C9 TCVSS P Analog Ground for Timing

V1–V4, HD, VD, MSHUT,

STROBE, and Serial Interface

NOTES

See Figure 50 for circuit configuration.

AI = Analog Input, AO = Analog Output, DI = Digital Input,

DO = Digital Output, DIO = Digital Input/Output, P = Power.

In Register Readback Mode

In Frame Transfer CCD Mode

REV. A–8–

AD9891/AD9895

SPECIFICATION DEFINITIONS Differential Nonlinearity (DNL)

An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus, every code must have a finite width. No missing codes guaranteed to 12-bit resolution indicates that all 4096 codes, respectively, must be present over all operating conditions.

Peak Nonlinearity

Peak nonlinearity, a full signal chain specification, refers to the peak deviation of the output of the AD9891/AD9895 from a true straight line. The point used as “zero scale” occurs 0.5 LSB before the first code transition. “Positive full scale” is defined as a level 1 and 0.5 LSB beyond the last code transition. The deviation is measured from the middle of each particular output code to the true straight line. The error is then expressed as a

EQUIVALENT CIRCUITS

AV DD1

percentage of the 2 V ADC full-scale signal. The input signal is always appropriately gained up to fill the ADC’s full-scale range.

Total Output Noise

The rms output noise is measured using histogram techniques. The standard deviation of the ADC output codes is calculated in LSB and represents the rms noise level of the total signal chain at the specified gain setting. The output noise can be converted to an equivalent voltage, using the relationship 1 LSB = (ADC Full

Scale/2

codes) when n is the bit resolution of the ADC. For the

AD9891, 1 LSB is 2 mV, while for the AD9895, 1 LSB is 0.5 mV.

Power Supply Rejection (PSR)

The PSR is measured with a step change applied to the supply pins. The PSR specification is calculated from the change in the data outputs for a given step change in the supply voltage.

DVD D

330

DATA

THREE-

STATE

AVSS1 AVSS1

Figure 1. CCDIN

DVD D

DVSS

Figure 2. Digital Data Outputs

DRVDD

DRVSS

DOUT

RG, H1–H4

ENABLE

DVSS

Figure 3. Digital Inputs

HVDD OR

RGVDD

HVSS OR

RGVSS

Figure 4. H1–H4, RG Drivers

OUTPUT

REV. A

–9–

AD9891/AD9895–Typical Performance Characteristics

440

RGVDD = HVDD = 5.0V

400

360

320

280

POWER DISSIPATION – mW

240

200

VDD = 2.7V

VDD = 3.3V

VDD = 3.0V

SAMPLE RATE – MHz

TPC 1. AD9891 Power vs. Sample Rate

1.0

0.5

725

RGVDD = HVDD = 5.0V

650

VDD = 3.3V

575

VDD = 3.0V

500

425

POWER DISSIPATION – mW

350

275

SAMPLE RATE – MHz

VDD = 2.7V

TPC 4. AD9895 Power vs. Sample Rate

1.0

0.5

–0.5

–1.0

200 600 800

400

TPC 2. AD9891 Typical DNL Performance

OUTPUT NOISE – LSB

200

400

VGA GAIN CODE – LSB

600

800

TPC 3. AD9891 Output Noise vs. VGA Gain

1000

–0.5

–1.0

800 2400 3200

1600

TPC 5. AD9895 Typical DNL Performance

OUTPUT NOISE – LSB

200

400

VGA GAIN CODE – LSB

600

800

TPC 6. AD9895 Output Noise vs. VGA Gain

4000

1000

REV. A–10–

AD9891/AD9895

SYSTEM OVERVIEW

Figure 5 shows the typical system block diagram for the AD9891/ AD9895 used in Master Mode. The CCD output is processed by the AD9891/AD9895’s AFE circuitry, which consists of a CDS, PxGA, VGA, black level clamp, and an A/D converter. The digitized pixel information is sent to the digital image processor chip, which performs the post-processing and compression. To operate the CCD, all CCD timing parameters are programmed into the AD9891/AD9895 from the system microprocessor, through the 3-wire serial interface. From the system master clock, CLI, provided by the image processor or external crystal, the AD9891/ AD9895 generates all of the CCD’s horizontal and vertical clocks and all internal AFE clocks. External synchronization is provided by a SYNC pulse from the microprocessor, which will reset internal counters and resync the VD and HD outputs.

V- DRIVER

H1–H4, RG, VSUB

CCDIN

CCD

MSHUT

STROBE

V1–V4, VSG1–VSG8, SUBCK

AD989x

SERIAL

INTERFACE

P

SYNC

DOUT DCLK

CLPOB/PBLK

LD/FD

HD, VD

CLI

DIGITAL

IMAGE

PROCESSING

ASIC

Figure 5. Typical System Block Diagram, Master Mode

Alternatively, the AD9891/AD9895 may be operated in Slave Mode, in which the VD and HD are provided externally from the image processor. In this mode, all AD9891/AD9895 timing will be synchronized with VD and HD.

The H-drivers for H1–H4 and RG are included in the AD9891/ AD9895, allowing these clocks to be directly connected to the CCD.

H-drive voltage of up to 5 V is supported. An external V-driver is required for the vertical transfer clocks, the sensor gate pulses, and the substrate clock.

The AD9891/AD9895 also includes programmable MSHUT and STROBE outputs, which may be used to trigger mechanical shutter and strobe (flash) circuitry.

Figure 6 shows the horizontal and vertical counter dimensions for the AD9891/AD9895. All internal horizontal and vertical clocking is programmed using these dimensions to specify line and pixel locations.

MAXIMUM FIELD DIMENSIONS

12-BIT HORIZONTAL = 4096 PIXELS MAX

12-BIT VERTICAL = 4096 LINES MAX

Figure 6. Vertical and Horizontal Counters

REV. A

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AD9891/AD9895

PRECISION TIMING HIGH SPEED TIMING GENERATION

The AD9891/AD9895 generates flexible, high speed timing signals using the Precision Timing core. This core is the foundation for generating the timing used for both the CCD and the AFE: the reset gate RG, horizontal drivers H1–H4, and the SHP/SHD sample clocks. A unique architecture makes it routine for the system designer to optimize image quality by providing precise control over the horizontal CCD readout and the AFE correlated double sampling.

The high speed timing of the AD9891/AD9895 operates the same in either Master or Slave Mode configuration.

Timing Resolution

The Precision Timing core uses a 1 master clock input (CLI) as a reference. This clock should be the same as the CCD pixel clock frequency. Figure 7 illustrates how the internal timing core divides the master clock period into 48 steps or edge positions. Using a 20 MHz CLI frequency, the edge resolution of the Precision Timing core is 1 ns. If a 1 system clock is not available, it is also possible to use a 2 reference clock by programming the CLIDIVIDE Register (Addr x01F). The AD9891/ AD9895 will then internally divide the CLI frequency by two.

POSITION

CLI

P[0] P[48] = P[0]P[12] P[24] P[36]

The AD9891/AD9895 also includes a master clock output, CLO, which is the inverse of CLI. This output is intended to be used as a crystal driver. A crystal can be placed between the CLI and CLO Pins to generate the master clock for the AD9891/AD9895. For more information on using a crystal, see Figure 51.

High Speed Clock Programmability

Figure 8 shows how the high speed clocks RG, H1–H4, SHP, and SHD are generated. The RG pulse has programmable rising

and falling edges, and may be inverted using the polarity

control.

The horizontal clocks H1 and H3 have programmable rising and falling edges and polarity control. The H2 and H4 clocks are always inverses of H1 and H3, respectively. Table I summarizes the high speed timing registers and their parameters. Figure 9 shows the typical 2-phase H-clock arrangement in which H3 and H4 are programmed for the same edge location as H1 and H2.

The edge location registers are six bits wide, but there are only 48 valid edge locations available. Therefore, the register values are mapped into four quadrants, with each quadrant containing 12 edge locations. Table II shows the correct register values for

CLIDLY

1 PIXEL PERIOD

NOTES PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (

CLIDLY

= 6ns TYP).

Figure 7. High Speed Clock Resolution from CLI Master Clock Input

CCD

SIGNAL

PROGRAMMABLE CLOCK POSITIONS: 1: RG RISING EDGE 2: RG FALLING EDGE 3: SHP SAMPLE LOCATION 4: SHD SAMPLE LOCATION 5: H1 RISING EDGE POSITION AND 6: H1 FALLING EDGE POSITION (H2 IS INVERSE OF H1) 7: H3 RISING EDGE POSITION AND 8: H3 FALLING EDGE POSITION (H4 IS INVERSE OF H3)

Figure 8. High Speed Clock Programmable Locations

REV. A–12–

AD9891/AD9895

the corresponding edge locations. Figure 10 shows the range and default locations of the high speed clock signals.

H-Driver and RG Outputs

In addition to the programmable timing positions, the AD9891/ AD9895 features on-chip output drivers for the RG and H1–H4 outputs. These drivers are powerful enough to directly drive the CCD inputs. The H-driver current can be adjusted for optimum rise/fall time into a particular load by using the DRV Registers (Addr x0E1 to x0E4). The RG drive current is adjustable using the RGDRV Register (Addr x0E8). Each 3-bit DRV Register is adjustable in 3.5 mA increments, with the minimum setting of 0 equal to OFF or three-state, and the maximum setting of 7 equal to 24.5 mA.

As shown in Figure 11, the H2 and H4 outputs are inverses of H1 and H3, respectively. The internal propagation delay resulting from the signal inversion is less than 1 ns, which is significantly less than the typical rise time driving the CCD load. This results

Table I. H1–H4, RG, SHP, and SHD Timing Parameters

in an H1/H2 crossover voltage at approximately 50% of the output swing. The crossover voltage is not programmable.

Digital Data Outputs

The AD9891/AD9895 data output and DCLK phase are programmable using the DOUTPHASE Register (Addr x01D). Any edge from 0 to 47 may be programmed, as shown in Figure 12. Normally, the DOUT and DCLK signals will track in phase, based on the DOUTPHASE Register contents. The DCLK output phase can also be held fixed with respect to the data outputs, by changing the DCLKMODE Register (Addr x01E) HIGH. In this mode, the DCLK output will remain at a fixed phase equal to CLO (the inverse of CLI) while the data output phase is still programmable.

There is a fixed output delay from the DCLK rising edge to the DOUT transition, called t

. This delay can be programmed to

four values between 0 ns and 12 ns, using the DOUT_DELAY Register (Addr x032). The default value is 8 ns.

POL 1b High/Low Polarity Control for H1, H3, and RG (0 = No Inversion, 1 = Inversion) POSLOC 6b 0–47 Edge Location Positive Edge Location for H1, H3, and RG

Sample Location for SHP, SHD NEGLOC 6b 0–47 Edge Location Negative Edge Location for H1, H3, and RG DRV 3b 0–7 Current Steps Drive Current for H1–H4 and RG Outputs (3.5 mA per Step)

CCD

SIGNAL

H1/H3

H2/H4

USING THE SAME TOGGLE POSITIONS FOR H1 AND H3 GENERATES STANDARD 2-PHASE H-CLOCKING.

Figure 9. 2-Phase H-Clock Operation

Table II. Precision Timing Edge Locations

Quadrant Edge Location (Dec) Register Value (Dec) Register Value (Bin)

I0 to 11 0 to 11 000000 to 001011 II 12 to 23 16 to 27 010000 to 011011 III 24 to 35 32 to 43 100000 to 101011 IV 36 to 47 48 to 59 110000 to 111011

REV. A

–13–

AD9891/AD9895

POSITION

PIXEL

PERIOD

H1/H3

CCD

SIGNAL

NOTES ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD. DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN.

P[0]

RGr[0]

Hr[0]

RGf[12]

P[24]P[12] P[36]

Hf[24]

SHP[28]

Figure 10. High Speed Clock Default and Programmable Locations

H1/H3

H2/H4

RISE

P[48] = P[0]

SHD[48]

RISE

H1/H3

FIXED CROSSOVER VOLTAGE

Figure 11. H-Clock Inverse Phase Relationship

P[0] P[48] = P[0]

PIXEL

PERIOD

DCLK

DOUT

NOTES DATA OUTPUT (DOUT) AND DCLK PHASE ARE ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD. WITHIN 1 CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO 48 DIFFERENT LOCATIONS.

OUTPUT DELAY (

) FROM DCLK RISING EDGE TO DOUT RISING EDGE IS PROGRAMMABLE.

P[12] P[24] P[36]

Figure 12. Digital Output Phase Adjustment

H2/H4

REV. A–14–

AD9891/AD9895

HORIZONTAL CLAMPING AND BLANKING

The AD9891/AD9895’s horizontal clamping and blanking pulses are fully programmable to suit a variety of applications. As with the vertical timing generation, individual sequences are defined for each signal, which are then organized into multiple regions during image readout. This allows the dark pixel clamping and blanking patterns to be changed at each stage of the readout in order to accommodate different image transfer timing and high speed line shifts.

Individual CLPOB, CLPDM, and PBLK Sequences

The AFE horizontal timing consists of CLPOB, CLPDM, and PBLK, as shown in Figure 13. These three signals are independently programmed using the registers in Table III. SPOL is the start polarity for the signal, and TOG1 and TOG2 are the first and second toggle positions of the pulse. All three signals are active low and should be programmed accordingly. Up to four individual sequences can be created for each signal.

123

CLPOB

CLPDM

PBLK

PROGRAMMABLE SETTINGS: 1: START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW) 2: 1ST TOGGLE POSITION 3: 2ND TOGGLE POSITION

CLAMP CLAMP

Figure 13. Clamp and Preblank Pulse Placement

To simplify the programming requirements, the CLPDM signal will track the CLPOB signal by default. If separate control of the CLPDM signal is desired, the SINGLE_CLAMP Register (Addr x031) should be set LOW.

Individual HBLK Sequences

The HBLK programmable timing shown in Figure 14 is similar to CLPOB, CLPDM, and PBLK. However, there is no start polarity control. Only the toggle positions are used to designate the start and the stop positions of the blanking period. Additionally, there is a polarity control, HBLKMASK, that designates the polarity of the horizontal clock signals H1–H4 during the blanking period. Setting HBLKMASK high will set H1 = H3 = Low and H2 = H4 = High during the blanking, as shown in Figure 15. Up to four individual sequences are available for HBLK.

Horizontal Sequence Control

The AD9891/AD9895 use sequence change positions (SCP) and

sequence pointers (SPTR) to organize the individual hori-

HBLK

PROGRAMMABLE SETTINGS: 1: 1ST TOGGLE POSITION = START OF BLANKING 2: 2ND TOGGLE POSITION = END OF BLANKING

BLANK BLANK

Figure 14. Horizontal Blanking (HBLK) Pulse Placement

HBLK

H1/H3

H2/H4

THE POLARITY OF H1 DURING BLANKING IS PROGRAMMABLE (H2 IS OPPOSITE POLARITY OF H1)

REV. A

Figure 15. HBLK Masking Control

–15–

AD9891/AD9895

zontal

sequences. Up to four SCPs are available to divide the readout into four separate regions, as shown in Figure 16. The SCP0 is always hard-coded to line 0, and SCP1–SCP3 are register programmable. During each region bound by the SCP, the

SPTR Registers designate which sequence is used by each

signal.

CLPOB and CLPDM share the same SCP, PBLK has a

separate

set of SCP, and HBLK shares the vertical RCP (see

Vertical Timing Generation section). For example,

CLPSCP1 will define Region 0 for CLPOB and CLPDM, and in that region CLPDM sequences may be selected with the The next SCP defines a new

any of the four individual

CLPOB and

region, and in that region each

SPTR Registers.

signal can be assigned to a different individual sequence. Because HBLK shares the vertical RCP, there are up to eight regions where HBLK sequences may be changed using the eight HBLKSPTR Registers.

Table III. CLPOB, CLPDM, and PBLK Individual Sequence Parameters

SPOL 1b High/Low Starting Polarity of Vertical Transfer Pulse for Sequences 0–3 TOG1 12b 0–4095 Pixel Location First Toggle Position within Line for Sequences 0–3 TOG2 12b 0–4095 Pixel Location Second Toggle Position within Line for Sequences 0–3

Table IV. HBLK Individual Sequence Parameters

HBLKMASK 1b High/Low Masking Polarity for H1 for Sequences 0–3 (0 = H1 Low, 1 = H1 High) HBLKTOG1 12b 0–4095 Pixel Location First Toggle Position within Line for Sequences 0–3 HBLKTOG2 12b 0–4095 Pixel Location Second Toggle Position within Line for Sequences 0–3

Table V. Horizontal Sequence Control Parameters for CLPOB, CLPDM, and PBLK

SCP1–SCP3 12b 0–4095 Line Number CLPOB/PBLK SCP to Define Horizontal Regions 0–3 SPTR0–SPTR3 2b 0–3 Sequence Number Sequence Pointer for Horizontal Regions 0–3

Table VI. Horizontal Sequence Control Parameters for HBLK

VTPRCP1– 12b 0–4095 Line Number Vertical Region Change Positions (See Table IX.) VTPRCP7

HBLKSPTR0– 2b 0–3 Sequence Number Sequence Pointer for HBLK Regions 0–7 HBLKSPTR7

SEQUENCE CHANGE POSITION #0

SEQUENCE CHANGE POSITION #1

SEQUENCE CHANGE POSITION #2

SEQUENCE CHANGE POSITION #3

UP TO FOUR INDIVIDUAL HORIZONTAL CLAMP AND BLANKING REGIONS MAY BE PROGRAMMED WITHIN A SINGLE FIELD, USING THE SEQUENCE CHANGE POSITIONS.

(V-COUNTER = 0)

SINGLE FIELD (1 VD INTERVAL)

CLAMP AND PBLK SEQUENCE REGION 1

CLAMP AND PBLK SEQUENCE REGION 2

CLAMP AND PBLK SEQUENCE REGION 3

CLAMP AND PBLK SEQUENCE REGION 4

Figure 16. Clamp and Blanking Sequence Flexibility

REV. A–16–

AD9891/AD9895

VERTICAL TIMING GENERATION

The AD9891/AD9895 provide a very flexible solution for generating vertical CCD timing and can support multiple CCDs and different system architectures. The 4-phase vertical transfer clocks V1–V4 are used to shift each line of pixels into the horizontal output register of the CCD. The AD9891/AD9895 allow these outputs to be individually programmed into different pulse patterns. Vertical sequence control registers then organize the individual vertical pulses into the desired CCD vertical timing arrangement.

Figure 17 shows an overview of how the vertical timing is generated in three basic steps. First, the individual pulse patterns or

CREATE THE INDIVIDUAL VERTICAL SEQUENCES (MAXIMUM OF 12 SEQUENCES).

SEQUENCE 0

SEQUENCE 1

SEQUENCE 2

SEQUENCE 3

SEQUENCE 4

SEQUENCE 5

SEQUENCE 6

SEQUENCE 7

SEQUENCE 8

SEQUENCE 9

SEQUENCE 10

SEQUENCE 11

sequences are created by using the Vertical Transfer Pulse (VTP) Registers. These sequences are a essentially a “pool” of pulse patterns that may be assigned to any of the V1-V4 outputs. Second, individual regions are built by assigning a sequence to each of the V1–V4 outputs. Up to five unique regions may be specified. Finally, the readout of the entire field is constructed by combining one or more of the individual regions sequentially. With up to eight region areas available, different steps of the readout such as high speed line shifts and vertical image transfer can be supported.

BUILD THE INDIVIDUAL VERTICAL REGIONS BY ASSIGNING EACH SEQUENCE TO V1–V4 OUTPUTS (MAXIMUM OF 5 REGIONS).

REGION 0 V1 (SEQ 0)

V2 (SEQ 0*)

V3 (SEQ 1)

V4 (SEQ 1*)

REGION 1 V1 (SEQ 2)

V2 (SEQ 3)

V3 (SEQ 4)

V4 (SEQ 5)

BUILD THE ENTIRE FIELD READOUT BY COMBINING MULTIPLE REGIONS (MAXIMUM OF 8 COMBINATIONS).

USE REGION 2 FOR LINES 1 TO 20

USE REGION 1 FOR LINE 21

USE REGION 0 FOR LINES 22 TO 2000

USE REGION 2 FOR LINES 2001 TO 2020

Figure 17. Summary of Vertical Timing Generation

REGION 4 V1 (SEQ 6)

V2 (SEQ 6*)

V3 (SEQ 7)

V4 (SEQ 7*)

*SEQUENCES MAY BE SHIFTED AND/OR INVERTED

REV. A

–17–

AD9891/AD9895

Individual Vertical Sequences

To generate the individual vertical sequences or patterns shown in Figure 18, five registers are required for each sequence. Table VII summarizes these registers and their respective bit lengths. polarity of

The start polarity (VTPPOL) determines the starting

the vertical sequence and can be programmed high or low. The first toggle position (VTPTOG1) and second toggle position (VTPTOG2) are the pixel locations within the

line where the pulse transitions. A third toggle position (VTPTOG3) is also available for sequences 0 through 7. All toggle positions are 10-bit values, which limits the placement of a pulse to within 1024 pixels of a line. A separate register, VSTART, sets the start position of the sequence within the line (see Individual Vertical Regions section). The Length (VTPLEN) Register determines the number of pixels between each of the pulse repetitions, if any repetitions have been programmed. The number of repetitions (VTPREP) simply determines the number of pulse repetitions desired within a

single line. Programming “1” for VTPREP gives a single pulse, while setting to “0” will provide a fixed dc output based on the start polarity value. There is a total of 12 individual sequences that may be programmed.

When specifying the individual regions, each sequence may be assigned to any of the V1–V4 outputs. For example, Figure 19 shows a typical 4-phase V-clock arrangement. Two different sequences are needed to generate the different pulsewidths. The use of individual start positions for V1–V4 allows the four outputs to be generated from two sequences. Figure 20 shows a slightly different V-clock arrangement in which V2, V3, and V4 are simply shifted and/or inverted versions of V1. Only one individual sequence is needed because all signals have the same pulsewidth. The invert sequence registers (VINV) are used for V3 and V4 (see Table VII).

Note that for added flexibility, the VTPPOL Registers (Start Polarity) may be used as an extra toggle position.

Table VII. Individual VTP Sequence Parameters

VTPPOL 1b High/Low Starting Polarity of Vertical Transfer Pulse for Each Sequence 0–11 VTPTOG1 10b 0–1023 Pixel Location First Toggle Position within Line for Each Sequence 0–11 VTPTOG2 10b 0–1023 Pixel Location Second Toggle Position within Line for Each Sequence 0–11 VTPTOG3 10b 0–1023 Pixel Location Third Toggle Position within Line for Each Sequence 0–7 VTPLEN 10b 0–1023 Pixels Length between Pulse Repetitions for Each Sequence 0–11 VTPREP 12b 0–4095 Pulses Number of Pulse Repetitions for Each Sequence 0–11 (0 = DC Output)

START POSITION OF SEQUENCE IS INDIVIDUALLY PROGRAMMABLE FOR EACH V1–V4 OUTPUT

V1–V4

PROGRAMMABLE SETTINGS FOR EACH SEQUENCE: 1: START POLARITY 2: 1ST TOGGLE POSITION 3: 2ND TOGGLE POSITION (THERE IS ALSO A 3RD TOGGLE POSITION AVAILABLE FOR SEQUENCES 0 TO 7) 4: LENGTH BETWEEN REPEATS 5: NUMBER OF REPEATS

Figure 18. Individual Vertical Sequence Programmability

V1 USES SEQUENCE 0

V2 USES SEQUENCE 0, WITH DIFFERENT START POSITION

V3 USES SEQUENCE 1

V4 USES SEQUENCE 1, WITH DIFFERENT START POSITION

Figure 19. Example of Separate V1–V4 Signals Using Two Individual Sequences

REV. A–18–

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