ANALOG DEVICES AD9888 Service Manual

100 MSPS/140 MSPS/170 MSPS

Data Sheet

FEATURES

170 MSPS maximum conversion rate 500 MHz programmable analog bandwidth

0.5 V to 1.0 V analog input range Less than 450 ps p-p PLL clock jitter at 170 MSPS

3.3 V power supply Full sync processing Sync detect for hot plugging 2:1 analog input mux 4:2:2 output format mode Midscale clamping Power-down mode Low power: <1 W typical at 170 MSPS

APPLICATIONS

RGB graphics processing LCD monitors and projectors Plasma display panels Scan converters Microdisplays Digital TV

Analog Flat Panel Interface

AD9888

FUNCTIONAL BLOCK DIAGRAM

AIN

HSYNC0

HSYNC1

VSYNC0

VSYNC1

SOGIN0

SOGIN1

COAST

CLAMP

CKINV

CKEXT

FILT

SCL SDA

2:1

MUX

2:1

MUX

2:1

MUX

2:1

MUX

2:1

MUX

2:1

MUX

CLAMP

SYNC

PROCESSING

AND CLOCK

GENERATION

SERIAL REG ISTER

POWER MANAGEMENT

ADC

AND

Figure 1.

REF

AD9888

RA[7:0]

DRB

[7:0]

DGA

[7:0]

DGB

[7:0]

DBA

[7:0]

DBB

[7:0]

DATACK

HSOUT

VSOUT

SOGOUT

REF BYPASS

02442-001

GENERAL DESCRIPTION

The AD9888 is a complete 8-bit, 170 MSPS, monolithic analog interface optimized for capturing RGB graphics signals from personal computers and workstations. Its 170 MSPS encode rate capability and full-power analog bandwidth of 500 MHz supports resolutions of up to 1600 × 1200 (UXGA) at 75 Hz.

For ease of design and to minimize cost, the AD9888 is a fully integrated interface solution for flat panel displays. The AD9888 includes an analog interface that has a 170 MHz triple ADC with an internal 1.25 V reference phase-locked loop (PLL) to generate a pixel clock from HSYNC and COAST; midscale clamping; and programmable gain, offset, and clamp controls. The user provides only a 3.3 V power supply, analog input, and HSYNC and COAST signals. Three-state CMOS outputs can be powered from 2.5 V to 3.3 V.

The on-chip PLL of the AD9888 generates a pixel clock from the HSYNC and COAST inputs. Pixel clock output frequencies

range from 10 MHz to 170 MHz. PLL clock jitter is typically less than 450 ps p-p at 170 MSPS. When the COAST signal is presented, the PLL maintains its output frequency in the absence of HSYNC. A sampling phase adjustment is provided. Data, HSYNC, and clock output phase relationships are maintained. The PLL can be disabled, and an external clock input can be provided as the pixel clock. The AD9888 also offers full sync processing for composite sync and sync-on-green applications.

A CLAMP signal is generated internally or can be provided by the user through the CLAMP input pin. This device is fully programmable via a 2-wire serial port.

Fabricated in an advanced CMOS process, the AD9888 is provided in a space-saving, 128-lead, MQFP, surface-mount, plastic package and is specified over the 0°C to 70°C temperature range. The AD9888 is also available in a Pb-free package.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9888 Data Sheet

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 3

Specifications..................................................................................... 4

Absolute Maximum Ratings............................................................ 6

Explanation of Test Levels ........................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Design Guide................................................................................... 12

General Description................................................................... 12

Input Signal Handling................................................................ 12

Sync Processing Overview ........................................................ 12

HSYNC and VSYNC Inputs...................................................... 12

Serial Control Port .....................................................................12

Output Signal Handling............................................................. 12

Clamping .....................................................................................12

Gain and Offset Control............................................................ 13

Sync-on-Green Input ................................................................. 14

Clock Generation ....................................................................... 14

Alternate Pixel Sampling Mode................................................ 16

Timing.......................................................................................... 17

2-Wire Serial Register Map........................................................... 21

2-Wire Serial Control Register Details........................................ 24

Chip Identification..................................................................... 24

PLL Divider Control.................................................................. 24

Clock Generator Control .......................................................... 24

Clamp Timing............................................................................. 24

HSYNC Pulse Width.................................................................. 25

Input Gain................................................................................... 25

Input Offset................................................................................. 25

Sync Control ............................................................................... 25

Input Control .............................................................................. 26

Mode Control 1 .......................................................................... 29

2-Wire Serial Control Port............................................................ 31

Data Transfer via Serial Interface............................................. 31

Sync Processing .......................................................................... 32

Sync Slicer.................................................................................... 33

Sync Separator ............................................................................ 33

PCB Layout Recommendations.................................................... 34

Analog Interface Inputs............................................................. 34

Power Supply Bypassing............................................................ 34

PLL ............................................................................................... 34

Outputs (Both Data and Clocks).............................................. 34

Digital Inputs .............................................................................. 35

Voltage Reference ....................................................................... 35

Outline Dimensions....................................................................... 36

Ordering Guide .......................................................................... 36

Rev. C | Page 2 of 36

Data Sheet AD9888

REVISION HISTORY

12/11—Rev. B to Rev. C

Updated Format.................................................................. Universal

Deleted AD9888AKSZ-205 Model .................................. Universal

Changed Maximum Conversion Rate from

205 MSPS to 170 MSPS............................................ Throughout

Changes to Figure 1 and General Description..............................1

Deleted AD9888KS-205 Columns, Changes to t

Parameter,

DHO

Table 1 .............................................................................................4

Changes to Output Voltage, Low (V

) Parameter, Table 1;

Moved Figure 2..............................................................................5

Changes to Table 2 and ESD Caution Section...............................6

Changes to Table 3 ............................................................................8

Changes to Table 4 ............................................................................9

Changes to YUV Clamping Section and to Gain and Offset

Control Section............................................................................13

Changes to Sync-on-Green Input Section and to Figure 8........14

Changes to Table 5 ..........................................................................15

Moved Figure 10, Figure 11, and Figure 12 .................................16

Changes to Captions of Figure 16 Through Figure 25...............17

Changes to Table 8 ..........................................................................21

Changes to Chip Identification Section .......................................24

Changes to Table 14 and Table 17 .................................................26

Changes to Address 0x10[7:3]—Sync-on-Green Slicer Threshold

Section and to Address 0x11[7:0]—Sync Separator Threshold

Section ..........................................................................................27

Changes to Address 0x14[6]—Active HSYNC (AHS) Section,

Added Table 29, Changes to Address 0x14[3]—Active

VSYNC (AVS) Section, Added Table 33, Changes to

Table 34.........................................................................................28

Changes to Address 0x15[6]—Output Mode Section and to

Address 0x15[5]—A/B Invert Control (OUTPHASE)

Section ..........................................................................................29

Moved Figure 26..............................................................................31

Moved Figure 27..............................................................................32

Changes to Outputs (Both Data and Clocks) Section................34

Changes to Voltage Reference Section .........................................35

Updated Outline Dimensions........................................................36

Changes to Ordering Guide...........................................................36

3/03—Rev. A to Rev. B

Changes to Specifications ...............................................................2

Changes to Pin Configuration.........................................................4

Changes to Table II .........................................................................11

Changes to Table IV........................................................................11

Changes to Figure 20 ......................................................................16

Changes to Figure 22 ......................................................................17

Changes to Table V .........................................................................17

Changes to Table VI........................................................................20

Changes to Table XIII ..................................................................... 22

Changes to Clamp Input Signal Source Section..........................22

Changes to Table XXX....................................................................24

Added text to Outputs (Both Data and Clocks) Section ...........29

Updated Outline Dimensions........................................................30

1/02—Rev. 0 to Rev. A.

Change to Title–Part Name ............................................................. 1

Change to Pin Function Detail, CKINV Section..........................7

Change to Figure 13.......................................................................... 5

Change to Figure 14........................................................................15

Change to Figure 15........................................................................16

Change to Figure 16........................................................................16

Change to Figure 17........................................................................17

Change to Figure 18 .......................................................................17

Change to Figure 21........................................................................19

Change to Figure 22........................................................................19

7/01—Revision 0: Initial Version

Rev. C | Page 3 of 36

AD9888 Data Sheet

SPECIFICATIONS

VD = 3.3 V, VDD = 3.3 V, ADC clock = maximum conversion rate.

Table 1.

AD9888KSZ-100/-1401 AD9888KSZ-170

Te st

Parameter Temp

RESOLUTION 8 8 Bits DC ACCURACY

Differential Nonlinearity 25°C I ±0.5 ±1.25/−1.0 ±0.6 +1.25/−1.0 LSB Full VI +1.35/−1.0 +1.50/−1.0 LSB Integral Nonlinearity 25°C I ±0.5 ±2.0 ±0.75 ±2.25 LSB Full VI ±2.5 ±2.75 LSB No Missing Codes 25°C I Guaranteed Guaranteed

ANALOG INPUT

Input Voltage Range

Minimum 25°C I 0.5 0.5 V p-p Maximum 25°C I 1.0 1.0 V p-p

Gain Temperature Coefficient 25°C V 100 100 ppm/°C Input Bias Current 25°C IV 1 1 μA

Full IV 2 2 μA

Input Capacitance Full V 3 3 pF Input Resistance Full IV 1 1 M Input Offset Voltage Full VI 7 90 7 90 mV Input Full-Scale Matching Full VI 2.5 9.0 2.5 9.0 % FS Offset Adjustment Range Full VI 44 49 53 44 49 53 % FS

REFERENCE OUTPUT

Output Voltage Full VI 1.20 1.25 1.30 1.20 1.25 1.30 V Temperature Coefficient Full V ±50 ±50 ppm/°C

SWITCHING PERFORMANCE

Maximum Conversion Rate Full VI 100/140 170 MSPS Minimum Conversion Rate Full IV 10 10 MSPS Clock to Data Skew (t

) Full IV −1.25 +1.25 −1.25 +1.25 ns

skew

I2C Timing2

Full VI 4.7 4.7 μs

BUFF

Full VI 4.0 4.0 μs

STAH

Full VI 250 250 ns

DHO

Full VI 4.7 4.7 μs

DAL

Full VI 4.0 4.0 μs

DAH

Full VI 250 250 ns

DSU

Full VI 4.7 4.7 μs

STASU

Full VI 4.0 4.0 μs

STOSU

HSYNC Input Frequency Full IV 15 110 15 110 kHz Maximum PLL Clock Rate Full VI 100/140 170 MHz Minimum PLL Clock Rate Full IV 10 10 MHz PLL Jitter3 25°C IV 470 700 450 700 ps p-p Full IV 1000 1000 ps p-p Sampling Phase Temperature

Full IV 15 15 ps/°C

Coefficient

Level Min Typ Max Min Typ Max Unit

Rev. C | Page 4 of 36

Data Sheet AD9888

AD9888KSZ-100/-1401 AD9888KSZ-170

Te st

Parameter Temp

DIGITAL INPUTS Full

Input Voltage, High (VIH) Full VI 2.5 2.5 V

Input Voltage, Low (VIL) Full VI 0.8 0.8 V

Input Current, High (IIH) Full IV −1.0 −1.0 μA

Input Current, Low (IIL) Full IV +1.0 +1.0 μA

Input Capacitance 25°C V 3 3 pF DIGITAL OUTPUTS

Output Voltage, High (VOH) Full VI VD − 0.1 VD − 0.1 V

Output Voltage, Low (VOL) Full VI 0.1 V

Duty Cycle Full

DATACK, DATACK

Full IV 44 49 55 44 49 55 %

Output Coding Full IV Binary Binary

POWER SUPPLY

Analog Power Supply Voltage (VD) Full IV 3.0 3.3 3.6 3.0 3.3 3.6 V

Output Power Supply Voltage (VDD) Full IV 2.2 3.3 3.6 2.2 3.3 3.6 V

PLL Power Supply Voltage (PVD) Full IV 3.0 3.3 3.6 3.0 3.3 3.6 V

Analog Power Supply Current (ID) 25°C 200 215 mA

Output Power Supply Current (IDD)4 25°C 50 55 mA

PLL Power Supply Current (IPVD) 25°C 8 9 mA

Total Power Dissipation Full VI 850 1050 920 1150 mW

Power-Down Supply Current Full VI 12 20 12 20 mA

Power-Down Dissipation Full VI 40 66 40 66 mW DYNAMIC PERFORMANCE

Analog Bandwidth, Full Power5 25°C V 500 500 MHz

Transient Response 25°C V 2 2 ns

Overvoltage Recovery Time 25°C V 1.5 1.5 ns

Signal-to-Noise Ratio (SNR)6 25°C IV 42 45 41 44 dB

Without Harmonics, fIN = 40.7 MHz Full V 44 43 dB

Crosstalk Full V 50 50 dBc THERMAL CHARACTERISTICS

Junction-to-Case Thermal

Resistance (θ

)

Junction-to-Ambient Thermal

Resistance (θ

AD9888JS-100 specifications are tested at 100 MHz. AD9888KS-140 specifications are tested at 140 MHz.

See Figure 2.

The maximum specifications for the AD9888KS-100 and AD9888KS-140 were obtained with VCO range = 10, charge pump current = 100, PLL divider = 1693. The

maximum specifications for the AD9888KS-170 were obtained with VCO range = 11, charge pump current = 100, PLL divider = 2159.

DEMUX = 1, DATACK and

Maximum bandwidth setting. Bandwidth can also be programmed to 300 MHz, 150 MHz, or 75 MHz.

Using an external pixel clock.

)

DATACK

load = 15 pF, data load = 5 pF.

V 8.4 8.4 °C/W

V 35 35 °C/W

Level

Min Typ Max Min Typ Max Unit

SDA

SCL

BUFF

STAH

DHOtDSU

DAL

DAH

STASU

STOSU

02442-025

Figure 2. Serial Port Read/Write Timing

Rev. C | Page 5 of 36

AD9888 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

VD 3.6 V VDD 3.6 V Analog Inputs VD to 0.0 V REF BYBASS VD to 0.0 V Digital Inputs 5 V to 0.0 V Digital Output Current 20 mA Operating Temperature Range −25°C to +85°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C Maximum Case Temperature 150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

EXPLANATION OF TEST LEVELS

I. 100% production tested.

II. 100% production tested at 25°C; sample tested at

specified temperatures.

III. Sample tested only.

IV. Parameter is guaranteed by design and characterization

testing.

V. Parameter is a typical value only.

VI. 100% production tested at 25°C; guaranteed by design

and characterization testing.

ESD CAUTION

Rev. C | Page 6 of 36

Data Sheet AD9888

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

REF BYPASS

GND

AIN

RMIDSCV

GND

SOGIN0

AIN

GND

SOGIN1

AIN

GND

AIN

GND

AIN

BMIDSCV

GND

CKINV

CLAMP

SDA

SCL

GND

A D

115

114

113

CKEXT

COAST

GND

112

110

111

GND

106

109

108

107

B D

105

104

103

102

101

GND

100

GND

DGA

GND

DGB

GND

DBA

GND

02442-002

GND

SOGOUT

HSOUT

VSOUT

127

128

126

125

PIN 1

GND41GND

VSYNC1

DATACK

124

HSYNC1

DATACK

123

VSYNC0

122

HSYNC0

GND

121

120

119

GND

117

118

AD9888

TOP VIEW

(Not to Scale)

FILT

GND

116

GND

Figure 3. Pin Configuration

Rev. C | Page 7 of 36

AD9888 Data Sheet

Table 3. Complete Pinout List

Pin Type Mnemonic Description Value Pin No.

Analog Video Inputs R G B R G B Sync/Clock Inputs HSYNC0 Channel 0 Horizontal Sync Input. 3.3 V CMOS 45 VSYNC0 Channel 0 Vertical Sync Input. 3.3 V CMOS 44 SOGIN0 Channel 0 Sync-on-Green Input. 0.0 V to 1.0 V 12 HSYNC1 Channel 1 Horizontal Sync Input. 3.3 V CMOS 43 VSYNC1 Channel 1 Vertical Sync Input. 3.3 V CMOS 42 SOGIN1 Channel 1 Sync-on-Green Input. 0.0 V to 1.0 V 16 CLAMP Clamp Input (external CLAMP signal). 3.3 V CMOS 30 COAST PLL Coast Signal Input. 3.3 V CMOS 53 CKEXT CKINV ADC Sampling Clock Invert. 3.3 V CMOS 29 Sync Outputs HSOUT Horizontal Sync Output Clock (phase-aligned with DATACK). 3.3 V CMOS 125 VSOUT Vertical Sync Output Clock (phase-aligned with DATACK). 3.3 V CMOS 127 SOGOUT Sync-on-Green Slicer Output. 3.3 V CMOS 126 Voltage REF BYPASS Internal Reference Bypass (bypass with 0.1 μF to ground). 1.25 V ± 10% 2 Clamp Voltages RMIDSCV Red Channel Midscale Clamp Voltage Bypass. 9 BMIDSCV Blue Channel Midscale Clamp Voltage Bypass. 24 PLL Filter FILT Connection for External Filter Components for Internal PLL. 50 Power Supply VD Analog Power Supply. 3.3 V ± 10% 1, 6, 7, 10,

PVD PLL Power Supply. 3.3 V ± 10% 38, 39, 47,

GND Ground. 0 V 3, 4, 11, 15,

Serial Port SDA Serial Port Data I/O. 3.3 V CMOS 31

(2-Wire Serial Interface) SCL Serial Port Data Clock. 3.3 V CMOS 32 A0 Serial Port Address Input 1. 3.3 V CMOS 33 Data Outputs DRA D D D D D Data Clock Output DATACK Data Output Clock. 3.3 V CMOS 123

0 Channel 0 Analog Input for Converter R. 0.0 V to 1.0 V 5

AIN

0 Channel 0 Analog Input for Converter G. 0.0 V to 1.0 V 13

AIN

0 Channel 0 Analog Input for Converter B. 0.0 V to 1.0 V 20

AIN

1 Channel 1 Analog Input for Converter R. 0.0 V to 1.0 V 8

AIN

1 Channel 1 Analog Input for Converter G. 0.0 V to 1.0 V 17

AIN

1 Channel 1 Analog Input for Converter B. 0.0 V to 1.0 V 23

AIN

External Pixel Clock Input (to bypass the PLL), or 10 k

Ω to ground.

3.3 V CMOS 54

18, 21, 25, 26, 34, 37

Output Power Supply. 3.3 V ± 10% 56, 69, 79,

89, 98, 102, 112, 122

48, 52

19, 22, 27, 28, 35, 36, 40, 41, 46, 49, 51, 55, 65 to 68, 78, 88, 99 to 101, 111, 121, 128

Port A Outputs of Converter Red. Bit 7 is the MSB. 3.3 V CMOS 113 to 120

[7:0]

Port B Outputs of Converter Red. Bit 7 is the MSB. 3.3 V CMOS 103 to 110

RB[7:0]

Port A Outputs of Converter Green. Bit 7 is the MSB. 3.3 V CMOS 90 to 97

GA[7:0]

Port B Outputs of Converter Green. Bit 7 is the MSB. 3.3 V CMOS 80 to 87

GB[7:0]

Port A Outputs of Converter Blue. Bit 7 is the MSB. 3.3 V CMOS 70 to 77

BA[7:0]

Port B Outputs of Converter Blue. Bit 7 is the MSB. 3.3 V CMOS 57 to 64

BB[7:0]

DATACK

Data Output Clock Complement. 3.3 V CMOS 124

Rev. C | Page 8 of 36

Data Sheet AD9888

Table 4. Pin Function Descriptions

Mnemonic Description

Inputs

0 Channel 0 Analog Input for Red.

AIN

0 Channel 0 Analog Input for Green.

AIN

0 Channel 0 Analog Input for Blue.

AIN

1 Channel 1 Analog Input for Red.

AIN

1 Channel 1 Analog Input for Green.

AIN

1 Channel 1 Analog Input for Blue.

AIN

HSYNC0 Channel 0 Horizontal Sync Input. HSYNC1 Channel 1 Horizontal Sync Input.

VSYNC0 Channel 0 Vertical Sync Input. VSYNC1 Channel 1 Vertical Sync Input. These are the inputs for vertical sync. SOGIN0 Channel 0 Sync-on-Green Input. SOGIN1 Channel 1 Sync-on-Green Input.

CLAMP External Clamp Input.

COAST Clock Generator Coast Input (optional).

CKEXT External Clock Input (optional).

CKINV Sampling Clock Inversion (optional).

These high impedance inputs accept red, green, and blue channel graphics signals, respectively. The six channels are identical and can be used for any color; colors are assigned for convenient reference. They accommodate input signals ranging from 0.5 V to 1.0 V full scale. Signals should be ac-coupled to these pins to support clamp operation.

These inputs receive a logic signal that establishes the horizontal timing reference and provides the frequency reference for pixel clock generation. The logic sense of this pin is controlled by the HSYNC input polarity control (Register 0x0E, Bit 6). Only the leading edge of HSYNC is used by the PLL. The trailing edge is used for clamp timing only. When the HSYNC input polarity control = 0, the falling edge of HSYNC is used. When the HSYNC polarity control = 1, the rising edge is active. The input includes a Schmitt trigger for noise immunity, with a nominal input threshold of 1.5 V.

These inputs are provided to assist in processing signals with embedded sync, typically on the green channel. These pins are connected to a high speed comparator with an internally generated, variable threshold level, which is nominally set to

0.15 V above the negative peak of the input signal. When connected to an ac-coupled graphics signal with embedded sync, these pins produce a noninverting digital output on SOGOUT. This output is usually a composite sync signal, containing both vertical and horizontal sync information. When not used, these inputs should be left unconnected. For more details about this function and how it should be configured, see the Sync-on-Green Input section.

This logic input can be used to define the time during which the input signal is clamped to the reference dc level (to ground for RGB or to midscale for YUV). It should be used when the reference dc level is known to be present on the analog input channels, typically during a period following HSYNC, called the back porch, when a good black reference is provided. The CLAMP pin is enabled by setting the external clamp control (Register 0x0F, Bit 7) to 1 (default is 0). When disabled, this pin is ignored and the clamp timing is determined internally by counting a delay and duration from the trailing edge of the HSYNC input. The logic sense of this pin is controlled by the clamp polarity control (Register 0x0F, Bit 6). When not used, this pin should be grounded and the external clamp should be programmed to 0.

This input can be used to stop the pixel clock generator from synchronizing with HSYNC while continuing to produce a clock at its current frequency and phase. This is useful when processing signals from sources that fail to produce horizontal sync pulses during the vertical interval or that include equalization pulses. The COAST signal is usually not required for PC generated signals. The logic sense of this pin is controlled by the coast polarity control (Register 0x0F, Bit 3). When this pin is not used, either ground the pin and program the coast polarity to 1 or tie the pin high (to V

through a 10 kΩ resistor)

and program the coast polarity to 0. The coast polarity register bit defaults to 1 at power-up.

This pin can be used to provide an external clock to the AD9888 in place of the clock internally generated from HSYNC. The external clock is enabled by programming the external clock select bit (Register 0x15, Bit 0) to 1. When an external clock is used, all other internal functions operate normally. When not used, this pin should be tied through a 10 kΩ resistor to ground, and the external clock register should be programmed to 0. The clock phase adjustment still operates when an external clock source is used.

This pin can be used to invert the pixel sampling clock, which has the effect of shifting the sampling phase 180°. This supports the alternate pixel sampling mode, wherein higher frequency input signals (up to 410 MSPS) can be captured by first sampling the odd pixels, and then capturing the even pixels on the subsequent frame. This pin should be used only during blanking intervals (typically vertical blanking) because it might produce several samples of corrupted data during the phase shift. When not in use, this pin should be grounded.

Rev. C | Page 9 of 36

AD9888 Data Sheet

Mnemonic Description

Outputs

DRA

Data Output, Red Channel, Port A.

[7:0]

DRB

Data Output, Red Channel, Port B.

[7:0]

DGA

Data Output, Green Channel, Port A.

[7:0]

DGB

Data Output, Green Channel, Port B.

[7:0]

DBA

Data Output, Blue Channel, Port A.

[7:0]

DBB

Data Output, Blue Channel, Port B.

[7:0]

DATACK,

DATACK

HSOUT Horizontal Sync Output.

VSOUT Verical Sync Output.

SOGOUT Sync-on-Green (SOG) Slicer Output.

REF BYPASS Internal Reference Bypass.

RMIDSCV Red Channel Midscale Voltage Bypass.

BMIDSCV Blue Channel Midscale Voltage Bypass.

FILT

Power Supply

VDD Digital Output Power Supply.

PVD Clock Generator Power Supply.

Each channel has two ports. When the part is operated in single-channel mode (channel mode bit (Register 0x15, Bit 7) = 0), all data is presented to Port A, and Port B is placed in a high impedance state. Programming the channel mode bit to 1 establishes dual-channel mode, where pixels are alternately presented to Port A and Port B of each channel. These appear simultaneously; two pixels are presented at the time of every second input pixel when the output mode bit (Register 0x15, Bit 6) is set to 1 (parallel mode). When the output mode bit is set to 0, pixel data appear alternately on the two ports, one new sample with each incoming pixel (interleaved mode). In dual-channel mode, the first pixel after HSYNC is routed to Port A. The second pixel goes to Port B, the third to Port A, and so on. This can be reversed by setting the A/B invert control bit (Register 0x15, Bit 5) to 1. The delay from the pixel sampling time to the output is fixed. When the sampling time is changed by adjusting the clock phase adjust register (Register 0x04, Bits[7:3]), the output timing is shifted as well. The DATACK, DATACK, and HSOUT outputs are also moved; therefore, the timing relationship among the signals is maintained.

Data Output Clock, Data Output Clock Complement.

These are differential data clock output signals to be used to strobe the output data and HSOUT into external logic. They are produced by the internal clock generator and are synchronous with the internal pixel sampling clock. When the AD9888 is operated in single-channel mode, the output frequency is equal to the pixel sampling frequency. When operated in dualchannel mode, the clock frequency is half the pixel frequency, as is the output data frequency. When the sampling time is changed by adjusting the clock phase adjust register (Register 0x04, Bits[7:3]), the output timing is shifted as well. The data, DATACK, DATACK, and HSOUT outputs are all moved; therefore, the timing relationship among the signals is maintained.

Either or both signals can be used, depending on the timing mode and interface design used.

This is a reconstructed, phase-aligned version of the HSYNC input. Both the polarity and duration of this output can be

DATACK

programmed via serial bus registers. By maintaining alignment with DATACK,

, and data, data timing with respect

to horizontal sync can always be determined.

This pin can be programmed to output either the sync-on-green slicer comparator or an unprocessed but delayed version of the HSYNC input. See the sync processing block diagram (Figure 27) to view how this pin is connected. Note that other than slicing off SOG, the output from this pin receives no other additional processing on the AD9888. VSYNC separation is performed via the sync separator.

The absolute accuracy of this reference is ±4%, and the temperature coefficient is ±50 ppm, which is adequate for most

AD9888 applications. If higher accuracy is required, an external reference can be employed instead.

These bypasses for the internal midscale voltage references should each be connected to ground through 0.1 μF capacitors. The exact voltage varies with the gain setting of the blue channel.

External Filter Connection. For proper operation, the internal PLL that generates the pixel clock requires an external filter. Connect the filter shown in Figure 9 to this pin. For optimal performance, minimize noise and parasitics on this node.

Main Power Supply. These pins supply power to the main elements of the circuit. This supply should be as quiet and filtered as possible.

A large number of output pins (up to 52) switching at high speed (up to 110 MHz) generates significant power supply transients (noise). These supply pins are identified separately from the V

pins; therefore, special care must be taken to

minimize output noise transferred into the sensitive analog circuitry. If the AD9888 is interfacing with lower voltage logic,

can be connected to a lower supply voltage (as low as 2.5 V) for compatibility.

The most sensitive portion of the AD9888 is the clock generation circuitry. These pins provide power to the PLL generated pixel clock and help the user design for optimal performance. The designer should provide noise-free power to these pins.

Rev. C | Page 10 of 36

Data Sheet AD9888

Mnemonic Description

GND Ground.

Serial Port

(2-Wire) SDA Serial Port Data I/O. SCL Serial Port Data Clock. A0 Serial Port Address Input 1

The ground return for all circuitry on the chip. It is recommended that the AD9888 be assembled on a single solid ground plane, with careful attention paid to ground current paths.

For a full description of the 2-wire serial register and how it works, refer to the 2-Wire Serial Control Port section.

Rev. C | Page 11 of 36

+ 25 hidden pages

ANALOG DEVICES AD9888 Service Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

EXPLANATION OF TEST LEVELS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS