Analog Devices AD9882A Datasheet

Dual Interface for

FEATURES

Analog interface

140 MSPS maximum conversion rate Programmable analog bandwidth

0.5 V to 1.0 V analog input range 500 ps p-p PLL clock jitter at 140 MSPS

3.3 V power supply Full sync processing Midscale clamping 4:2:2 output format mode

Digital interface

DVI 1.0 compatible interface 112 MHz operation High skew tolerance of 1 full input clock Sync detect for hot plugging Supports high bandwidth digital content protection

APPLICATIONS

RGB graphics processing LCD monitors and projectors Plasma display panels Scan converter Microdisplays Digital TV

GENERAL DESCRIPTION

The AD9882A offers designers the flexibility of an analog interface and a digital visual interface (DVI) receiver integrated on a single chip. Also included is support for high bandwidth digital content protection (HDCP).

Analog Interface

The AD9882A is a complete, 8-bit, 140 MSPS monolithic analog interface optimized for capturing RGB graphics signals from personal computers and workstations. Its 140 MSPS encode rate capability and full power analog bandwidth of 300 MHz sup-ports resolutions up to SXGA (1280 × 1024 at 75 Hz).

The analog interface includes a 140 MHz triple ADC with internal 1.25 V reference, a phase-locked loop (PLL), programmable gain, offset, and clamp control. The user provides only a

3.3 V power supply, analog input, and Hsync. Three-state CMOS outputs can be powered from 2.2 V to 3.3 V.

The AD9882A’s on-chip PLL generates a pixel clock from Hsync. Pixel clock output frequencies range from 12 MHz to 140 MHz. PLL clock jitter is typically 500 ps p-p at 140 MSPS.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Flat Panel Displays

AD9882A

FUNCTIONAL BLOCK DIAGRAM

ANALOG INTERFACE

AIN

X0+ X0– X1+ X1– X2+ X2–

CLAMP

SYNC

PROCESSING AND

CLOCK

GENERATION

SERIAL REGISTER AND

POWER MANAGEMENT

DIGITAL INTERFACE

DVI

RECEIVER

HDCP

8 8

A/D

DATACK

SOGOUT

DATACK

SOGIN

HSYNC

FILT

VSYNC

SCL

SDA

R R R R R R

XC+

XC–

TERM

DDCSCL DDCSDA

MCL

MDA

Figure 1.

The AD9882A also offers full sync processing for composite sync and sync-on-green (SOG) applications.

Digital Interface

The AD9882A contains a DVI 1.0 compatible receiver and supports display resolutions up to SXGA (1280 × 1024 at 60 Hz). The receiver features an intrapair skew tolerance of up to one full clock cycle.

With the inclusion of HDCP, displays can now receive encrypted video content. The AD9882A allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during transmission, as specified by the HDCP v1.0 protocol. It also has high tolerance of noncompliant HDCP sources.

Fabricated in an advanced CMOS process, the AD9882A is provided in a space-saving, 100-lead LQFP surface-mount plastic package and is specified over the 0°C to 70°C temperature range. It is available in a Pb-free package.

www.analog.com

REF

HSOUT VSOUT

R G B

HSYNC VSYNC

AD9882A

OUT

MUXES

OUT

REFBYPASS

OUT

DATACK HSOUT

CSOUT SOGOUT

05123-001

AD9882A

TABLE OF CONTENTS

Specifications............................................................................................3

Absolute Maximum Ratings .................................................................. 6

Explanation of Test Levels.................................................................. 6

ESD Caution ........................................................................................6

Pin Configuration and Function Descriptions....................................7

Pin Descriptions of Shared Pins between Analog and Digital Interfaces

Serial Port (2-Wire) ............................................................................8

Data Outputs........................................................................................8

Pin Function Detail: Analog Interface ............................................. 9

Power Supply .....................................................................................10

Theory of Operation: Interface Detection .........................................12

Active Interface Detection and Selection.......................................12

Power Management ..........................................................................12

Theory of Operation and Design Guide: Analog Interface............. 13

General Description..........................................................................13

Input Signal Handling ......................................................................13

Hsync and Vsync Inputs .................................................................. 13

Serial Control Port............................................................................ 13

Output Signal Handling ...................................................................13

Clamping............................................................................................13

Gain and Offset Control...................................................................14

Sync-on-Green (SOG)......................................................................15

Clock Generation..............................................................................15

Timing: Analog Interface .....................................................................17

Timing Diagrams ..............................................................................18

Theory of Operation: Digital Interface...............................................19

Digital Interface Pin Descriptions .................................................. 19

Capturing the Encoded Data...........................................................20

Data Frames....................................................................................... 20

..............................................................................................8

Special Characters.............................................................................20

Channel Resynchronization.............................................................20

Data Decoder.....................................................................................20

HDCP..................................................................................................20

General Timing Diagrams: Digital Interface.................................22

Timing Mode Diagrams: Digital Interface ....................................22

2-Wire Serial Register Map ..................................................................23

2-Wire Serial Control Register Detail.................................................26

Chip Identification ............................................................................26

PLL Divider Control.........................................................................26

Clamp Timing....................................................................................27

Hsync Output Pulse Width..............................................................27

Input Gain ..........................................................................................27

Input Offset........................................................................................27

2-Wire Serial Control Port ...............................................................32

Sync Processing Engine ........................................................................35

Sync Slicer...........................................................................................35

Sync Separator ...................................................................................35

PCB Layout Recommendations...........................................................36

Analog Interface Inputs....................................................................36

Digital Interface Inputs.....................................................................36

Power Supply Bypassing ...................................................................36

PLL ......................................................................................................37

Outputs: Data and Clocks ................................................................37

Digital Inputs .....................................................................................37

Volt a ge R ef e re n c e ..............................................................................37

Outline Dimensions ..............................................................................38

Ordering Guide..................................................................................38

REVISION HISTORY

10/04—Revision 0: Initial Version

Rev. 0 | Page 2 of 40

AD9882A

SPECIFICATIONS

VD = 3.3 V, VDD = 3.3 V, ADC clock = maximum conversion rate, unless otherwise noted.

Table 1. Analog Interface Electrical Characteristics

AD9882AKSTZ-100 AD9882AKSTZ-140 Parameter Temp Test Level Min Typ Max Min Typ Max Unit

RESOLUTION 8 8 Bits DC ACCURACY

Differential Nonlinearity 25°C I ±0.5 +1.25/–1.0 ±0.5 +1.35/–1.0 LSB

Full VI +1.35/–1.0 +1.45/–1.0 LSB

Integral Nonlinearity 25°C I ±0.5 ±1.85 ±0.5 ±2.0 LSB

Full VI ±2.0 ±2.3 LSB

No Missing Codes Full VI Guaranteed Guaranteed

ANALOG INPUT

Input Voltage Range

Minimum Full VI 0.5 0.5 V p-p

Maximum Full VI 1.0 1.0 V p-p Gain Tempco 25°C V 100 100 ppm/°C Input Bias Current Full IV 1 1 µA Input Full-Scale Matching Full VI 1.5 8.0 1.5 8.0 % FS Offset Adjustment Range Full VI 45 49 56 45 49 56 % FS

REFERENCE OUTPUT

Output Voltage Full VI 1.25 1.25 V Temperature Coefficient Full V ±50 ±50 ppm/°C

SWITCHING PERFORMANCE

Maximum Conversion Rate Full VI 100 140 MSPS Minimum Conversion Rate Full IV 10 10 MSPS Clock to Data Skew, t Serial Port Timing

BUFF

STAH

DHO

DAL

DAH

DSU

STASU

STOSU

Hsync Input Frequency Full IV 15 110 15 110 kHz Maximum PLL Clock Rate Full VI 100 140 MHz Minimum PLL Clock Rate Full IV 12 12 MHz PLL Jitter 25°C IV 500 700

Full IV 10002 10002 ps p-p

Sampling Phase Tempco Full IV 15 15 ps/°C

DIGITAL INPUTS

Input Voltage, High (VIH) Full VI 2.6 2.6 V Input Voltage, Low (VIL) Full VI 0.8 0.8 V Input Current, High (IIH) Full IV –1.0 –1.0 µA Input Current, Low (IIL) Full IV 1.0 1.0 µA Input Capacitance 25°C V 3 3 pF

DIGITAL OUTPUTS1

Output Voltage, High (VOH) Full IV VDD – 0.1 VDD – 0.1 V Output Voltage, Low (VOL) Full IV 0.4 0.4 V Duty Cycle, DATACK Full IV 45 50 55 45 50 55 %

SKEW

Full IV –0.5 +2.0 –0.5 +2.0 ns

Full VI 4.7 4.7 µs Full VI 4.0 4.0 µs Full VI 250 250 ns Full VI 4.7 4.7 µs Full VI 4.0 4.0 µs Full VI 250 250 ns Full VI 4.7 4.7 µs Full VI 4.0 4.0 µs

500 7002 ps p-p

Rev. 0 | Page 3 of 40

AD9882A

AD9882AKSTZ-100 AD9882AKSTZ-140 Parameter Temp Test Level Min Typ Max Min Typ Max Unit

Output Coding Binary Binary

POWER SUPPLY1

VD Supply Voltage Full IV 3.15 3.3 3.45 3.15 3.3 3.45 V VDD Supply Voltage Full IV 2.2 3.3 3.45 2.2 3.3 3.45 V PVD Supply Voltage Full IV 3.15 3.3 3.45 3.15 3.3 3.45 V ID Supply Current (VD) 25°C V 162 181 mA IDD Supply Current (VDD) IPVD Supply Current (PVD) 25°C V 19 21 mA Total Supply Current Full VI 228 237 265 274 mA Power-Down Supply Current Full VI 30 35 30 35 mA

DYNAMIC PERFORMANCE

Analog Bandwidth, Full Power 25°C V 300 300 MHz Signal-to-Noise Ratio (SNR) 25°C V 44 43 dB

fIN = 2.3 MHz

Crosstalk Full V 55 55 dBc

THERMAL CHARACTERISTICS

θJA Junction-to-Ambient

Drive strength = 11.

VCO range = 10, Charge pump current = 110, PLL divider = 1693.

DATACK Load = 15 pF, Data load = 5 pF.

Simulated typical performance with package mounted to a 4-layer board.

25°C V 47 63 mA

V 43 43 °C/W

VD = 3.3 V, VDD = 3.3 V, clock = maximum, unless otherwise noted.

Table 2. Digital Interface Electrical Characteristics

AD9882AKSTZ Parameter Conditions Temp Test Level Min Typ Max Unit

RESOLUTION 8 Bits DC DIGITAL I/O Specifications

High Level Input Voltage (VIH) Full VI 2.6 V Low Level Input Voltage (VIL) Full VI 0.8 V High Level Output Voltage (VOH) Full IV 2.4 V Low Level Output Voltage (VOL) Full IV 0.4 V Output Leakage Current (IOL) High impedance Full IV –10 +10 µA

DC SPECIFICATIONS

Output High Drive Output drive = high Full V 11 mA

)(V

OHD

= VOH) Output drive = medium Full V 8 mA

OUT

Output drive = low Full V 5 mA

Output Low Drive Output drive = high Full V –7 mA

)(V

OLD

= VOL) Output drive = medium Full V –6 mA

OUT

Output drive = low Full V –5 mA

DATACK High Drive Output drive = high Full V 28 mA

)(V

OHC

= VOH) Output drive = medium Full V 14 mA

OUT

Output drive = low Full V 7 mA

DATACK Low Drive Output drive = high Full V –15 mA

)(V

= VOL) Output drive = medium Full V –9 mA

OLC

OUT

Output drive = low Full V –7 mA

Differential Input Voltage

Single-Ended Amplitude Full IV 75 800 mV

Rev. 0 | Page 4 of 40

AD9882A

AD9882AKSTZ Parameter Conditions Temp Test Level Min Typ Max Unit

POWER SUPPLY

VD Supply Voltage Full IV 3.15 3.3 3.45 V VDD Supply Voltage Full IV 2.2 3.3 3.45 V PVD Supply Voltage Full IV 3.15 3.3 3.45 V ID Supply Current (Typical Pattern) IDD Supply Current (Typical Pattern) IPVD Supply Current (Typical Pattern)

Total Supply Current with HDCP

(Typical Pattern)

1, 2

ID Supply Current (Worst-Case Pattern)3 25°C V 247 mA

IDD Supply Current

(Worst-Case Pattern)

IPVD Supply Current

(Worst-Case Pattern)

Total Supply Current with HDCP

(Worst-Case Pattern)

2, 3

Power-Down Supply Current (IPD) Full VI 30 35 mA

AC SPECIFICATIONS

Intrapair (+ to –) Differential Input

DPS

)

Skew (T

Channel-to-Channel Differential

Input Skew (T

CCS

)

Low-to-High Transition Time

for Data (D

LHT

)

Output drive = low, CL = 5 pF Full IV 3.2 ns

Low-to-High Transition Time

for DATACK (D

LHT

)

Output drive = low, CL = 5 pF Full IV 2.1 ns

High-to-Low Transition Time

for Data (D

HLT

)

Output drive = low, CL = 5 pF Full IV 1.7 ns

High-to-Low Transition Time

for DATACK (D

HLT

)

Output drive = low, CL = 5 pF Full IV 1.4 ns

Clock -to- Data Skew,4 t

SKEW

Duty Cycle, DATACK4 Full IV 40 46 50 % DATACK Frequency (F

) Full VI 25 112 MHz

CIP

The typical pattern contains a gray scale area. Output drive = high.

DATACK load = 10 pF, data load = 10 pF.

The worst-case pattern contains a black and white checkerboard pattern. Output drive = high.

Drive strength = 11.

1, 2

25°C V 237 mA 25°C V 25 mA

25°C V 57 mA Full IV 340 367 mA

25°C V 61 mA

25°C V 57 mA

Full IV 385 420 mA

Full IV 360 ps

Full IV 1 Clock Period

Output drive = high, C

= 10 pF Full IV 2.2 ns

Output drive = medium, C

= 7 pF Full IV 2.5 ns

Output drive = high, C

= 10 pF Full IV 1.0 ns

Output drive = medium, C

= 7 pF Full IV 1.6 ns

Output drive = high, C

= 10 pF Full IV 2.2 ns

Output drive = medium, C

= 7 pF

Output drive = high, C

= 10 pF

Full IV 1.9 ns

Full IV 1.0 ns

Output drive = medium, C

= 7 pF Full IV 1.0 ns

Full IV –0.5 +2.0 ns

Rev. 0 | Page 5 of 40

AD9882A

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Analog Inputs VD to 0.0 V V

VD to 0.0 V

REF

Digital Inputs 5 V to 0.0 V Digital Output Current 20 mA Operating Temperature –25°C to +85°C Storage Temperature –65°C to +150°C Maximum Junction Temperature 150°C Maximum Case Temperature 150°C

3.6 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.

EXPLANATION OF TEST LEVELS

I. 100% production tested.

II. 100% production tested at 25°C and sample tested at

specified temperatures.

III. Sample tested only. IV. Parameter is guaranteed by design and characterization

testing.

V. Parameter is a typical value only.

VI. 100% production tested at 25°C; guaranteed by design and

characterization testing.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 6 of 40

AD9882A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VDDRED<0>

RED<1>

RED<2>

RED<3>

RED<4>

RED<5>

RED<6>

RED<7>

GND

VDDSOGOUT

HSOUT

VSOUTDEDATACK

GND

VDDMDA

MCL

VSYNC

HSYNC

SDA

SCL

9998979695949392919089888786858483828180797877

100

GND

GREEN<7> GREEN<6> GREEN<5> GREEN<4> GREEN<3> GREEN<2> GREEN<1> GREEN<0>

GND BLUE<7> BLUE<6> BLUE<5> BLUE<4> BLUE<3> BLUE<2> BLUE<1> BLUE<0>

GND

CTL 0 CTL 1 CTL 2 CTL 3

PIN 1

INDICATOR

3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

26272829303132333435363738394041424344454647484950

TERM

VDV

X0–

X0+

GND

X1–

AD9882A

TOP VIEW

(Not to Scale)

X2–

X1+

GND

DPVD

GND

XC–

XC+

X2+

GND

Figure 2. 100-Lead LQFP Pin Configuration

Table 4. Pin Function Descriptions

Pin Type Mnemonic Function Value

Analog Video Inputs R G B

AIN

Analog Input for Converter R 0.0 V to 1.0 V 70 Analog Analog Input for Converter G 0.0 V to 1.0 V 65 Analog

Analog Input for Converter B 0.0 V to 1.0 V 59 Analog External Sync/Clock HSYNC Horizontal Sync Input 3.3 V CMOS 79 Analog VSYNC Vertical Sync Input 3.3 V CMOS 80 Analog SOGIN Input for Sync-on-Green 0.0 V to 1.0 V 64 Analog Sync Outputs HSOUT

HSYNC Output Clock (Phase-Aligned with

DATACK) VSOUT VSYNC Output Clock 3.3 V CMOS 87 Both SOGOUT Sync-on-Green Slicer Output 3.3 V CMOS 89 Analog References REFBYPASS Internal Reference Bypass 1.25 V 73 Analog MIDBYPASS Internal Midscale Voltage Bypass 74 Analog PLL Filter FILT

Connection for External Filter Components for

Internal PLL Power Supply V V PV

Analog Power Supply 3.15 V to 3.45 V Both

Output Power Supply 2.2 V to 3.6 V Both

PLL Power Supply 3.15 V to 3.45 V Both GND Ground 0 V Both Serial Port Control SDA Serial Port Data I/O 3.3 V CMOS 78 Both SCL Serial Port Data Clock (100 kHz Maximum) 3.3 V CMOS 77 Both A0 Serial Port Address Input 3.3 V CMOS 76 Both

GND

MIDBYPASS

REFBYPASS

GND

AIN

GND

GND G

AIN

SOGIN

GND

AIN

GND

DDCSDA

DDCSCL

GND

FILT

GND

05123-002

Pin Number Interface

3.3 V CMOS 88 Both

48 Analog

Rev. 0 | Page 7 of 40

AD9882A

Pin Type Mnemonic Function Value

Data Outputs RED [7:0] Outputs of Converter Red, Bit 7 is the MSB 3.3 V CMOS 92–99 Both GREEN [7:0] Outputs of Converter Green, Bit 7 is the MSB 3.3 V CMOS 2–9 Both BLUE [7:0] Outputs of Converter Bue, Bit 7 is the MSB 3.3 V CMOS 12–19 Both Data Clock Output DATACK

Data Output Clock for the Analog and Digital

3.3 V CMOS 85 Both

Interface

Digital Video Data Inputs

R R R R Digital Video Clock

Inputs

X0+

X0–

X1+

X1–

X2+

X2–

XC+

XC–

Digital Input Channel 0 True 33 Digital Digital Input Channel 0 Complement 32 Digital Digital Input Channel 1 True 36 Digital Digital Input Channel 1 Complement 35 Digital Digital Input Channel 2 True 39 Digital Digital Input Channel 2 Complement 38 Digital Digital Data Clock True 41 Digital

Digital Data Clock Complement 42 Digital Data Enable DE Data Enable 3.3 V CMOS 86 Digital Control Bits CTL [0:3] Decoded Control Bits 3.3 V CMOS 22–25 Digital RTERM R

TERM

Sets Internal Termination Resistance 28 Digital HDCP DDCSCL HDCP Slave Serial Port Data Clock 3.3 V CMOS 53 Digital DDCSDA HDCP Slave Serial Port Data I/O 3.3 V CMOS 54 Digital MCL HDCP Master Serial Port Data Clock 3.3 V CMOS 81 Digital MDA HDCP Master Serial Port Data I/O 3.3 V CMOS 82 Digital

Number Interface

PIN DESCRIPTIONS OF SHARED PINS BETWEEN ANALOG AND DIGITAL INTERFACES

HSOUT—Horizontal Sync Output

A reconstructed and phase-aligned version of the video Hsync. The polarity of this output can be controlled via a serial bus bit. In analog interface mode, the placement and duration are variable. In digital interface mode, the placement and duration are set by the graphics transmitter.

VSOUT—Vertical Sync Output

The separated Vsync from a composite signal or a direct passthrough of the Vsync input. The polarity of this output can be controlled via a serial bus bit. The placement and duration in all modes is set by the graphics transmitter.

SERIAL PORT (2-WIRE)

SDA—Serial Port Data I/O

SCL—Serial Port Data Clock

A0—Serial Port Address Input

For a full description of the 2-wire serial register, refer to the 2-Wire Serial Control Register Detail section.

DATA OUTPUTS

RED—Data Output, Red Channel

GREEN—Data Output, Green Channel

BLUE—Data Output, Blue Channel

The main data outputs. Bit 7 is the MSB. These outputs are shared between the two interfaces and behave in accordance with the active interface. Refer to the Analog Interface and Digital Interface sections.

DATACK—Dat a Output Clo c k

Just like the data outputs, the data clock output is shared between the two interfaces. It behaves differently depending on which interface is active. Refer to the DATACK—Data Output Clock section to determine how this pin behaves. .

Rev. 0 | Page 8 of 40

AD9882A

Table 5. Analog Interface Pin List

Pin Type Mnemonic Function Value

Analog Video Inputs R G B

AIN

Analog input for Converter R 0.0 V to 1.0 V 70 Analog input for Converter G 0.0 V to 1.0 V 65

Analog input for Converter B 0.0 V to 1.0 V 59 External Sync/Clock HSYNC Horizontal SYNC input 3.3 V CMOS 79 VSYNC Vertical SYNC input 3.3 V CMOS 80 SOGIN Sync-on-green input 0.0 V to 1.0 V 64 Sync Outputs HSOUT Hsync output (phase-aligned with DATACK) 3.3 V CMOS 88 VSOUT Vsync output 3.3 V CMOS 87 SOGOUT Composite SYNC 3.3 V CMOS 89 Voltage Reference Clamp Voltages REFBYPASS Internal reference bypass 1.25 V 73 MIDBYPASS Internal midscale voltage bypass 74 PLL Filter FILT

Connection for external filter components for

internal PLL Power Supply V PV V

Main power supply 3.15 V to 3.45 V

PLL power supply (nominally 3.3 V) 3.15 V to 3.45 V

Output power supply 2.2 V to 3.6 V GND Ground 0 V

Number

PIN FUNCTION DETAIL: ANALOG INTERFACE

Inputs

—Analog Input for Red Channel

AIN

—Analog Input for Green Channel

AIN

—Analog Input for Blue Channel

AIN

High impedance inputs that accept the red, green, and blue channel graphics signals, respectively. For RGB, the three channels are identical and can be used for any colors, but colors are assigned for convenient reference.

For proper 4:2:2 formatting in a YPbPr application, the Y must be connected to the G

input, and the Pr must be connected to the R

AIN

They accommodate input signals ranging from 0.5 V to 1.0 V full scale. Signals should be ac-coupled to these pins to support clamp operation.

Hsync—Horizontal Sync Input

This input receives a logic signal that establishes the horizontal timing reference and provides the frequency reference for pixel clock generation. The logic sense of this pin is controlled by Serial Register Bit 0x10, Bit 6 (Hsync polarity). Only the leading edge of Hsync is used by the PLL; the trailing edge is used for clamp timing. When Hsync polarity = 0, the falling edge of Hsync is used. When Hsync polarity = 1, the rising edge is active.

input, the Pb must be connected to the

AIN

input.

AIN

The input includes a Schmitt trigger for noise immunity, with a nominal input threshold of 1.5 V.

Electrostatic discharge (ESD) protection diodes conduct heavily if this pin is driven more than 0.5 V above the maximum tolerance voltage (3.3 V) or more than 0.5 V below ground.

VSYNC—Vertical Sync Input

This is the input for vertical sync.

SOGIN—Sync-on-Green Input

This input is provided to assist with processing signals with embedded sync, typically on the green channel. The pin is connected to a high speed comparator with an internally generated threshold, which is set by the value of Register 0x0F, Bits 7 to 3.

When connected to an ac-coupled graphics signal with embedded sync, it produces a noninverting digital output on SOGOUT.

When not used, this input should be left unconnected. For more details on this function and how it should be configured, refer to the Sync-on-Green (SOG) section.

SOGOUT—Sync-on-Green Slicer Output

This pin can be programmed to produce either the output from the sync-on-green slicer comparator or an unprocessed but delayed version of the Hsync input. See Figure 20, the sync processing block diagram, to view how this pin is connected. Note that the output from this pin is the composite sync without additional processing from the AD9882A.

Rev. 0 | Page 9 of 40

AD9882A

FILT—External Filter Connection

RED—Data Output, Red Channel

For proper operation, the pixel clock generator PLL requires an external filter. Connect the filter as shown in Figure 8 to this pin. For optimal performance, minimize noise and parasitics on this node.

REFBYPASS—Internal Reference Bypass

Bypass for the internal 1.25 V band gap reference. It should be connected to ground through a 0.1 µF capacitor.

The absolute accuracy of this reference is ±4%, and the temperature coefficient is ±50 ppm, which is adequate for most AD9882A applications. If higher accuracy is required, an external reference can be employed instead.

MIDBYPASS—Midscale Voltage Reference Bypass

Bypass for the internal midscale voltage reference. It should be connected to ground through a 0.1 µF capacitor. The exact voltage varies with the gain setting of the red channel.

HSOUT—Horizontal Sync Output

A reconstructed and phase-aligned version of the Hsync input. The duration of Hsync can be programmed only on the analog interface, not the digital.

DATACK—Dat a Output Clo c k

The data clock output signal is used to clock the output data and HSOUT into external logic. It is produced by the internal clock generator and is synchronous with the internal pixel sampling clock.

When the sampling time is changed by adjusting the phase register, the output timing is shifted as well. The data bits, DATACK, and HSOUT outputs are all moved, so the timing relationship among the signals is maintained.

VSOUT—Vertical Sync Output

The separated Vsync from a composite signal or a direct passthrough of the Vsync input. The polarity of this output can be controlled via Register 0x10, Bit 2. The placement and duration in all modes is set by the graphics transmitter.

GREEN—Data Output, Green Channel

BLUE—Data Output, Blue Channel

These are the main data outputs. Bit 7 is the MSB.

The delay from pixel sampling time to output is fixed. When the sampling time is changed by adjusting the phase register, the output timing is shifted as well. The DATACK and HSOUT outputs are also moved, so the timing relationship among the signals is maintained. See the Timing Diagrams section for more information.

POWER SUPPLY

VD—Main Power Supply

These pins supply power to the main elements of the circuit. They should be as quiet as possible.

—Digital Output Power Supply

A large number of output pins (up to 25) switching at high speed (up to 140 MHz) generates a lot of power supply transi-

can

ents. These supply pins are identified separately from the V pins, so special care must be taken to minimize output noise transferred into the sensitive analog circuitry.

If the AD9882A is interfacing with lower voltage logic, V be connected to a lower supply voltage (as low as 2.2 V) for compatibility.

—Clock Generator Power Supply

The most sensitive portion of the AD9882A is the clock generation circuitry. These pins provide power to the clock PLL and help the user design for optimal performance. The designer should provide noise-free power to these pins.

GND—Ground

The ground return for all circuitry on-chip. It is recommended that the AD9882A be assembled on a single solid ground plane, with careful attention to ground current paths.

Rev. 0 | Page 10 of 40

AD9882A

Table 6. Interface Selection Controls

AIO (0xF Bit 2)

Table 7. Power-Down Modes, 4:2:2 and 4:4:4 Format Descriptions

Mode

Soft Power-Down (Seek Mode)

Digital Interface On 1 0 1 0 X X

Analog Interface On 4:4:4 Format

Analog Interface On 4:2:2 Format

Serial Bus Arbitrated Interface

Override to Analog Interface

Override to Digital Interface

Absolute PowerDown

Power-down is controlled via Bit 1 in Serial Bus Register 0x14.

Analog interface detect is determined by OR’ing Bits 7, 6, and 5 in Serial Bus Register 0x15.

Digital interface detect is determined by Bit 4 in Serial Bus Register 0x15.

Analog Interface Detect

Digital Interface Detect

AIS (0x0F, Bit 1)

Active Interface

Description

0 Analog Force the analog interface active. 1 X X 1 Digital Force the digital interface active.

0 X None

Neither interface

Both interfaces are powered down.

was detected.

0 1 X Digital

The digital interface was detected. Power down the analog interface.

1 0 X Analog

The analog interface was detected. Power down the digital interface.

1 1 0 Analog

Both interfaces were detected. The analog interface gets priority.

1 Digital

Both interfaces were detected. The digital interface gets priority.

Analog PowerDown

Interface

Detect

1 0 0 0 X X

Digital Interface

Detect

Active Interface Override

Active Interface Select

4:2:2 Formatting

Data Sheet Signals Powered On

Serial bus, digital interface clock detect, analog interface clock detect, SOG

Serial bus; digital interface and analog interface activity detect; SOG, band gap reference; red, green, and blue outputs

1 1 0 0 X 0

Serial bus; analog interface and digital interface clock detect; SOG, band gap reference; red, green, and blue outputs

1 1 0 0 X 1

Serial bus; analog interface and digital interface clock detect; SOG, band gap reference; red and green outputs only

1 1 1 1 0 0

Same as the analog interface in 4:4:4 mode

1 1 1 1 0 1

Same as the analog interface in 4:2:2 mode

1 1 1 1 1 X Same as digital interface mode

1 1 X 1 0 0

Same as the analog interface 4:4:4 mode

1 1 X 1 0 1

Same as the analog interface 4:2:2 mode

1 X 1 1 1 X Same as digital interface mode

0 X X X X X Serial bus

Rev. 0 | Page 11 of 40

AD9882A

THEORY OF OPERATION: INTERFACE DETECTION

ACTIVE INTERFACE DETECTION AND SELECTION

The AD9882A includes circuitry to detect whether an interface is active or not (see Table 6).

For detecting the analog interface, the circuitry monitors the presence of Hsync, Vsync, and sync-on-green. The result of the detection circuitry can be read from the 2-wire serial interface bus at Address 0x15, Bits 7, 5, and 6, respectively. If one of these sync signals disappears, the maximum time it takes for the circuitry to detect it is 100 ms.

For detecting the digital interface, there are two stages of detection. The first stage searches for the presence of the digital interface clock. The circuitry for detecting the digital interface clock is active even when the digital interface is powered down. The result of this detection stage can be read from the 2-wire serial interface bus at Address 0x15, Bit 4. If the clock disappears, the maximum time it takes for the circuitry to detect it is 100 ms. Once a digital interface clock is detected, the digital interface is powered up and the second stage of detection begins. During the second stage, the circuitry searches for 32 consecutive DEs. Once 32 DEs are found, the detection process is complete.

There is an override for the automatic interface selection. It is the AIO (Active Interface Override) bit, Register 0x0F, Bit 2. When the AIO bit is set to Logic 0, the automatic circuitry is used. When the AIO bit is set to Logic 1, the AIS (Active Interface Select) bit (Register 0x0F, Bit 1) is used to determine the active interface rather than the automatic circuitry.

POWER MANAGEMENT

The AD9882A is a dual interface device with shared outputs. Only one interface can be used at a time. For this reason, the chip automatically powers down the unused interface. When the analog interface is being used, most of the digital interface circuitry is powered down, and vice versa. This helps to minimize the AD9882A total power dissipation. In addition, if neither interface has activity on it, the chip powers down both interfaces. The AD9882A uses the activity detect circuits, the active interface bits in Serial Register 0x15, the active interface override bits in Register 0x0F, Bits 2 and 1, and the power-down bit in Register 0x14, Bit 1, to determine the correct power state. In a given power mode, not all circuitry in the inactive interface is powered down completely.

When the digital interface is active, the band gap reference Hsync, Vsync, and SOG detect circuitry remain powered-up. When the analog interface is active, the digital interface clock detect circuit is not powered-down. Table 7 summarizes how the AD9882A determines which power mode to be in and which circuitry is powered on/off in each of these modes. The power-down command has priority, then the active interface override, and then the automatic circuitry.

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