ANALOG DEVICES AD9880 Service Manual

Analog/HDMI

www.BDTIC.com/ADI

FEATURES

Analog/HDMI dual interface
Supports high bandwidth digital content protection
RGB-to-YCbCr 2-way color conversion
Automated clamping level adjustment

1.8 V/3.3 V power supply
100-lead LQFP Pb-free package
RGB and YCbCr output formats
Analog interface

8-bit triple ADC
100 MSPS maximum conversion rate
Macrovision® detection
2:1 input mux
Full sync processing
Sync detect for hot plugging
Midscale clamping

Digital video interface

HDMI v 1.1, DVI v 1.0
150 MH
Supports high bandwidth digital content protection
(HDCP 1.1)

Digital audio interface

HDMI 1.1-compatible audio interface
S/PDIF (IEC90658-compatible) digital audio output
Multichannel I2S audio output (up to 8 channels)

APPLICATIONS

Advanced TV
HDTV
Projectors
LCD monitor

GENERAL DESCRIPTION

The AD9880 offers designers the flexibility of an analog interface
and high definition multimedia interface (HDMI) receiver inte­grated on a single chip. Also included is support for high band­width digital content protection (HDCP).

Analog Interface

The AD9880 is a complete 8-bit 150 MSPS monolithic analog inter­face o
graphics signals. Its 150 MSPS encode rate capability and full power
analog bandwidth of 330 MHz supports all HDTV formats (up to
1080 p) and FPD resolutions up to SXGA (1280 × 1024 @ 75 Hz).

The analog interface includes a 150 MHz triple ADC with internal

1.25
gain, offset, and clamp control. The user provides only 1.8 V and

3.3 V power supplies, analog input, and Hsync. Three-state

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

z HDMI receiver

ptimized for capturing component video (YPbPr) and RGB

V reference, a phase-locked loop (PLL), and programmable

Dual Display Interface

AD9880

FUNCTIONAL BLOCK DIAGRAM

COAST

FILT

CKINV

CKEXT

SCL
SDA

RX0+
RX0–
RX1+
RX1–
RX2+

RX2–
RXC+
RXC–

R

TERM

MCL

MDA

IN0
IN1

ANALOG INTERFACE

2:1

CLAMP

MUX

2:1

MUX

2:1

MUX

2:1

MUX

POWER MANAGEMENT

DIGITAL INTERFACE

SYNC

PROCESSING

AND

CLOCK

GENERATION

SERIAL REGISTER

AND

HDMI RECEIVER

HDCP

A/D

REFOUT

REFIN

Figure 1.

2

4

R/G/B 8X3
or YCbCr

2

DATACK
HSOUT
VSOUT
SOGOUT

REF

R/G/B 8X3

OR YCbCr

DATACK
DE

H

SYNC

V

SYNC

MUXES

AD9880

R/G/B OR YPbPr
R/G/B OR YPbPr

HSYNC 0
HSYNC 1

HSYNC 0
HSYNC 1

SOGIN 0
SOGIN 1

DDCSCL

DDCSDA

CMOS outputs can be powered from 1.8 V to 3.3 V. The
AD9880’s on-chip PLL generates a pixel clock from Hsync. Pixel
clock output frequencies range from 12 MHz to 150 MHz. PLL
clock jitter is typically less than 700 ps p-p at 150 MHz. The
AD9880 also offers full sync processing for composite sync and
sync-on-green (SOG) applications.

Digital Interface

The AD9880 contains a HDMI 1.1-compatible receiver and sup­p

orts all HDTV formats (up to 1080 p and 720 p) and display
resolutions up to SXGA (1280 × 1024 @75 Hz). The receiver
features an intrapair skew tolerance of up to one full clock cycle.
With the inclusion of HDCP, displays can now receive encrypted
video content. The AD9880 allows for authentication of a video
receiver, decryption of encoded data at the receiver, and renewa­bility of the authentication during transmission, as specified by the
HDCP v 1.1 protocol.

Fabricated in an advanced CMOS process, the AD9880 is provided

ace-saving, 100-lead LQFP surface-mount Pb-free plastic

in a sp
package and is specified over the 0°C to 70°C temperature range.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

R/G/B 8X3
YCbCr (4:2:2

OR 4:4:4)
2

RGB YCbCr MATRIX

SPDIF OUT
8-CHANNEL

I

SOUT

2

SCLK
MCLK
LRCLK

05087-001

DATACK

HSOUT

VSOUT
SOGOUT

DE

AD9880

www.BDTIC.com/ADI

TABLE OF CONTENTS

Specifications..................................................................................... 3

Analog Interface Electrical Characteristics............................... 3

Digital Interface Electrical Characteristics ............................... 4

Absolute Maximum Ratings............................................................ 6

Explanation of Test Levels........................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Design Guide................................................................................... 12

General Description................................................................... 12

Digital Inputs ..............................................................................12

Analog Input Signal Handling.................................................. 12

Hsync and Vsync Inputs............................................................ 12

Serial Control Port ..................................................................... 12

Output Signal Handling............................................................. 12

Clamping ..................................................................................... 12

Timing Diagrams ....................................................................... 21

2-Wire Serial Register Map ........................................................... 23

2-Wire Serial Control Register Detail.......................................... 37

Chip Identification..................................................................... 37

PLL Divider Control.................................................................. 37

Clock Generator Control .......................................................... 37

Input Gain ................................................................................... 38

Input Offset ................................................................................. 38

Sync .............................................................................................. 39

Coast and Clamp Controls........................................................ 39

Status of Detected Signals ......................................................... 40

Polarity Status ............................................................................. 41

BT656 Generation...................................................................... 46

Macrovision................................................................................. 48

Color Space Conversion............................................................ 49

Timing.......................................................................................... 16

HDMI Receiver........................................................................... 20

DE Generator ..............................................................................20

4:4:4 to 4:2:2 Filter...................................................................... 20

Audio PLL Setup......................................................................... 21

Audio Board Level Muting........................................................ 21

REVISION HISTORY

8/05—Revision 0: Initial Version

2-Wire Serial Control Port........................................................ 56

PCB Layout Recommendations.................................................... 58

Color Space Converter (CSC) Common Settings...................... 60

Outline Dimensions ....................................................................... 62

Ordering Guide .......................................................................... 62

Rev. 0 | Page 2 of 64

AD9880

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SPECIFICATIONS

ANALOG INTERFACE ELECTRICAL CHARACTERISTICS

V

= 3.3 V, DVDD = PVDD = 1.8 V, ADC clock = maximum.

DD, VD

Table 1.

AD9880KSTZ-100 AD9880KSTZ-150
Parameter Temp Test Level Min Typ Max Min Typ Max Unit

RESOLUTION 8 8 Bits
DC ACCURACY

Differential Nonlinearity 25°C I –0.6

Integral Nonlinearity 25°C I ±1.0 ±2.1 ±1.1 ±2.25 LSB
No Missing Codes Full Guaranteed Guaranteed

ANALOG INPUT

Input Voltage Range

Minimum Full VI 0.5 0.5 V p–p

Maximum Full VI 1.0 1.0 V p–p
Gain Tempco +25°C V 100 220 ppm/°C
Input Bias Current +25°C V 0.2 1 μA
Input Full-Scale Matching

Offset Adjustment Range Full V 50 50 %FS

SWITCHING PERFORMANCE

Maximum Conversion Rate Full VI 100 150 MSPS
Minimum Conversion Rate Full VI 10 10 MSPS
Data to Clock Skew Full IV −0.5 +2.0 −0.5 +2.0 ns

Serial Port Timing

t

BUFF

t

STAH

t

DHO

t

DAL

t

DAH

t

DSU

t

STASU

t

STOSU

HSYNC Input Frequency Full VI 15 110 15 110 KHz
Maximum PLL Clock Rate Full VI 100 150 MHz
Minimum PLL Clock Rate Full IV 12 12 MHz
PLL Jitter +25°C IV 700 700 ps p-p
Sampling Phase Tempco Full IV 15 15 ps/°C

DIGITAL INPUTS: (5V tolerant)

Input Voltage, High (VIH) Full VI 2.6 2.6 V
Input Voltage, Low (VIL) Full VI 0.8 0.8 V
Input Current, High (IIH) Full V -82 -82 μA
Input Current, Low (IIL) Full V 82 82 μA
Input Capacitance 25°C V 3 3 pF

DIGITAL OUTPUTS

Output Voltage, High (VOH) Full VI VDD − 0.1 VDD − 0.1 V
Output Voltage, Low (VOL) Full VI 0.4 0.4 V
Duty Cycle, DATACK Full V 45 50 55 45 50 55 %
Output Coding Binary Binary

POWER SUPPLY

VD Supply Voltage Full IV 3.15 3.3 3.47 3.15 3.3 3.47 V
DVDD Supply Voltage Full IV 1.7 1.8 1.9 1.7 1.8 1.9 V

25C

ull

F

1

Full VI 4.7 4.7 μs
Full VI 4.0 4.0 μs
Full VI 0 0 μs
Full VI 4.7 4.7 μs
Full VI 4.0 4.0 μs
Full VI 250 250 ns
Full VI 4.7 4.7 μs
Full VI 4.0 4.0 μs

VI
VI

1.25

1.50

+1.6/–

1.0

5
7

±0.7

1.25

1.50

+1.8/–

1.0

5
7

LSB

%FS
%FS

Rev. 0 | Page 3 of 64

AD9880

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AD9880KSTZ-100 AD9880KSTZ-150
Parameter Temp Test Level Min Typ Max Min Typ Max Unit

VDD Supply Voltage Full IV 1.7 3.3 3.47 1.7 3.3 3.47 V
PVDD Supply Voltage Full IV 1.7 1.8 1.9 1.7 1.8 1.9 V
ID Supply Current (VD) 25°C VI 260 300 330 mA
I

Supply Current (DVDD) 25°C VI 45 60 85

DVDD

IDD Supply Current (VDD)
IP

Supply Current (P

VDD

Total Power Full VI 1.1 1.4 1.15 1.4 W
Power-Down Dissipation Full VI 130 130 mW

DYNAMIC PERFORMANCE

Analog Bandwidth, Full
Power

Signal–to–Noise Ratio (SNR) 25°C I 46 46 dB

Without Harmonics Full V 45 45 dB

fIN = 40.7 MHz

Crosstalk Full V 60 60 dBc

THERMAL CHARACTERISTICS

θJA-Junction-to-Ambient V 35 35 °C/W

1

Drive strength = high.

2

DATACK load = 15 pF, data load = 5 pF.

3

Specified current and power values with a worst case pattern (on/off).

2

VDD

25°C VI 37 100

) 25°C VI 10 15 20 mA

3

130

3

mA

25°C V 330 330 MHz

DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS

VDD = VD =3.3 V, DVDD = PVDD = 1.8 V, ADC clock = maximum.

Table 2.

AD9880KSTZ-100

AD9880KSTZ-150

Te st

Parameter

Le

vel Conditions Min Typ Max Min Typ Max Unit

RESOLUTION 8 8 Bit
DC DIGITAL I/O Specifications

High-Level Input Voltage, (VIH) VI 2.5 2.5 V
Low-Level Input Voltage, ( VIL) VI 0.8 0.8 V
High-Level Output Voltage, (VOH) VI VDD − 0.1 V
Low-Level Output Voltage, (VOL) VI VDD − 0.1 0.1 0.1 V

DC SPECIFICATIONS

Output High Level IV Output drive = high 36 36 mA

(I

) (V

OHD

= VOH) IV Output drive = low 24 24 mA

OUT

Output Low Level IV Output drive = high 12 12 mA

I

, (V

OLD

= VOL) IV Output drive = low 8 8 mA

OUT

DATACK High Level IV Output drive = high 40 40 mA

V

, (V

OHC

= VOH) IV Output drive = low 20 20 mA

OUT

DATACK Low Level IV Output drive = high 30 30 mA

V

, (V

OLC

Differential Input Voltage, Single Ended

= VOL) IV Output drive = low 15 15 mA

OUT

IV 75 700 75 700 mV

Amplitude

Rev. 0 | Page 4 of 64

AD9880

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AD9880KSTZ-100

AD9880KSTZ-150

Te st

Parameter

Level

Conditions Min Typ Max Min Typ Max Unit

POWER SUPPLY

VD Supply Voltage IV 3.15 3.3 3.47 3.15 3.3 3.47 V
VDD Supply Voltage IV 1.7 3.3 347 1.7 3.3 347 V
DVDD Supply Voltage IV 1.7 1.8 1.9 1.7 1.8 1.9 V
PVDD Supply Voltage IV 1.7 1.8 1.9 1.7 1.8 1.9 V

IVD Supply Current (Typical Pattern)

I

Supply Current (Typical Pattern)

VDD

I

Supply Current (Typical Pattern)

DVDD

I

Supply Current (Typical Pattern)

PVDD

1

V 80 100 80 110 mA

2

V 40 1003 55 175*

1, 4

V 88 110 110 145 mA

1

V 26 35 30 40 mA

Power-Down Supply Current (IPD) VI 130 130 mA

AC SPECIFICATIONS

Intrapair (+ to −) Differential Input Skew

)

(T

DPS

Channel to Channel Differential Input

CCS

)

Skew (T
Low-to-High Transition Time for Data and

Controls (D

LHT

)

IV

Low-to-High Transition Time for
DATACK (D

LHT

)

IV

IV 360 pS

IV 6

IV

Output drive = high;

900 ps

CL = 10 pF

1300 ps

650 ps

1200 ps

IV

Output drive = low;

= 5 pF

C

L

Output drive = high;

= 10 pF

C

L

Output drive = low;
CL = 5 pF

High-to-Low Transition Time for Data and
Controls (D

HLT

)

IV

High-to-Low Transition Time for
DATACK (D

HLT

)

IV

Clock to Data Skew5 (T
Duty Cycle, DATACK
DATACK Frequency (F

1

The typical pattern contains a gray scale area, output drive = high. Worst case pattern is alternating black and white pixels.

2

The typical pattern contains a gray scale area, output drive = high.

3

Specified current and power values with a worst case pattern (on/off).

4

DATACK load = 10 pF, data load = 5 pF.

5

Drive strength = high.

) IV –0.5 2.0 –0.5 2.0 ns

SKEW

5

) VI 20 150 MHz

CIP

IV

Output drive = high;

= 10 pF

C

L

Output drive = low;

= 5 pF

C

L

IV

Output drive = high;

= 10 pF

C

L

Output drive = low;

= 5 pF

C

L

IV 45 50 55 %

850 ps

1250 ps

800 ps

1200 ps

Clock

riod

Pe

Rev. 0 | Page 5 of 64

AD9880

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ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VD 3.6 V
VDD 3.6 V
DVDD 1.98 V
PVDD 1.98 V
Analog Inputs VD to 0.0 V
Digital Inputs 5 V to 0.0 V
Digital Output Current 20 mA
Operating Temperature −25°C to + 85°C
Storage Temperature −65°C to + 150°C
Maximum Junction Temperature 150°C
Maximum Case Temperature 150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

EXPLANATION OF TEST LEVELS

Tes t Le v el

I. 100% production tested.
II. 100% p

specified temperatures.

III. S
IV. P

V. P
VI. 100% p

ample tested only.

arameter is guaranteed by design and

characterization testing.

arameter is a typical value only.

and characterization testing.

roduction tested at 25°C and sample tested at

roduction tested at 25°C; guaranteed by design

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 6 of 64

AD9880

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AIN0

AIN1

VDDRED 0

99

100

RED 1

98

RED 2

97

RED 3

96

RED 4

95

RED 5

94

RED 6

93

RED 7

92

GND

91

VDDDATACLKDEHSOUT

898887

90

SOGOUT

VSOUT

86

85

O/E FIELD

SDA

SCL

84

82

83

PWRDN

81

VDR

80

79

GND

R

787776

D

V

GND
GREEN 7
GREEN 6
GREEN 5
GREEN 4
GREEN 3
GREEN 2
GREEN 1
GREEN 0

V

GND

BLUE 7
BLUE 6
BLUE 5
BLUE 4
BLUE 3
BLUE 2
BLUE 1
BLUE 0

MCLKIN

MCLKOUT

SCLK

LRCLK

I2S3

I2S2

1

2

3
4
5
6

7

8
9

10

DD

11
12
13
14
15
16

17

18
19

20
21
22
23
24

25

PIN 1

26

I2S1

27

I2S0

AD9880

TOP VIEW

(Not to Scale)

31

33

GND

32

DV

34

D

DD

V

RX0–

29

30

28

DD

GND

DV

S/PDIF

37

38

39

42

35

36

GND

RX0+

40

GND

RX1–

RX2–

RX1+

44

41

43

GND

RX2+

RxC–

RxC+

48

45

46

47

D

V

DD

GND

DV

RTERM

Figure 2. Pin Configuration

75

GND

74

G

AIN0

73

SOGIN0

72

V

D

71

G

AIN1

70

SOGIN1

69

GND

68

B

AIN0

67

V

D

66

B

AIN1

65

GND

64

HSYNC 0

63

HSYNC 1

62

EXTCLK/COAST

61

VSYNC 0

60

VSYNC 1

59

PV

DD

58

GND

57

FILT

56

PV

DD

55

GND

54

PV

DD

53

ALGND

52

MDA

51

MCL

49

50

DDC_SCL

DDC_SDA

05087-002

Table 4. Complete Pinout List

Pin Type Pin No. Mnemonic Function Value

INPUTS 79 R
77 R
74 G
71 G
68 BB
66 BB

AIN0

AIN1

AIN0

AIN1

AIN0

AIN1

Analog Input for Converter R Channel 0 0.0 V to 1.0 V
Analog Input for Converter R Channel 1 0.0 V to 1.0 V
Analog Input for Converter G Channel 0 0.0 V to 1.0 V
Analog Input for Converter G Channel 1 0.0 V to 1.0 V
Analog Input for Converter B Channel 0 0.0 V to 1.0 V

Analog Input for Converter B Channel 1 0.0 V to 1.0 V
64 HSYNC0 Horizontal SYNC Input for Channel 0 3.3 V CMOS
63 HSYNC1 Horizontal SYNC Input for Channel 1 3.3 V CMOS
61 VSYNC0 Vertical SYNC Input for Channel 0 3.3 V CMOS
60 VSYNC1 Vertical SYNC Input for Channel 1 3.3 V CMOS
73 SOGIN0 Input for Sync-on-Green Channel 0 0.0 V to 1.0 V
70 SOGIN1 Input for Sync-on-Green Channel 1 0.0 V to 1.0 V
62 EXTCLK External Clock Input—Shares Pin with COAST 3.3 V CMOS
62 COAST PLL COAST Signal Input—Shares Pin with EXTCLK 3.3 V CMOS
81 PWRDN Power-Down Control 3.3 V CMOS

Rev. 0 | Page 7 of 64

AD9880

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Pin Type Pin No. Mnemonic Function Value

OUTPUTS 92 to 99 RED [7:0] Outputs of Red Converter, Bit 7 is MSB V
2 to 9 GREEN [7:0] Outputs of Green Converter, Bit 7 is MSB V
12 to 19 BLUE [7:0] Outputs of Blue Converter, Bit 7 is MSB V
89 DATACK Data Output Clock V
87 HSOUT HSYNC Output Clock (Phase-Aligned with DATACK) V
85 VSOUT VSYNC Output Clock (Phase-Aligned with DATACK) V
86 SOGOUT SOG Slicer Output V
84 O/E FIELD Odd/Even Field Output V
REFERENCES 57 FILT Connection For External Filter Components For PLL
POWER SUPPLY

80, 76, 72,

V

D

Analog Power Supply and DVI Terminators 3.3 V

67, 45, 33
100, 90, 10 V
59, 56, 54 PV
48, 32, 30 DV

DD

DD

DD

Output Power Supply 1.8 V to 3.3 V
PLL Power Supply 1.8 V

Digital Logic Power Supply 1.8 V
GND Ground 0 V
CONTROL 83 SDA Serial Port Data I/O 3.3 V CMOS
82 SCL Serial Port Data Clock 3.3 V CMOS
HDCP 49 DDC_SCL HDCP Slave Serial Port Data Clock 3.3 V CMOS
50 DDC_SDA HDCP Slave Serial Port Data I/O 3.3 V CMOS
51 MCL HDCP Master Serial Port Data Clock 3.3 V CMOS
52 MDA HDCP Master Serial Port Data I/O 3.3 V CMOS
AUDIO DATA OUTPUTS 28 S/PDIF S/PDIF Digital Audio Output V
27 I2S0 I2S Audio (Channels 1, 2) V
26 I2S1 I2S Audio (Channels 3, 4) V
25 I2S2 I2S Audio (Channels 5, 6) V
24 I2S3 I2S Audio (Channels 7, 8) V
20 MCLKIN External Reference Audio Clock In V
21 MCLKOUT Audio Master Clock Output V
22 SCLK Audio Serial Clock Output V
23 LRCLK Data Output Clock For Left And Right Audio Channels V
DIGITAL VIDEO DATA 35 Rx0+ Digital Input Channel 0 True TMDS
34 Rx0− Digital Input Channel 0 Complement TMDS
38 Rx1+ Digital Input Channel 1 True TMDS
37 Rx1− Digital Input Channel 1 Complement TMDS
41 Rx2+ Digital Input Channel 2 True TMDS
40 Rx2− Digital Input Channel 2 Complement TMDS
DIGITAL VIDEO CLOCK INPUTS 43 RxC+ Digital Data Clock True TMDS
44 RxC− Digital Data Clock Complement TMDS
DATA ENABLE 88 DE Data Enable 3.3 V CMOS
RTERM 46 RTERM Sets Internal Termination Resistance

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

500Ω

Rev. 0 | Page 8 of 64

AD9880

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Table 5. Pin Function Descriptions

Pin Description

INPUTS

R

AIN0

G

AIN0

BB

AIN0

R

AIN1

G

AIN1

BB

AIN1

Rx0+ Digital Input Channel 0 True.
Rx0− Digital Input Channel 0 Complement.
Rx1+ Digital Input Channel 1 True.
Rx1− Digital Input Channel 1 Complement.
Rx2+ Digital Input Channel 2 True.
Rx2−

RxC+ Digital Data Clock True.
RxC−

HSYNC0 Horizontal Sync Input Channel 0.
HSYNC1

VSYNC0 Vertical Sync Input Channel 0.
VSYNC1

SOGIN0 Sync-On-Green Input Channel 0.
SOGIN1

EXTCLK/COAST

EXTCLK/COAST External Clock.

Analog Input for the Red Channel 0.
Analog Input for the Green Channel 0.
Analog Input for the Blue Channel 0.
Analog Input for the Red Channel 1.
Analog Input for the Green Channel 1.
Analog Input for Blue Channel 1.

High impedance inputs that accept the red, green, and blue channel graphics signals, respectively. The three channels
are identical, and can be used for any colors, but colors are assigned for convenient reference. They accommodate
input signals ranging from 0.5 V to 1.0 V full scale. Signals should be ac-coupled to these pins to support clamp
operation. (see Figure 3 for an input reference circuit).

Digital input Channel 2 Complement.
These six pi
from a digital graphics transmitter.

Digital Data Clock Complement.
This cloc

Horizontal Sync Input Channel 1.
These inputs r
reference for pixel clock generation. The logic sense of this pin is controlled by serial register 0x12 Bits 5:4 (Hsync
polarity). Only the leading edge of Hsync is active; the trailing edge is ignored. When Hsync Polarity = 0, the falling
edge of Hsync is used. When Hsync Polarity = 1, the rising edge is active. The input includes a Schmitt trigger for noise
immunity.

Vertical Sync Input Channel 1.
These ar

Sync-On-Green Input Channel 1.
These inputs ar
pin is connected to a high speed comparator with an internally generated threshold. The threshold level can be
programmed in 10 mV steps to any voltage between 10 mV and 330 mV above the negative peak of the input signal.
The default voltage threshold is 150 mV. When connected to an ac-coupled graphics signal with embedded sync, it
produces a noninverting digital output on SOGOUT. (This is usually a composite sync signal, containing both vertical
and horizontal sync (Hsync) information that must be separated before passing the horizontal sync signal to Hsync.)
When not used, this input should be left unconnected. For more details on this function and how it should be
configured, refer to the

Coast Input to Clock Generator (Optional).

his input may be used to cause the pixel clock generator to stop synchronizing with Hsync and continue producing a

T
clock at its current frequency and phase. This is useful when processing signals from sources that fail to produce
horizontal sync pulses during the vertical interval. The Coast signal is generally not required for PC-generated signals.
The logic sense of this pin is controlled by Coast polarity (Register 0x18, Bits 6:5). When not used, this pin may be
grounded and input Coast polarity programmed to 1 (Register 0x18, Pin 5), or tied high (to V
and input Coast polarity programmed to 0. Input Coast polarity defaults to 1 at power-up. This pin is shared with the
EXTCLK function, which does not affect Coast functionality. For more details on Coast, see the description in the

neration section.

Ge

This allows the insertion of an external clock sour
shared with the Coast function, which will not affect EXTCLK functionality.

ns receive three pairs TMDS (Transition Minimized Differential Signaling) pixel data (at 10X the pixel rate)

k pair receives a TMDS clock at 1× pixel data rate.

eceive a logic signal that establishes the horizontal timing reference and provides the frequency

e the inputs for vertical sync.

e provided to assist with processing signals with embedded sync, typically on the green channel. The

Hsync and Vsync Inputs section.

through a 10 KΩ resistor)

D

ce rather than the internally generated PLL locked clock. This pin is

Clock

Rev. 0 | Page 9 of 64

AD9880

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Pin Description

PWRDN

FILT External Filter Connection.

OUTPUTS

HSOUT

VSOUT

SOGOUT

O/E FIELD

SERIAL PORT

SDA Serial Port Data I/O for programming AD9880 registers – I2C address is 0x98.
SCL Serial Port Data Clock for programming AD9880 registers.
DDCSDA Serial Port Data I/O for HDCP communications to transmitter – I2C address is 0x74 or 0x76.
DDCSCL Serial Port Data Clock for HDCP communications to transmitter.
MDA Serial Port Data I/O to EEPROM with HDCP keys – I2C address is 0xA0
MCL Serial Port Data Clock to EEPROM with HDCP keys.

DATA OUTPUTS

Red [7:0] Data Output, Red Channel.
Green [7:0] Data Output, Green Channel.
Blue [7:0]

DATA CLOCK

OUTPUT
DATACK

Power-Down Control/Three-State Control.
The func

For proper operation, the pixel clock generator PLL requires an ex
this pin. F
PCB Layout Recommendations.

Horizontal Sync Output.
A r
programmed via serial bus registers. By maintaining alignment with DATACK and Data, data timing with respect to
horizontal sync can always be determined.

Vertical Sync Output.
The separa
can be controlled via serial bus bit (Register 0x24 [6]).

Sync-On-Green Slicer Output.
This pin outputs one of f
Hsync from the filter, or the filtered Hsync. See the Sync processing block diagram (see Figure 8) to view how this pin is
c
performed via the sync separator.

Odd/Even Field Bit for Interlaced Video. This output will identify whether the cur
or even. The polarity of this signal is programmable via Register 0x24[4].

Data Output, Blue Channel. The main data outputs
fixed, but will be different if the color space converter is used. When the sampling time is changed by adjusting the
phase register, the output timing is shifted as well. The DATACK and HSOUT outputs are also moved, so the timing
relationship among the signals is maintained.

Data Clock Output.
T
clocks can be selected with Register 0x25 [7:6]. These are related to the pixel clock (1/2× pixel clock, 1× pixel clock, 2×
frequency pixel clock and a 90° phase shifted pixel clock) and they are produced either by the internal PLL clock
generator or EXTCLK and are synchronous with the pixel sampling clock. The polarity of DATACK can also be inverted
via Register 0x24 [0]. The sampling time of the internal pixel clock can be changed by adjusting the phase register.
When this is changed, the pixel-related DATACK timing is shifted as well. The DATA, DATACK, and HSOUT outputs are all
moved, so the timing relationship among the signals is maintained.

tion of this pin is programmable via Register 0x26 [2:1].

ternal filter. Connect the filter shown in Figure 6 to

or optimal performance, minimize noise and parasitics on this node. For more information see the section on

econstructed and phase-aligned version of the Hsync input. Both the polarity and duration of this output can be

ted Vsync from a composite signal or a direct pass through of the Vsync signal. The polarity of this output

our possible signals (controlled by Register 0x1D [1:0]): raw SOG, raw Hsync, regenerated

onnected. (Note: besides slicing off SOG, the output from this pin is not processed on the AD9880. Vsync separation is

rent field (in an interlaced signal) is odd

. Bit 7 is the MSB. The delay from pixel sampling time to output is

his is the main clock output signal used to strobe the output data and HSOUT into external logic. Four possible output

Rev. 0 | Page 10 of 64

AD9880

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Pin Description

POWER SUPPLY1

VD (3.3 V)

VDD (1.8 V – 3.3 V)

PVDD (1.8 V)

DVDD (1.8 V)

GND

1

The supplies should be sequenced such that VD and VDD are never less than 300 mV below DVDD. At no time should DVDD be more than 300 mV greater than VD or

VDD.

Analog Power Supply.
These pins

Digital Output Power Supply.
A large number of output pins (up to 27) switching at high speed (up to 150 MHz) generates many power supply
transients (noise). These supply pins are identified separately from the VD pins so special care can be taken to minimize
output noise transferred into the sensitive analog circuitry. If the AD9880 is interfacing with lower voltage logic, V
may be connected to a lower supply voltage (as low as 1.8 V) for compatibility.

Clock Generator Power Supply.
The most sensiti
and help the user design for optimal performance. The designer should provide quiet, noise-free power to these pins.

Digital Input Power Supply.
This sup

Ground.
The g
plane, with careful attention to ground current paths.

supply power to the ADCs and terminators. They should be as quiet and filtered as possible.

DD

ve portion of the AD9880 is the clock generation circuitry. These pins provide power to the clock PLL

plies power to the digital logic.

round return for all circuitry on chip. It is recommended that the AD9880 be assembled on a single solid ground

Rev. 0 | Page 11 of 64

AD9880

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DESIGN GUIDE

GENERAL DESCRIPTION

The AD9880 is a fully integrated solution for capturing analog
RGB or YUV signals and digitizing them for display on flat
panel monitors, projectors, or PDPs. In addition, the AD9880
has a digital interface for receiving DVI/HDMI signals and
is capable of decoding HDCP encrypted signals through con­nections to an internal EEPROM. The circuit is ideal for
providing an interface for HDTV monitors or as the front end
to high performance video scan converters.

Implemented in a high-performance CMOS process, the
in

terface can capture signals with pixel rates of up to 150 MHz.

The AD9880 includes all necessary input buffering, signal dc
r

estoration (clamping), offset and gain (brightness and contrast)
adjustment, pixel clock generation, sampling phase control, and
output data formatting. Included in the output formatting is a
color space converter (CSC), which accommodates any input
color space and can output any color space. All controls are
programmable via a 2-wire serial interface. Full integration of
these sensitive analog functions makes system design straight­forward and less sensitive to the physical and electrical
environment.

DIGITAL INPUTS

All digital control inputs (Hsync, Vsync, I2C) on the AD9880
operate to 3.3 V CMOS levels. In addition, all digital inputs
except the TMDS (HDMI/DVI) inputs are 5 V tolerant.
(Applying 5 V to them does not cause any damage.) TMDS
inputs (RX0+/–, RX1+/–, RX2+/–, and RXC+/–) must maintain
a 100 Ω differential impedance (through proper PCB layout)
from the connector to the input where they are internally
terminated (50 Ω to 3.3 V). If additional ESD protection is
desired, use of a California Micro Devices (CMD) CM1213
(among others) series low capacitance ESD protection offers 8
kV of protection to the HDMI TMDS lines.

In an ideal world of perfectly matched impedances, the best

rformance can be obtained with the widest possible signal

pe
bandwidth. The ultrawide bandwidth inputs of the AD9880
(330 MHz) can track the input signal continuously as it moves
from one pixel level to the next, and digitizes the pixel during a
long, flat pixel time. In many systems, however, there are
mismatches, reflections, and noise, which can result in excessive
ringing and distortion of the input waveform. This makes it
more difficult to establish a sampling phase that provides good
image quality. It has been shown that a small inductor in series
with the input is effective in rolling off the input bandwidth
slightly, and providing a high quality signal over a wider range
of conditions. Using a Fair-Rite #2508051217Z0 High Speed
Signal Chip Bead inductor in the circuit shown in

od results in most applications.

go

RGB

INPUT

Figure 3. Analog Input Interface Circuit

47nF

75Ω

Figure 3 gives

R

AIN

G

AIN

B

AIN

05087-003

HSYNC AND VSYNC INPUTS

The interface also takes a horizontal sync signal, which is used
to generate the pixel clock and clamp timing. This can be either
a sync signal directly from the graphics source, or a prepro­cessed TTL or CMOS level signal.

The Hsync input includes a Schmitt trigger buffer for immunity
t

o noise and signals with long rise times. In typical PC-based
graphic systems, the sync signals are simply TTL-level drivers
feeding unshielded wires in the monitor cable. As such, no
termination is required.

SERIAL CONTROL PORT

The serial control port is designed for 3.3 V logic. However, it is
tolerant of 5 V logic signals.

ANALOG INPUT SIGNAL HANDLING

The AD9880 has six high-impedance analog input pins for the
red, green, and blue channels. They accommodate signals
ranging from 0.5 V to 1.0 V p-p.

Signals are typically brought onto the interface board via a

VI-I connector, a 15-pin D connector, or RCA-type

D
connectors. The AD9880 should be located as close as practical
to the input connector. Signals should be routed via 75 
matched impedance traces to the IC input pins.

At that point the signal should be resistively terminated (75 

o the signal ground return) and capacitively coupled to the

t
AD9880 inputs through 47 nF capacitors. These capacitors form
part of the dc restoration circuit.

Rev. 0 | Page 12 of 64

OUTPUT SIGNAL HANDLING

The digital outputs are designed to operate from 1.8 V to 3.3 V
(V

).

DD

CLAMPING

RGB Clamping

To properly digitize the incoming signal, the dc offset of the
input must be adjusted to fit the range of the on-board ADC.

Most graphics systems produce RGB signals with black at
g

round and white at approximately 0.75 V. However, if sync
signals are embedded in the graphics, the sync tip is often at
ground and black is at 300 mV. Then white is at approximately

1.0 V. Some common RGB line amplifier boxes use emitter­follower buffers to split signals and increase drive capability.

AD9880

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This introduces a 700 mV dc offset to the signal, which must be
removed for proper capture by the AD9880.

within ½ LSB in 10 lines with a clamp duration of 20 pixel
periods on a 75 Hz SXGA signal.

The key to clamping is to identify a portion (time) of the signal

hen the graphic system is known to be producing black. An

w
offset is then introduced which results in the ADCs producing a
black output (Code 0x00) when the known black input is
present. The offset then remains in place when other signal
levels are processed, and the entire signal is shifted to eliminate
offset errors.

In most pc graphics systems, black is transmitted between active

ideo lines. With CRT displays, when the electron beam has

v
completed writing a horizontal line on the screen (at the right
side), the beam is deflected quickly to the left side of the screen
(called horizontal retrace) and a black signal is provided to
prevent the beam from disturbing the image.

In systems with embedded sync, a blacker-than-black signal
(H

sync) is produced briefly to signal the CRT that it is time to
begin a retrace. For obvious reasons, it is important to avoid
clamping on the tip of Hsync. Fortunately, there is virtually
always a period following Hsync called the back porch where a
good black reference is provided. This is the time when
clamping should be done.

Clamp timing employs the AD9880 internal clamp timing

enerator. The clamp placement register is programmed with

g
the number of pixel periods that should pass after the trailing
edge of Hsync before clamping starts. A second register (clamp
duration) sets the duration of the clamp. These are both 8-bit
values, providing considerable flexibility in clamp generation.
The clamp timing is referenced to the trailing edge of Hsync
because, though Hsync duration can vary widely, the back
porch (black reference) always follows Hsync. A good starting
point for establishing clamping is to set the clamp placement to
0x08 (providing 8 pixel periods for the graphics signal to
stabilize after sync) and set the clamp duration to 0x14 (giving
the clamp 20 pixel periods to reestablish the black reference).
For three-level syncs embedded on the green channel, it is
necessary to increase the clamp placement to beyond the posi­tive portion of the sync. For example, a good clamp placement
(Register 0x19) for a 720p input is 0x26. This delays the start of
clamp by 38 pixel clock cycles after the rising edge of the three­level sync, allowing plenty of time for the signal to return to a
black reference.

YUV Clamping

YUV graphic signals are slightly different from RGB signals in
that the dc reference level (black level in RGB signals) can be
at the midpoint of the graphics signal rather than the bottom.
For these signals it can be necessary to clamp to the midscale
range of the ADC range (128) rather than bottom of the ADC
range (0).

Clamping to midscale rather than ground can be accomplished
b

y setting the clamp select bits in the serial bus register. Each of
the three converters has its own selection bit so that they can be
clamped to either midscale or ground independently. These bits
are located in Register 0x1B [7:5]. The midscale reference
voltage is internally generated for each converter.

Auto Offset

The auto-offset circuit works by calculating the required offset
setting to yield a given output code during clamp. When this
block is enabled, the offset setting in the I
clamp code rather than an actual offset. The circuit compares
the output code during clamp to the desired code and adjusts
the offset up or down to compensate.

The offset on the AD9880 can be adjusted automatically to a
s

pecified target code. Using this option allows the user to set the
offset to any value and be assured that all channels with the
same value programmed into the target code will match. This
eliminates any need to adjust the offset at the factory. This
function is capable of running continuously anytime the clamp
is asserted.

There is an offset adjust register for each channel, namely the

ffset registers at Addresses 0x08, 0x0A, and 0x0C. The offset

o
adjustment is a signed (twos complement) number with
±64 LSB range. The offset adjustment is added to whatever
offset the auto-offset comes up with. For example: using ground
clamp, the target code is set to 4. To get this code, the auto­offset generates an offset of 68. If the offset adjustment is set to
10, the offset sent to the converter is 78. Likewise, if the offset
adjust is set to –10, the offset sent to the converter is 58. Refer to
application note AN-775, Implementing the Auto-Offset
Function of the AD9880, for a detailed description of how to
use this function.

2

C is seen as a desired

Clamping is accomplished by placing an appropriate charge on
t

he external input coupling capacitor. The value of this capa­citor affects the performance of the clamp. If it is too small,
there is a significant amplitude change during a horizontal line
time (between clamping intervals). If the capacitor is too large,
then it takes excessively long for the clamp to recover from a
large change in incoming signal offset. The recommended value
(47 nF) results in recovering from a step error of 100 mV to

Rev. 0 | Page 13 of 64

Sync-on-Green (SOG)

The SOG input operates in two steps. First, it sets a baseline
clamp level off of the incoming video signal with a negative
peak detector. Second, it sets the sync trigger level to a
programmable level (typically 150 mV) above the negative
peak. The SOG input must be ac-coupled to the green analog
input through its own capacitor. The value of the capacitor must
be 1 nF ± 20%. If SOG is not used, this connection is not

AD9880

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required. Note that the SOG signal is always negative polarity.
For additional detail on setting the SOG threshold and other
SOG-related functions, see the

47nF

47nF

47nF

1nF

Figure 4. Typical Clamp Configuration for RGB/YUV Applications

Clock Generation

A PLL is employed to generate the pixel clock. In this PLL,
the Hsync input provides a reference frequency. A voltage
controlled oscillator (VCO) generates a much higher pixel clock
frequency. This pixel clock is divided by the PLL divide value
(Registers 0x01 and 0x02) and phase compared with the Hsync
input. Any error is used to shift the VCO frequency and
maintain lock between the two signals.

The stability of this clock is a very important element in provi-

g the clearest and most stable image. During each pixel time,

din
there is a period during which the signal slews from the old
pixel amplitude and settles at its new value. This is followed by a
time when the input voltage is stable before the signal must slew
to a new value. The ratio of the slewing time to the stable time is
a function of the bandwidth of the graphics DAC and the
bandwidth of the transmission system (cable and termination).
It is also a function of the overall pixel rate. Clearly, if the
dynamic characteristics of the system remain fixed, then the
slewing and settling time is likewise fixed. This time must be
subtracted from the total pixel period, leaving the stable period.
At higher pixel frequencies, the total cycle time is shorter and
the stable pixel time also becomes shorter.

PIXEL CLOCK INVALID SAMPLE TIMES

Sync Processing section.

R

AIN

B

AIN

G

AIN

SOG

05087-004

The PLL characteristics are determined by the loop filter design,

he PLL charge pump current, and the VCO range setting. The

t
loop filter design is illustrated in Figure 6. Recommended set­t

ings of the VCO range and charge pump current for VESA

standard display modes are listed in

C

P

8nF

R

1.5kΩ

FILT

Figure 6. PLL Loop Filter Detail

Tabl e 8.

PV

C

Z

80nF

Z

D

05087-006

Four programmable registers are provided to optimize the
performance of the PLL. These registers are

• The 12-Bi

t Divisor Register. The input Hsync frequency
range can be any frequency which, combined with the
PLL_Div, does not exceed the VCO range . The PLL multi­plies the frequency of the Hsync signal, producing pixel
clock frequencies in the range of 10 MHz to 100 MHz. The
divisor register controls the exact multiplication factor.

• The 2-Bi

t VCO Range Register. To improve the noise
performance of the AD9880, the VCO operating frequency
range is divided into four overlapping regions. The VCO
range register sets this operating range. The frequency
ranges for the lowest and highest regions are shown in
Tabl e 6.

• Table 6.

VCORNGE Pixel Rate Range

00 12-30
01 30-60
10 60-120
11 120-150

• The 5-Bit Phase Adjust Register. The phase of the

generated sampling clock can be shifted to locate an
optimum sampling point within a clock cycle. The phase
adjust register provides 32 phase-shift steps of 11.25° each.
The Hsync signal with an identical phase shift is available
through the HSOUT pin.

05087-005

Figure 5. Pixel Sampling Times

Any jitter in the clock reduces the precision with which the
sampling time can be determined and must also be subtracted
from the stable pixel time. Considerable care has been taken in
the design of the AD9880’s clock generation circuit to minimize
jitter. The clock jitter of the AD9880 is less than 13% of the total
pixel time in all operating modes, making the reduction in the
valid sampling time due to jitter negligible.

Rev. 0 | Page 14 of 64

The COAST pin or the internal Coast is used to allow the PLL
t

o continue to run at the same frequency, in the absence of the
incoming Hsync signal or during disturbances in Hsync (such
as equalization pulses). This can be used during the vertical
sync period or any other time that the Hsync signal is unavail­able. The polarity of the Coast signal can be set through the
Coast polarity register. Also, the polarity of the Hsync signal
can be set through the Hsync polarity register. For both Hsync
and Coast, a value of 1 is active high. The internal Coast
function is driven off the Vsync signal, which is typically a time
when Hsync signals can be disrupted with extra equalization
pulses.

AD9880

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Power Management

The AD9880 uses the activity detect circuits, the active interface
bits in the serial bus, the active interface override bits, the
power-down bit, and the power-down pin to determine the
correct power state. There are four power states: full-power,
seek mode, auto power-down and power-down.

Tabl e 7 s

ummarizes how the AD9880 determines which power
mode to be in and which circuitry is powered on/off in each of
these modes. The power-down command has priority and then

Table 7. Power-Down Mode Descriptions

Inputs
Mode Power-Down

1

Sync Detect

2

Auto PD Enable

Full Power 1 1 X Everything
Seek Mode 1 0 0 Everything
Seek Mode 1 0 1

Power-Down 0 X

1

Power-down is controlled via Bit 0 in Serial Bus Register 0x26.

2

Sync detect is determined by OR’ing Bits 7 to 2 in Serial Bus Register 0x15.

3

Auto power-down is controlled via Bit 7 in Serial Bus Register 0x27

Table 8. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats

Standard Resolution Refresh Rate Horizontal Frequency Pixel Rate VCO Range

VGA 640 × 480 60 Hz 31.5 kHz 25.175 MHz 00 101
72 Hz 37.7 kHz 31.500 MHz 01 011
75 Hz 37.5 kHz 31.500 MHz 01 100
85 Hz 43.3 kHz 36.000 MHz 01 100
SVGA 800 × 600 56 Hz 35.1 kHz 36.000 MHz 01 100
60 Hz 37.9 kHz 40.000 MHz 01 101
72 Hz 48.1 kHz 50.000 MHz 01 110
75 Hz 46.9 kHz 49.500 MHz 01 110
85 Hz 53.7 kHz 56.250 MHz 01 110
XGA 1024 × 768 60 Hz 48.4 kHz 65.000 MHz 10 011
70 Hz 56.5 kHz 75.000 MHz 10 100
75 Hz 60.0 kHz 78.750 MHz 10 100
80 Hz 64.0 kHz 85.500 MHz 10 101
85 Hz 68.3 kHz 94.500 MHz 10 110
SXGA 1280 × 1024 60 Hz 64.0 kHz 108.000 MHz 10 110
1280 × 1024 75 Hz 80.0 kHz 135.000 MHz 11 110
TV 480i 60 Hz 15.75 kHz 13.51 MHz 00 010
480p 60 Hz 31.47 kHz 27 MHz 00 101
720p 60 Hz 45 kHz 74.25 MHz 10 100
1035i 60 Hz 33.75 kHz 74.25 MHz 10 100
1080i 60 Hz 33.75 kHz 74.25 MHz 10 100
1080p 60 Hz 67.5 KHz 148.5 MHz 11 110

1

These are preliminary recommendations for the analog PLL and are subject to change without notice.

the automatic circuitry. The power-down pin (Pin 81—polarity
set by Register 0x26[3]) can drive the chip into four power­down options. Bits 2 and 1 of Register 0x26 control these four
options. Bit 0 controls whether the chip is powered down or the
outputs are placed in high impedance mode (with the exception
of SOG). Bits 7 to 4 of Register 0x26 control whether the
outputs, SOG, Sony Philips digital interface (SPDIF ) or I2S (IIS
or Inter IC sound bus) outputs are in high impedance mode or
not. See the 2-Wire Serial Control Register Detail section for
the details.

3

Power-On or Comments

Serial bus, sync activity detect, SOG, band gap

ference

re
Serial bus, sync activity detect, SOG, band gap

ference

re

1

Current

Rev. 0 | Page 15 of 64

AD9880

K

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TIMING

The output data clock signal is created so that its rising edge
always occurs between data transitions and can be used to latch
the output data externally.

There is a pipeline in the AD9880, which must be flushed

efore valid data becomes available. This means 23 data sets are

b
presented before valid data is available.

The timing diagram in Fi
AD9880.

DATAC

gure 7 shows the operation of the

t

PER

t

DCYCLE

clock generator during Vsync, it is important to ignore these
distortions. If the pixel clock PLL sees extraneous pulses, it
attempts to lock to this new frequency, and changes frequency
by the end of the Vsync period. It then takes a few lines of
correct Hsync timing to recover at the beginning of a new
frame, resulting in a tearing of the image at the top of the
display.

The Coast input is provided to eliminate this problem. It is an

nchronous input that disables the PLL input and allows the

asy
clock to free run at its then-current frequency. The PLL can free
run for several lines without significant frequency drift.

Coast can be generated internally by the AD9880 (see

ister 0x12 [1]), can be driven directly from a Vsync input,

Reg
or can be provided externally by the graphics controller.

t

SKEW

DATA

HSOUT

05087-007

Figure 7. Output Timing

Hsync Timing

Horizontal Sync (Hsync) is processed in the AD9880 to
eliminate ambiguity in the timing of the leading edge with
respect to the phase-delayed pixel clock and data.

The Hsync input is used as a reference to generate the pixel

mpling clock. The sampling phase can be adjusted, with

sa
respect to Hsync, through a full 360° in 32 steps via the phase
adjust register (to optimize the pixel sampling time). Display
systems use Hsync to align memory and display write cycles, so
it is important to have a stable timing relationship between the
Hsync output (HSOUT) and data clock (DATACK).

Three things happen to Hsync in the AD9880. First, the polarity

f Hsync input is determined and thus has a known output

o
polarity. The known output polarity can be programmed either
active high or active low (Register 0x24, Bit 7). Second, HSOUT
is aligned with DATACK and data outputs. Third, the duration
of HSOUT (in pixel clocks) is set via Register 0x23. HSOUT is
the sync signal that should be used to drive the rest of the
display system.

Coast Timing

In most computer systems, the Hsync signal is provided
continuously on a dedicated wire. In these systems, the Coast
input and function are unnecessary, and should not be used and
the pin should be permanently connected to the inactive state.

Sync Processing

The inputs of the sync processing section of the AD9880 are
combinations of digital Hsyncs and Vsyncs, analog sync-on­green, or sync-on-Y signals, and an optional external Coast
signal. From these signals it generates a precise, jitter-free (9%
or less at 95 MHz) clock from its PLL; an odd-/even-field signal;
Hsync and Vsync out signals; a count of Hsyncs per Vsync; and
a programmable SOG output. The main sync processing blocks
are the sync slicer, sync separator, Hsync filter, Hsync regen­erator, Vsync filter, and Coast generator.

The sync slicer extracts the sync signal from the green graphics

r luminance video signal that is connected to the SOGIN input

o
and outputs a digital composite sync. The sync separator’s task
is to extract Vsync from the composite sync signal, which can
come from either the sync slicer or the Hsync input. The Hsync
filter is used to eliminate any extraneous pulses from the Hsync
or SOGIN inputs, outputting a clean, low-jitter signal that is
appropriate for mode detection and clock generation. The
Hsync regenerator is used to recreate a clean, although not low
jitter, Hsync signal that can be used for mode detection and
counting Hsyncs per Vsync. The Vsync filter is used to elimi­nate spurious Vsyncs, maintain a stable timing relationship
between the Vsync and Hsync output signals, and generate the
odd/even field output. The Coast generator creates a robust
Coast signal that allows the PLL to maintain its frequency in
the absence of Hsync pulses.

In some systems, however, Hsync is disturbed during the verti­cal sy

nc period (Vsync). In some cases, Hsync pulses disappear.
In other systems, such as those that employ composite sync
(Csync) signals or embedded SOG, Hsync includes equalization
pulses or other distortions during Vsync. To avoid upsetting the

Rev. 0 | Page 16 of 64

AD9880

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Sync Slicer

The purpose of the sync slicer is to extract the sync signal from
the green graphics or luminance video signal that is connected
to the SOGIN input. The sync signal is extracted in a two step
process. First, the SOG input (typically 0.3 V below the black
level) is detected and clamped to a known dc voltage. Next, the

signal is routed to a comparator with a variable trigger level (set
by Register 0x1D, Bits [7:3]), but nominally 0.128 V above the
clamped voltage. The sync slicer output is a digital composite
sync signal containing both Hsync and Vsync information (see
Figure 9).

HSYNC 0

HSYNC 1

SOGIN 0

SOGIN 1

VSYNC 0

VSYNC 1

COAST

1

AD

1

AD

SYNC

SLICER

SYNC

SLICER

1

AD

1

AD

AD9880

1

ACTIVITY DETECT

2

POLARITY DETECT

3

REGENERATED HSYNC

4

FILTERED HSYNC

5

SET POLARITY

PD

PD

AD

AD

PD

PD

CHANNEL
SELECT

MUX

2

2

MUX

1

1

MUX

2

2

FILTER COAST VSYNC

VSYNC

0x12:0

[0x11:3]

PROCESSOR

VSYNC FILTER

SYNC

AND

HSYNC
SELECT

MUX

PLL SYNC FILTER EN

MUX

COAST SELECT

0x12:1

SP SYNC FILTER EN

0x21:6

COAST

Figure 8. Sync Processing Block Diagram

[0x11:7]

0x21:7

MUX

HSYNC

4

FH

MUX

PLL CLOCK

GENERATOR

HSYNC FILTER

AND

REGENERATOR

RH

SOGOUT SELECT

FILTERED

HSYNC/VSYNC

COUNTER

REG 26H, 27H

3

MUX

0x24:2,1

VSYNC

VSYNC

5

SP

MUX

VSYNC FILTER EN

0x21:5

5

SP

5

SP

5

SP

SOG OUT

VSYNC OUT

ODD/EVEN
FIELD

HSYNC OUT

DATACK

05087-008

NEGATIVE PULSE WIDTH = 40 SAMPLE CLOCKS

700mV MAXIMUM

SOG INPUT

SOGOUT OUTPUT

CONNECTED TO

HSYNCIN

COMPOSITE

SYNC

AT HSYNCIN

VSYNCOUT
FROM SYNC
SEPARATOR

–300mV

0mV

–300mV

Figure 9. Sync Slicer and Sync Separator Output

Rev. 0 | Page 17 of 64

04740-015

AD9880

www.BDTIC.com/ADI

Sync Separator

As part of sync processing, the sync separator’s task is to extract
Vsync from the composite sync signal. It works on the idea that
the Vsync signal stays active for a much longer time than the
Hsync signal. By using a digital low-pass filter and a digital
comparator, it rejects pulses with small durations (such as
Hsyncs and equalization pulses) and only passes pulses with
large durations, such as Vsync (see Figure 9).

The threshold of the digital comparator is programmable for
max

imum flexibility. To program the threshold duration, write
a value (N) to Register 0x11. The resulting pulse width is
N × 200 ns. So, if N = 5 the digital comparator threshold is 1 µs.
Any pulses less than 1 µs is rejected, while any pulse greater
than 1 µs passes through.

The sync separator on the AD9880 is simply an 8-bit digital
co

unter with a 6 MHz clock. It works independently of the
polarity of the composite sync signal. Polarities are determined
elsewhere on the chip. The basic idea is that the counter counts
up when Hsync pulses are present. But since Hsync pulses are
relatively short in width, the counter only reaches a value of N
before the pulse ends. It then starts counting down until
eventually reaching 0 before the next Hsync pulse arrives. The
specific value of N varies for different video modes, but is
always less than 255. For example with a 1 s width Hsync, the
counter only reaches 5 (1 s/200 ns = 5). Now, when Vsync is
present on the composite sync the counter also counts up.
However, since the Vsync signal is much longer, it counts to a
higher number, M. For most video modes, M is at least 255.
So, Vsync can be detected on the composite sync signal by
detecting when the counter counts to higher than N. The
specific count that triggers detection, T, can be programmed
through the Serial Register 0x11.

Once Vsync has been detected, there is a similar process to

ct when it goes inactive. At detection, the counter first

dete
resets to 0, then starts counting up when Vsync finishes.
Similarly to the previous case, it detects the absence of Vsync
when the counter reaches the threshold count, T. In this way, it
rejects noise and/or serration pulses. Once Vsync is detected to
be absent, the counter resets to 0 and begins the cycle again.

There are two things to keep in mind when using the sync

eparator. First, the resulting clean Vsync output is delayed

s

from the original Vsync by a duration equal to the digital
comparator threshold (N × 200 ns). Second, there is some
variability to the 200 ns multiplier value. The maximum varia­bility over all operating conditions is ±20% (160 ns to 240 ns).
Since normal Vsync and Hsync pulse widths differ by a factor of
about 500 or more, 20% variability is not an issue.

Hsync Filter and Regenerator

The Hsync filter is used to eliminate any extraneous pulses from
the Hsync or SOGIN inputs, outputting a clean, low-jitter signal
that is appropriate for mode detection and clock generation.
The Hsync regenerator is used to recreate a clean, although not
low jitter, Hsync signal that can be used for mode detection and
counting Hsyncs per Vsync. The Hsync regenerator has a high
degree of tolerance to extraneous and missing pulses on the
Hsync input, but is not appropriate for use by the PLL in
creating the pixel clock because of jitter.

The Hsync regenerator runs automatically and requires no

etup to operate. The Hsync filter requires the setting up of a

s
filter window. The filter window sets a periodic window of time
around the regenerated Hsync leading edge where valid Hsyncs
are allowed to occur. The general idea is that extraneous pulses
on the sync input occur outside of this filter window and thus
are filtered out. To set the filter window timing, program a value
(x) into Register 0x20. The resulting filter window time is ±x
times 25 ns around the regenerated Hsync leading edge. Just
as for the sync separator threshold multiplier, allow a ±20%
variance in the 25 ns multiplier to account for all operating
conditions (20 ns to 30 ns range).

A second output from the Hsync filter is a status bit (Reg-

ter 0x16[0]) that tells whether extraneous pulses are present

is
on the incoming sync signal or not. Extraneous pulses are often
included for copy protection purposes; this status bit can be
used to detect that.

The filtered Hsync (rather than the raw Hsync/SOGIN signal)

or pixel clock generation by the PLL is controlled by

f
Register 0x21[6]. The regenerated Hsync (rather than the
raw Hsync/SOGIN signal) for sync processing is controlled by
Register 0x21[7]. Use of the filtered Hsync and regenerated
Hsync is recommended. See Figure 10 for an illustration of a
filtered Hsync.

Rev. 0 | Page 18 of 64

AD9880

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HSYNCIN

FILTER

WINDOW

HSYNCOUT

VSYNC

Figure 10. Sync Processing Filter

Vsync Filter and Odd/Even Fields

The Vsync filter is used to eliminate spurious Vsyncs, maintain
a consistent timing relationship between the Vsync and Hsync
output signals, and generate the odd/even field output.

The filter works by examining the placement of Vsync with

spect to Hsync and, if necessary, slightly shifting it in time at

re
the VSOUT output. The goal is to keep the Vsync and Hsync
leading edges from switching at the same time, eliminating
confusion as to when the first line of a frame occurs. Enabling
the Vsync filter is done with Register 0x21[5]. Use of the Vsync
filter is recommended for all cases, including interlaced video,
and is required when using the Hsync per Vsync counter.
Figure 12 illustrates even/odd field determination in two
situations.

FILTER

WINDOW

QUADRANT

HSYNCIN

VSYNCIN

VSYNCOUT

O/E FIELD

QUADRANT

HSYNCIN

VSYNCIN

EQUALIZATION

PULSES

EXPECTED
EDGE

05087-010

SYNC SEPARATOR THRESHOLD

FIELD 1 FIELD 0

23 214431

EVEN FIELD

Figure 11.

SYNC SEPARATOR THRESHOLD

FIELD 1 FIELD 0

23 214431

FIELD 1 FIELD 0

FIELD 1 FIELD 0

05087-011

Rev. 0 | Page 19 of 64

VSYNCOUT

O/E FIELD

ODD FIELD

Figure 12. Vsync Filter—Odd/Even

05087-012

AD9880

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HDMI RECEIVER

The HDMI receiver section of the AD9880 allows the reception
of a digital video stream, which is backward-compatible with
DVI and able to accommodate not only video of various for­mats (RGB, YCrCb 4:4:4, 4:2:2), but also up to eight channels of
audio. Infoframes are transmitted carrying information about
the video format, audio clocks, and many other items necessary
for a monitor to utilize fully the information stream available.

The earlier digital visual interface (DVI) format was restricted

an RGB 24 bit color space only. Embedded in this data

to
stream were Hsyncs, Vsyncs and display enable (DE) signals,
but no audio information. The HDMI specification allows
trans-mission of all the DVI capabilities, but adds several
YCrCb formats that make the inclusion of a programmable
color space converter (CSC) a very desirable feature. With this,
the scaler following the AD9880 can specify that it always
wishes to receive a particular format, for instance, 4:2:2 YCrCb
regardless of the transmitted mode. If RGB is sent, the CSC can
easily convert that to 4:2:2 YCrCb while relieving the scaler of
this task.

In addition, the HDMI specification supports the transmission
o

f up to eight channels of S/PDIF or I2S audio. The audio
information is packetized and transmitted during the video
blanking periods along with specific information about the
clock frequency. Part of this audio information (Audio
Infoframe) tells the user how many channels of audio, where
they should be placed, information regarding the source (make,
model), and other data.

DE GENERATOR

The AD9880 has an onboard generator for DE, for start of
active video (SAV), and for end of active video (EAV), all of
which are necessary for describing the complete data stream for
a BT656 compatible output. In addition to this particular
output, it is possible to generate the DE for cases in which a
scaler is not planned to be used. This signal alerts the following
circuitry as to which are displayable video pixels.

4:4:4 TO 4:2:2 FILTER

The AD9880 contains a filter which allows it to convert a signal
from YCrCb 4:4:4 to YCrCb 4:2:2 while maintaining the
maximum accuracy and fidelity of the original signal.

Input Color space to Output Color space

The AD9880 can accept a wide variety of input formats and
either retain that format or convert to another. Input formats
supported are

• 4:4:4 Y

• 4:2:2 Y

• RG

CrCb 8 bit

CrCb 8, 10, and 12 bit

B 8-bit

Output modes supported are

• 4:4:4 Y

• 4:2:2 Y

• Dual 4:2:2

CrCb 8 bits

CrCb 8, 10, and 12 bits

YCrCb 8 bits.

Color space Conversion (CSC) Matrix

The color space conversion (CSC) matrix in the AD9880
consists of three identical processing channels. In each channel,
three input values are multiplied by three separate coefficients.
Also included are an offset value for each row of the matrix and
a scaling multiple for all values. Each value has a 13 bit twos
complement resolution to ensure the signal integrity is main­tained. The CSC is designed to run at speeds up to 150 MHz
supporting resolutions up to 1080 p at 60 Hz. With any-to-any
color space support, formats such as RGB, YUV, YCbCr, and
others are supported by the CSC.

The main inputs, Rin, Gin, and Bin come from the 8- to 12-bit
in

puts from each channel. These inputs are based on the input
format detailed in Ta b le 7 to Ta bl e 15. The mapping of these
inputs to the CSC inputs is shown in Tab l e 9.

Table 9. CSC Port Mapping

Input Channel CSC Input Channel

R/CR R
Gr/Y G
B/CB BB

IN

IN

IN

One of the three channels is represented in Figure 13. In each
processing channel the three inputs are multiplied by three
separate coefficients marked a1, a2, and a3. These coefficients
are divided by 4096 to obtain nominal values ranging from
–0.9998 to +0.9998. The variable labeled a4 is used as an offset
control. The CSC_mode setting is the same for all three
processing channels. This multiplies all coefficients and offsets
by a factor of 2

csc_mode

.

The functional diagram for a single channel of the CSC as

n Figure 13 is repeated for the remaining G and B

shown i
channels. The coefficients for these channels are b1, b2, b3, b4,
c1, c2, c3, and c4.

CSC_MODE[1:0]

+

a4[12:0]

+

×4

2

R

[11:0]

×2

OUT

1

0

a1[12:0]

[11:0]

R

IN

B

[11:0]

IN

G

[11:0]

IN

×

a2[12:0]

×

a3[12:0]

×

1

×

×

×

+

4096

1

4096

1

4096

Figure 13. Single CSC Channel

05087-013

Rev. 0 | Page 20 of 64