Analog Devices AD9877 a Datasheet

Mixed-Signal Front End

FEATURES Low Cost 3.3 V CMOS MxFE™ for

MCNS-DOCSIS, DVB-, DAVIC-Compliant Set-Top Box and Cable Modem Applications

232 MHz Quadrature Digital Upconverter

12-Bit Direct IF DAC (TxDAC+ Up to 65 MHz Carrier Frequency DDS Programmable Sampling Clock Rates Selectable Interpolation Filter

Analog Tx Output Level Adjust 12-Bit, 33 MSPS Direct IF ADC Dual 8-Bit, 16.5 MSPS Sampling IQ ADCs Two 12-Bit ⌺-⌬ Auxiliary DACs Direct Interface to AD8321/AD8325 or AD8322/AD8327

PGA Cable Driver

APPLICATIONS Cable Modems Set-Top Boxes Wireless Modems

)

Tx DATA

SPORT

PROFILE

RxIQ DATA

RxIF DATA

Set-Top Box, Cable Modem

AD9877

FUNCTIONAL BLOCK DIAGRAM

COS

SIN

DAC

⌺-⌬

ADC

SDELTA0

SDELTA1 OSCOUT

I IN

Q IN

IF IN

PLL

AD9877

INTER-

POLATOR

FILTER

DDS

CONTROL FUNCTIONS

GENERAL DESCRIPTION

The AD9877 is a single-supply cable modem/set-top box mixed-signal front end. The device contains a transmit path interpolation filter, a complete quadrature digital upconverter, and a transmit DAC. The receive path contains a 12-bit ADC and dual 8-bit ADCs. All internally required clocks and an output system clock are generated by the PLL from a single crystal or clock input.

The transmit path interpolation filter provides upsampling factors of 12⫻ or 16⫻ with an output signal bandwidth as high as 5.8 MHz. Carrier frequencies up to 65 MHz with 26 bits of frequency tuning resolution can be generated by the direct digital synthesizer (DDS). The transmit DAC resolution is 12 bits and can run at sampling rates as high as 232 MSPS. Analog output scaling from 0 dB to

7.5 dB in 0.5 dB steps is available to preserve SNR when reduced output levels are required.

The 12-bit ADC has excellent undersampling performance, allowing it to deliver better than 10 ENOBs with IF inputs up to 70 MHz. The 12-bit IF ADC can sample at a rate up to 33 MHz, allowing it to process wideband signal inputs.

Two programmable sigma-delta DACs are available and can be used to control external components, such as variable gain amplifiers (VGAs) or voltage-controlled tuners.

The AD9877 integrates a CA port that enables a host processor to control the AD8321/AD8325 or AD8322/AD8327 programmable gain amplifier (PGA) cable drivers via the MxFE SPORT.

The AD9877 is available in a 100-lead MQFP package. It offers enhanced receive path undersampling performance and lower cost, compared to the pin-compatible AD9873. The AD9877 is specified over the extended industrial (–40

C to +85oC) temperature range.

MxFE is a trademark of Analog Devices, Inc. TxDAC+ is a registered trademark of Analog Devices, Inc.

REV. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002

AD9877–SPECIFICATIONS

= 54 MHz (M = 8 and N = 4). ADC sample frequencies derived from PLL (f

MCLK

(VAS = 3.3 V ⴞ 5%, V

= 3.3 V ⴞ 10%, f

), R

MCLK

= 4.02 k⍀, max. fine gain, 75 ⍀ DAC load.)

SET

= 27 MHz, f

OSCIN

SYSCLK

= 216 MHz,

Test

Parameter Temp Level Min Typ Max Unit

SYSTEM CLOCK DAC SAMPLING, f

SYSCLK

Frequency Range (N = 4) Full II 232 MHz Frequency Range (N = 3) Full II 177 MHz

OSCIN and XTAL CHARACTERISTICS

Frequency Range Full II 3 33 MHz Duty Cycle 25ºC II 35 50 65 % Input Impedance 25ºC III 100 3 MΩ pF

MCLK JITTER

Cycle to Cycle (f

derived from PLL) 25ºC III 6 ps rms

MCLK

Tx DAC CHARACTERISTICS

Resolution N/A N/A 12 Bits Full-Scale Output Current Full II 4 10 20 mA Gain Error (using internal reference) Full II –2.5 –1 +2.5 %FS Offset Error 25ºC III ±1.0 %FS Reference Voltage (REFIO Level) 25ºC III 1.23 V Differential Nonlinearity (DNL) 25ºC III ±2.5 LSB Integral Nonlinearity (INL) 25ºC III ±8 LSB Output Capacitance 25ºC III 5 pF Phase Noise @ 1 kHz Offset, 42 MHz Carrier 25ºC III –110 dBc/Hz Output Voltage Compliance Range Full II –0.5 +1.5 V Wideband SFDR

5 MHz Analog Out, I 65 MHz Analog Out,

= 10 mA Full I 48 55 dBc

OUT

= 10 mA Full I 48 51 dBc

OUT

Narrow-Band SFDR (±1 MHz Window):

65 MHz Analog Out, I

= 10 mA Full I 53 69 dBc

OUT

Tx MODULATOR CHARACTERISTICS

I/Q Offset Full II 50 55 dB Pass-Band Amplitude Ripple (f < f Pass-Band Amplitude Ripple (f < f Stop-Band Response (f > f

× 3/4) Full II –63 dB

IQCLK

/8) Full II ±0.1 dB

IQCLK

/4) Full II ±0.5 dB

IQCLK

Tx GAIN CONTROL

Gain Step Size 25ºC III 0.5 dB Gain Step Error 25ºC III 0.05 dB Settling Time, 1% (Full-Scale Step) 25ºC III 1.8 µs

8-BIT ADC CHARACTERISTICS

Resolution N/A N/A 8 Bits Conversion Rate Full II 16.5 MHz Pipeline Delay N/A N/A 3.5 ADC Cycles Offset Matching between I and Q ADCs ±8.0 LSBs Gain Matching between I and Q ADCs ±2.0 LSBs Analog Input

Input Voltage Range Full II 1 Vppd Differential Input Impedance 25ºC III 42kΩpF Full Power Bandwidth 25ºC III 90 MHz Input Referred Noise 25ºC III 600 µV

Dynamic Performance (A

= –0.5 dBFS, f = 5 MHz)

Signal-to-Noise and Distortion (SINAD) Full I 40.8 47.3 dB Effective Number of Bits (ENOB) Full I 6.5 7.6 Bits Total Harmonic Distortion (THD) Full I –60.1 –50.0 dB Spurious-Free Dynamic Range (SFDR) Full I 52.0 63.0 dB

Reference Voltage Error

REFT8-REFB8 (0.5 V) Full I –100 ±10 +100 mV

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REV. A

AD9877

Test

Parameter Temp Level Min Typ Max Unit

12-BIT ADC CHARACTERISTICS

Resolution N/A N/A 12 Bits Conversion Rate Full II 33 MHz Pipeline Delay N/A N/A 5.5 ADC Cycles Analog Input

Input Voltage Range Full III 2 Vppd Differential Input Impedance 25ºC III 4.2 kΩ, pF Aperture Delay 25ºC III 2.0 ns Aperture Uncertainty (Jitter) 25ºC III 1.2 ps rms Full Power Bandwidth 25ºC III 85 MHz Input Referred Noise 25ºC III 75 µV

Reference Voltage Error

REFT12-REFB12 (1 V) Full I –200 ±16 +200 mV

Dynamic Performance (A ADC Sample Clock = OSCIN

Signal-to-Noise and Distortion (SINAD) Full I 63.2 65.9 dB Effective Number of Bits (ENOBs) Full I 10.2 10.7 Bits Signal-to-Noise Ratio (SNR) Full I 63.7 66.2 dB Total Harmonic Distortion (THD) Full I –79.1 –68.3 dB Spurious-Free Dynamic Range (SFDR) Full I 72.5 79.3 dB

ADC Sample Clock = PLL

Signal-to-Noise and Distortion (SINAD) Full II 62.0 64.6 dB Effective Number of Bits (ENOBs) Full II 10.0 10.4 Bits Signal-to-Noise Ratio (SNR) Full II 62.5 64.8 dB Total Harmonic Distortion (THD) Full II –78 –67.8 dB

Spurious-Free Dynamic Range (SFDR) Full II 72.5 79.3 dB Dynamic Performance (A ADC Sample Clock = OSCIN

Signal-to-Noise and Distortion (SINAD) Full II 61.1 63.1 dB

Effective Number of Bits (ENOB) Full II 9.9 10.2 Bits

Signal-to-Noise Ratio (SNR) Full II 61.5 63.3 dB

Total Harmonic Distortion (THD) Full II –77 –67.9 dB

Spurious-Free Dynamic Range (SFDR) Full II 69.9 79.6 dB Differential Phase 25ºC III <0.1 Degrees Differential Gain 25ºC III <1 LSB

CHANNEL-TO-CHANNEL ISOLATION

Tx DAC-to-ADC Isolation

(5 MHz Analog Output)

Isolation between Tx and 8-Bit ADCs 25ºC III 80 dB

Isolation between Tx and 12-Bit ADCs 25ºC III 90 dB ADC-to-ADC Isolation

= –0.5 dBFS, f = 5 MHz)

Isolation between I/Q in and IF12 25ºC III 70 dB

Isolation between Q and I Inputs 25ºC III 65 dB

TIMING CHARACTERISTICS (10 pF Load)

Wake-Up Time N/A N/A 200 t Minimum RESET Pulsewidth Low (t Digital Output Rise/Fall Time Full II 2.8 4 ns Tx/Rx Interface

MCLK Frequency (f

TxSYNC/TxIQ Setup Time (t

TxSYNC/TxIQ Hold Time (t

MCLK Rising Edge to RxSYNC/RxIQ/IF Valid

Delay (t

) Full II 0 1.0 ns

OSCOUT Rising or Falling Edge to RxSYNC/

RxIQ/IF Valid Delay (t

OSCOUT Edge to MCLK Falling Edge (tEE) Full II –1.0 +1.0 ns

= –0.5 dBFS, f = 5 MHz)

= –0.5 dBFS, f = 50 MHz)

) N/A N/A 5 t

) Full II 66 MHz

MCLK

) Full II 3 ns

) Full II T

/4 – 2.0 T

OSC

/4 + 3.0 ns

MCLK

Cycles

REV. A

–3–

AD9877

SPECIFICATIONS

(continued)

Test

Parameter Temp Level Min Typ Max Unit

Serial Control Bus (continued)

Maximum SCLK Frequency (f Minimum Clock Pulsewidth High (t Minimum Clock Pulsewidth Low (t

) Full II 15 MHz

SCLK

) Full II 30 ns

PWH

) Full II 30 ns

PWL

Maximum Clock Rise/Fall Time Full II 1 µs Minimum Data/Chip-Select Setup Time (t Minimum Data Hold Time (t

) Full II 0 ns

) Full II 25 ns

Maximum Data Valid Time (tDV) Full II 30 ns

CMOS LOGIC INPUTS

Logic “1” Voltage 25ºC II DRVDD – 0.7 V Logic “0” Voltage 25ºC II 0.4 V Logic “1” Current 25ºC II 12 µA Logic “0” Current 25ºC II 12 µA Input Capacitance 25ºC III 3 pF

CMOS LOGIC OUTPUTS (1 mA Load)

Logic “1” Voltage 25ºC II DRVDD – 0.6 V Logic “0” Voltage 25ºC II 0.4 V

POWER SUPPLY

Supply Current, IS (Full Operation) 25oCII 313 355 mA

Analog Supply Current I Digital Supply Current I

Supply Current, I

25ºC III 85 mA 25ºC III 228 mA

Standby (PWRDN Pin Active) 25ºC II 104 113 mA Full Power-Down (Register 02h = 0xF9) 25ºC III 10 mA Power-Down Tx Path (Register 2 = 0x20) 25ºC III 60 mA Power-Down Rx Paths (Register 2 = 0x19) 25ºC III 265 mA Reset (RESET Pin Active) 25ºC III 85 mA

Power Supply Rejection (Differential Signal)

Tx DAC 25ºC III <0.25 % FS 8-Bit ADC 25ºC III <0.004 % FS 12-Bit ADC 25ºC III <0.0004 % FS

Specifications subject to change without notice.

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REV. A

AD9877

ABSOLUTE MAXIMUM RATINGS

Power Supply (V

AVDD

, V

DVDD

, V

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA

Digital Inputs . . . . . . . . . . . . . . . –0.3 V to DRVDD + 0.3 V

Analog Inputs . . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V

Operating Temperature . . . . . . . . . . . . . . . . . –40ºC to +85ºC

Maximum Junction Temperature . . . . . . . . . . . . . . . . 150ºC

Storage Temperature . . . . . . . . . . . . . . . . . . –65ºC to +150ºC

Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . 300ºC

*Absolute maximum ratings are limiting values, to be applied individually, and

beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability.

) . . . . . . . . . . . . 3.9 V

DRVDD

EXPLANATION OF TEST LEVELS

I Devices are 100% production tested at 25ºC and guaranteed

by design and characterization testing for industrial operating temperature range (–40ºC to +85ºC).

II Parameter is guaranteed by design and/or characterization

testing.

III Parameter is a typical value only.

N/A Test level definition is not applicable.

THERMAL CHARACTERISTICS Thermal Resistance

100-Lead MQFP

␪

= 40.5ºC/W

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

AD9877ABS –40ºC to +85ºC 100-MQFP S-100C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9877 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. A

–5–

AD9877

AVDD

DRGND

DRVDD

IF(11)

IF(10)

IF(9)

IF(8)

IF(7)

IF(6)

IF(5)

IF(4)

IF(3)

IF(2)

IF(1)

IF(0)

RxIQ(3)

RxIQ(2)

RxIQ(1)

RxIQ(0)

RxSYNC

DRGND

DRVDD

MCLK

DVDD

DGND

TxSYNC

TxIQ(5)

TxIQ(4)

TxIQ(3)

TxIQ(2)

IF12–

IF12+

AGND

1009998

313233 34 353637 38 39

TxIQ(1)

TxIQ(0)

97 96

DVDD

AGND

95 94

DGND

PROFILE(1)

PIN CONFIGURATION

REFB12

REFT12

AVDD

RESET

PROFILE(0)

AVDD

91 90

AD9877

TOP VIEW

100-Lead MQFP

DVDD

DGND

AGND

41 42

DGND

SCLK

AGND

44 45

SDIO

AVDD

SDO

REFT8

46 47

DGNDTx

REFB8

AVDD

848382

PWRDN

DVDDTx

AGND

REFIO

Q IN+

FSADJ

Q IN–

AGNDTx

AGNDIQ

I IN+

I IN–

AGNDIQ

AVDDIQ

DRVDD

OSCOUT

DRGND

DGNDSD

SDELTA0

SDELTA1

DVDDSD

CA_EN

CA_DATA

CA_CLK

DVDDOSC

OSCIN

XTAL

DGNDOSC

AGNDPLL

PLLFILT

AVDDPLL

DVDDPLL

DGNDPLL

AVDDTx

Tx+

Tx–

NC = NO CONNECT

–6–

REV. A

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Pin Function

1, 84, 87, AVDD 12-Bit ADC Analog 3.3 V Supply 92, 95 2, 21, 70 DRGND Pin Driver Digital Ground 3, 22, 72 DRVDD Pin Driver Digital 3.3 V Supply 25, 34, DGND Digital Ground 39, 40 24, 33, DVDD Digital 3.3 V Supply 38 45 DGNDTx Tx Path Digital Ground 46 DVDDTx Tx Path Digital 3.3 V Supply 50 AGNDTx Tx Path Analog Ground 53 AVDDTx Tx Path Analog 3.3 V Supply 54 DGNDPLL PLL Digital Ground 55 DVDDPLL PLL Digital 3.3 V Supply 56 AVDDPLL PLL Analog 3.3 V Supply 58 AGNDPLL PLL Analog Ground 59 DGNDOSC Oscillator Digital Ground 62 DVDDOSC Oscillator Digital 3.3 V Supply 66 DVDDSD Sigma-Delta Digital 3.3 V Supply 69 DGNDSD Sigma-Delta Digital Ground 73 AVDDIQ 8-Bit ADC Analog 3.3 V Supply 74, 77, AGNDIQ 8-Bit ADC Analog Ground 80 83, 88, AGND 12-Bit ADC Analog Ground 91, 96, 99 4:15 IF[11:0] 12-Bit ADC Digital Output 16:19 RxIQ[3:0] Muxed I and Q ADC Output 20 RxSYNC Sync Output, IF, I, and Q ADCs 23 MCLK Master Clock Output

AD9877

Pin No. Mnemonic Pin Function

26 TxSYNC Sync Input for Transmit Port 27:32 TxIQ[5:0] Digital Input for Transmit Port 35, 36 PROFILE[1:0] Profile Selection Inputs 37 RESET Chip Reset Input 41 SCLK SPORT Clock 42 CS SPORT Chip Select 43 SDIO SPORT Data I/O 44 SDO SPORT Data Output 47 PWRDN Power-Down Transmit Path 48 REFIO TxDAC Decoupling (to AGND) 49 FSADJ DAC Output Adjust (External Res.) 51, 52 Tx–, Tx+ Tx Path Complementary Outputs 57 PLLFILT PLL Loop Filter Connection 60 XTAL Crystal Oscillator Inv. Output 61 OSCIN Oscillator Clock Input 63 CA_CLK Serial Clock to Cable Driver 64 CA_DATA Serial Data to Cable Driver 65 CA_EN Serial Enable to Cable Driver 67 SDELTA1 Sigma-Delta Output Stream 1 68 SDELTA0 Sigma-Delta Output Stream 0 71 OSCOUT Oscillator Clock Output 75, 76 NC No Connect (Leave Floating) 78, 79 I IN–, I IN+ Differential Input to I ADC 81, 82 Q IN–, Q IN+ Differential Input to Q ADC 85 REFB8 8-Bit ADC Decoupling Node 86 REFT8 8-Bit ADC Decoupling Node 89, 90 NC No Connect (Leave Floating) 93 REFB12 12-Bit ADC Decoupling Node 94 REFT12 12-Bit ADC Decoupling Node 97, 98 IF12–, IF12+ Differential Input to IF ADC 100 NC No Connect (Leave Floating)

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AD9877

DEFINITIONS OF SPECIFICATIONS APERTURE DELAY

The aperture delay is a measure of the sample-and-hold amplifier (SHA) performance and specifies the time delay between the rising edge of the sampling clock input to when the input signal is held for conversion.

APERTURE UNCERTAINTY (JITTER)

Aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the ADC.

CHANNEL-TO-CHANNEL ISOLATION (CROSSTALK)

In an ideal multichannel system, the signal in one channel will not influence the signal level of another channel. The channel-to-channel isolation specification is a measure of the change that occurs to a grounded channel as a full-scale signal is applied to another channel.

DIFFERENTIAL NONLINEARITY ERROR (DNL, NO MISSING CODES)

An ideal converter exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 10-bit resolution indicates that all 1,024 codes, respectively, must be present over all operating ranges.

EFFECTIVE NUMBER OF BITS (ENOB)

For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula:

N SINAD dB=−

()

It is possible to get a measure of performance expressed as N, the effective number of bits. Thus, the effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD.

GAIN ERROR

The first code transition should occur at an analog value one-half LSB above full scale. The last transition should occur for an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual difference between the first and last code transitions and the ideal difference between the first and last code transitions.

INPUT REFERRED NOISE

The rms output noise is measured using histogram techniques. The ADC output code’s standard deviation is calculated in LSB and converted to an equivalent voltage. This results in a noise figure that can be directly referred to the input of the MxFE.

INTEGRAL NONLINEARITY ERROR (INL)

Linearity error refers to the deviation of each individual code from a line drawn from the negative full scale through the positive full scale. The point used as the negative full scale occurs 1/2 LSB before the first code transition. The positive full scale is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line.

176 602..

OFFSET ERROR

First transition should occur for an analog value 1/2 LSB above –FS. Offset error is defined as the deviation of the actual transition from that point.

OUTPUT COMPLIANCE RANGE

The range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance.

PHASE NOISE

Single sideband phase noise power is specified relative to the carrier (dBc/Hz) at a given frequency offset (1 kHz) from the carrier. Phase noise can be measured directly in single-tone transmit mode with a spectrum analyzer that supports noise marker measurements. It detects the relative power between the carrier and the offset (1 kHz) sideband noise and takes the resolution bandwidth (rbw) into account by subtracting 10 log(rbw). It also adds a correction factor that compensates for the implementation of the resolution bandwidth, log display, and detector characteristic.

PIPELINE DELAY (LATENCY)

The number of clock cycles between conversion initiation and the associated output data being made available.

POWER SUPPLY REJECTION

Power supply rejection specifies the converter’s maximum full-scale change when the supplies are varied from nominal to minimum and maximum specified voltages.

SIGNAL-TO-NOISE AND DISTORTION (SINAD) RATIO

SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels.

SIGNAL-TO-NOISE RATIO (SNR)

SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels.

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

The difference, in dB, between the rms amplitude of the DAC’s output signal (or ADC’s input signal) and the peak spurious signal over the specified bandwidth (Nyquist bandwidth unless otherwise noted).

TOTAL HARMONIC DISTORTION (THD)

THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels.

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AD9877

Table I. Register Map*

Address Default (Hex) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex) Type

00 SDIO LSB First RESET OSCIN Multiplier M [4] 08 rw

Bidirectional

01 PLL Lock SYSCLK MCLK Divider R [5:0] 00 rw

Detect Divider N = 3

(N = 4 Default)

02 Power-Down Power-Down Power-Down Power-Down Power-Down Power-Down 00 rw

PLL DAC Tx Digital Tx 12-Bit ADC 12-Bit ADC 0 0 8-Bit ADC

Reference

03 Sigma-Delta Output [0] Control Word [3:0] LSB 0 0 0

04 Flag [0] Sigma-Delta Output 0 Control Word [11:4] MSB 00 rw ⌺-⌬

05 Sigma-Delta Output [0] Control Word [3:0] LSB 0 0 0

06 Flag [1] Sigma-Delta Output 1 Control Word [11:4] MSB 00 rw ⌺-⌬

07 0000000000rw Tx

08 ADC Clock 0 0 Power-Down 0 0 0 0 80 rw ADC

Select RxSYNC and

8-Bit ADC CLOCK

09 0000000000rw

0A 0000000000r

0B 0000000000rw

0C 0 0 0 1 Version [3:0] 10 r

0D Tx Frequency Tuning Tx Frequency Tuning Tx Frequency Tuning Tx Frequency Tuning 00 rw Tx

Word Profile 3 LSBs [1:0] Word Profile 2 LSBs [1:0] Word Profile 1 LSB [1:0] Word Profile 3 LSBs [1:0]

0E 0 0 0 0 DAC Gain Control [3:0] 00 rw Tx

0F 0 0 Profile Select [1:0] CA Interface 0 Spectral Single-Tone 00 rw Tx

Mode Select Inversion Tx Tx Mode

10 Tx Frequency Turning Word Profile 0 [9:2] 00 rw Tx

11 Tx Frequency Turning Word Profile 0 [17:10] 00 rw Tx

12 Tx Frequency Turning Word Profile 0 [25:18] 00 rw Tx

13 CA Interface Transmit Word Control Profile 0 [7:4] DAC Gain Control Profile 0 [3:0] 00 rw Tx

14 Tx Frequency Turning Word Profile 1 [9:2] 00 rw Tx

15 Tx Frequency Turning Word Profile 1 [9:2] 00 rw Tx

16 Tx Frequency Turning Word Profile 1 [9:2] 00 rw Tx

17 CA Interface Transmit Word Control Profile 1 [7:4] DAC Gain Control Profile 1 [3:0] 00 rw Tx

18 Tx Frequency Turning Word Profile 2 [9:2] 00 rw Tx

19 Tx Frequency Turning Word Profile 2 [9:2] 00 rw Tx

1A Tx Frequency Turning Word Profile 2 [9:2] 00 rw Tx

1B CA Interface Transmit Word Control Profile 2 [7:4] DAC Gain Control Profile 2 [3:0] 00 rw Tx

1C Tx Frequency Turning Word Profile 3 [9:2] 00 rw Tx

1D Tx Frequency Turning Word Profile 3 [9:2] 00 rw Tx

1E Tx Frequency Turning Word Profile 3 [9:2] 00 rw Tx

1F CA Interface Transmit Word Control Profile 3 [7:4] DAC Gain Control Profile 3 [3:0] 00 rw Tx

*Register bits denoted with “0” must be programmed with a “0” every time that register is written.

Flag [0] Enable

Flag [1] Enable

00 rw ⌺-⌬

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