ANALOG DEVICES AD9877 Service Manual
Mixed-Signal Front End
FEATURES
Low cost 3.3 V CMOS MxFE™ for
MCNS-DOCSIS-, DVB-, DAVIC-compliant
set-top box and cable modem applications
232 MHz quadrature digital upconverter
12-bit direct IF DAC (TxDAC+®)
Up to 65 MHz carrier frequency DDS
Programmable sampling clock rates
Selectable interpolation filter
Analog Tx output level adjust
12-bit, 33 MSPS direct IF ADC
Dual 8-bit, 16.5 MSPS sampling IQ ADCs
Two 12-bit Σ-Δ auxiliary DACs
Direct interface to AD8321/AD8325 or
AD8322/AD8327 PGA cable driver
APPLICATIONS
Cable modems
Set-top boxes
Wireless modems
Set-Top Box, Cable Modem
AD9877
FUNCTIONAL BLOCK DIAGRAM
COS
SIN
Figure 1.
12
DAC
12
Σ-Δ
12
Σ-Δ
8
ADC
8
ADC
12
ADC
Tx
3
CA
SDELTA0
SDELTA1
REFCLK
I IN
Q IN
IF IN
02716-001
Tx DATA
SPORT
PROFILE
RxIQ DATA
RxIF DATA
Tx
PLL
4
2
Rx
AD9877
INTER-
POLATOR
FILTER
DDS
CONTROL FUNCTIONS
GENERAL DESCRIPTION
The AD9877 is a single-supply set-top box and cable modem
mixed-signal front end. The device contains a transmit path
interpolation filter, complete quadrature digital upconverter,
and transmit DAC. The receive path contains a 12-bit ADC and
dual 8-bit ADCs. All internally required clocks and an output
system clock are generated by the phase-locked loop (PLL) from
a single crystal or clock input.
The transmit path interpolation filter provides upsampling
factors of 12× or 16× with an output signal bandwidth as high
as 5.8 MHz. Carrier frequencies up to 65 MHz with 26 bits of
frequency tuning resolution can be generated by the direct
digital synthesizer (DDS). The transmit DAC resolution is 12 bits
and can run at sampling rates as high as 232 MSPS. Analog
output scaling from 0 dB to 7.5 dB in 0.5 dB steps is available to
preserve SNR when reduced output levels are required.
The 12-bit ADC has excellent undersampling performance,
allowing it to typically deliver better than 10 ENOBs with IF
inputs up to 70 MHz. The 12-bit IF ADC can sample at a rate
up to 33 MHz, allowing it to process wideband signal inputs.
Two programmable Σ- DACs are available and can be used to
control external components, such as variable gain amplifiers
(VGAs) or voltage-controlled tuners.
The AD9877 integrates a CA port that enables a host processor
to control the AD8321/AD8325 or AD8322/AD8327
programmable gain amplifier (PGA) cable drivers via the
MxFE SPORT.
The AD9877 is available in a 100-lead MQFP package. It offers
enhanced receive path undersampling performance and lower
cost compared to the pin-compatible AD9873. The AD9877 is
specified over the extended industrial (−40°C to +85°C)
temperature range.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
AD9877
TABLE OF CONTENTS
Specifications..................................................................................... 4
MSB/LSB Transfers .................................................................... 22
Absolute Maximum Ratings............................................................ 7
Explanation of Test Levels........................................................... 7
Thermal Characteristics .............................................................. 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ........................................... 10
Te r mi n ol o g y .................................................................................... 12
Theory of Operation ...................................................................... 13
Transmi t S ect i on ......................................................................... 13
Clock and Oscillator Circuitry ................................................. 14
Programmable Clock Output REFCLK................................... 15
Reset and Transmit Power-Down ............................................16
Σ- Outputs ................................................................................17
Register Map and Bit Definitions................................................. 18
Register 0x00—Initialization .................................................... 19
Register 0x01—Clock Configuration....................................... 19
Register 0x02—Power-Down.................................................... 19
Register 0x03–0x06—Σ- Control Words .............................. 19
Register 0x08—ADC Clock Configuration ............................ 20
Register 0x0C—Die Revision.................................................... 20
Register 0x0D—Tx Frequency Tuning Words LSBs.............. 20
Register 0x0E—DAC Gain Control ......................................... 20
Register 0x0F—Tx Path Configuration................................... 20
Registers 0x10–0x1F—Burst Parameter.................................. 20
Serial Interface for Register Control............................................ 22
General Operation of the Serial Interface............................... 22
Notes on Serial Port Operation ................................................ 23
Transmi t P a t h (Tx) ......................................................................... 24
Transmi t T i ming ......................................................................... 24
Data Assembler........................................................................... 24
Half-Band Filters (HBFs).......................................................... 24
Cascaded Integrator-Comb (CIC) Filter................................. 24
Combined Filter Response........................................................ 25
Tx Signal Level Considerations................................................ 27
Tx Throughput and Latency..................................................... 27
Digital-to-Analog Converter .................................................... 27
Programming the AD8321/AD8325 or AD8322/AD8327 Cable
Driver Amplifier Gain Control..................................................... 29
Receive Path (Rx) ........................................................................... 30
ADC Theory of Operation........................................................ 30
Receive Timing........................................................................... 30
Driving the Analog Inputs ........................................................ 30
Op Amp Selection Guide .......................................................... 31
ADC Differential Inputs............................................................ 31
ADC Voltage References ........................................................... 32
PCB Design Considerations.......................................................... 33
Component Placement.............................................................. 33
Power Planes and Decoupling .................................................. 33
Ground Planes ............................................................................ 33
Signal Routing............................................................................. 34
Outline Dimensions ....................................................................... 35
Ordering Guide .......................................................................... 35
Instruction Byte ..........................................................................22
Serial Interface Port Pin Description....................................... 22
Rev. B | Page 2 of 36
AD9877
REVISION HISTORY
5/05—Rev. A to Rev. B
Updated Format.................................................................. Universal
Changed OSCOUT to REFCLK....................................... Universal
Changed REF CLK to REFCLK........................................ Universal
Changes to Specifications.................................................................4
Changes to Figure 24 ......................................................................23
Updated Outline Dimensions........................................................35
Changes to Ordering Guide...........................................................35
7/02—Rev. 0 to Rev. A
Edits to ORDERING GUIDE..........................................................5
Edits to RESET AND TRANSMIT POWER-DOWN section..17
Revision 0: Initial Version
Rev. B | Page 3 of 36
AD9877
SPECIFICATIONS
VAS = 3.3 V ± 5%, VDS = 3.3 V ± 10%, f
derived from PLL (f
MCLK
), R
= 4.02 kΩ, maximum fine gain, 75 Ω DAC load.
SET
Table 1.
Parameter Temp
SYSTEM CLOCK DAC SAMPLING, f
SYSCLK
Frequency Range (N = 4) Full II 232 MHz
Frequency Range (N = 3) Full II 177 MHz
OSCIN and XTAL CHARACTERISTICS
Frequency Range Full II 3 33 MHz
Duty Cycle 25°C II 35 50 65 %
Input Impedance 25°C III 100||3 MΩ||pF
MCLK JITTER
Cycle to Cycle (f
derived from PLL) 25°C III 6 ps rms
MCLK
Tx DAC CHARACTERISTICS
Resolution N/A N/A 12 Bits
Full-Scale Output Current Full II 4 10 20 mA
Gain Error (using internal reference) Full I −2.5 −1 +2.5 % FS
Offset Error 25°C I ±1.0 % FS
Reference Voltage (REFIO Level) 25°C I 1.18 1.23 1.28 V
Differential Nonlinearity (DNL) 25°C III ±2.5 LSB
Integral Nonlinearity (INL) 25°C III ±8 LSB
Output Capacitance 25°C III 5 pF
Phase Noise @ 1 kHz Offset, 42 MHz Carrier 25°C III −110 dBc/Hz
Output Voltage Compliance Range Full II −0.5 +1.5 V
Wideband SFDR
5 MHz Analog Out, I
65 MHz Analog Out, I
= 10 mA Full II 48 55 dBc
OUT
= 10 mA Full II 48 51 dBc
OUT
Narrow-Band SFDR (±1 MHz Window)
65 MHz Analog Out, I
= 10 mA Full II 53 69 dBc
OUT
Tx MODULATOR CHARACTERISTICS
I/Q Offset Full II 50 55 dB
Pass-Band Amplitude Ripple (f < f
Pass-Band Amplitude Ripple (f < f
Stop-Band Response (f > f
× 3/4) Full II −63 dB
IQCLK
Tx GAIN CONTROL
Gain Step Size 25°C III 0.5 dB
Gain Step Error 25°C III 0.05 dB
Settling Time, 1% (Full-Scale Step) 25°C III 1.8 μs
8-BIT ADC CHARACTERISTICS
Resolution N/A N/A 8 Bits
Conversion Rate Full II 16.5 MHz
Pipeline Delay N/A N/A 3.5 ADC cycles
Offset Matching Between I and Q ADCs ±8.0 LSBs
Gain Matching Between I and Q ADCs ±2.0 LSBs
Analog Input
Input Voltage Range Full II 1 Vppd
Differential Input Impedance 25°C III 4||2 kΩ||pF
Full Power Bandwidth 25°C III 90 MHz
Input Referred Noise 25°C III 600 μV
= 27 MHz, f
OSCIN
= 216 MHz, f
SYSCLK
= 54 MHz (M = 8 and N = 4). ADC sample frequencies
MCLK
Test
Level
Min Typ Max Unit
/8) Full II ±0.1 dB
IQCLK
/4) Full II ±0.5 dB
IQCLK
Rev. B | Page 4 of 36
AD9877
Test
Parameter Temp
Dynamic Performance (AIN = −0.5 dBFS, f = 5 MHz)
Signal-to-Noise and Distortion (SINAD) 25°C I 40.8 47.3 dB
Effective Number of Bits (ENOB) 25°C I 6.5 7.6 Bits
Total Harmonic Distortion (THD) 25°C I −60.1 −50.0 dB
Spurious-Free Dynamic Range (SFDR) 25°C I 52.0 63.0 dB
Reference Voltage Error
REFT8 to REFB8 (0.5 V) 25°C I −100 ±10 +100 mV
12-BIT ADC CHARACTERISTICS
Resolution N/A N/A 12 Bits
Conversion Rate Full II 33 MHz
Pipeline Delay N/A N/A 5.5 ADC cycles
Analog Input
Input Voltage Range Full III 2 Vppd
Differential Input Impedance 25°C III 4||2 kΩ||pF
Aperture Delay 25°C III 2.0 ns
Aperture Uncertainty (Jitter) 25°C III 1.2 ps rms
Full-Power Bandwidth 25°C III 85 MHz
Input Referred Noise 25°C III 75 μV
Reference Voltage Error
REFT12 to REFB12 (1 V) 25°C I −200 ±16 ±200 mV
Dynamic Performance (AIN = −0.5 dBFS, f = 5 MHz)
ADC Sample Clock = OSCIN
Signal-to-Noise and Distortion (SINAD) Full II 63.2 65.9 dB
Effective Number of Bits (ENOBs) Full II 10.2 10.7 Bits
Signal-to-Noise Ratio (SNR) Full II 63.7 66.2 dB
Total Harmonic Distortion (THD) Full II −79.1 −68.3 dB
Spurious-Free Dynamic Range (SFDR) Full II 72.5 79.3 dB
ADC Sample Clock = PLL
Signal-to-Noise and Distortion (SINAD) Full II 62.0 64.6 dB
Effective Number of Bits (ENOBs) Full II 10.0 10.4 Bits
Signal-to-Noise Ratio (SNR) Full II 62.5 64.8 dB
Total Harmonic Distortion (THD) Full II −78 −67.8 dB
Spurious-Free Dynamic Range (SFDR) Full II 71.0 78.9 dB
Dynamic Performance (AIN = −0.5 dBFS, f = 50 MHz)
ADC Sample Clock = OSCIN
Signal-to-Noise and Distortion (SINAD) Full II 61.1 63.1 dB
Effective Number of Bits (ENOB) Full II 9.9 10.2 Bits
Signal-to-Noise Ratio (SNR) Full II 61.5 63.3 dB
Total Harmonic Distortion (THD) Full II −77 −67.9 dB
Spurious-Free Dynamic Range (SFDR) Full II 69.9 79.6 dB
Differential Phase 25°C III <0.1 Degrees
Differential Gain 25°C III <1 LSB
CHANNEL-TO-CHANNEL ISOLATION
Tx DAC-to-ADC Isolation (5 MHz Analog Output)
Isolation Between Tx and 8-Bit ADCs 25°C III 80 dB
Isolation Between Tx and 12-Bit ADCs 25°C III 90 dB
ADC-to-ADC Isolation
(AIN = −0.5 dBFS, f = 5 MHz)
Isolation Between I/Q in and IF12 25°C III 70 dB
Isolation Between Q and I Inputs 25°C III 65 dB
Level Min Typ Max Unit
Rev. B | Page 5 of 36
AD9877
Test
Parameter Temp
TIMING CHARACTERISTICS (10 pF Load)
Wake-Up Time N/A N/A 200 t
Minimum RESET Pulse Width Low (tRL)
N/A N/A 5 t
Digital Output Rise/Fall Time Full II 2.8 4 ns
Tx/Rx Interface
MCLK Frequency (f
) Full II 66 MHz
MCLK
TxSYNC/TxIQ Setup Time (tSU) Full II 3 ns
TxSYNC/TxIQ Hold Time (tHD) Full II 3 ns
MCLK Rising Edge to RxSYNC/RxIQ/IF Valid Delay (tMD) Full II 0 1.0 ns
REFCLK Rising or Falling Edge to RxSYNC/RxIQ/IF Valid
Delay (t
)
OD
Full II T
REFCLK Edge to MCLK Falling Edge (tEE) Full II −1.0 +1.0 ns
Serial Control Bus
Maximum SCLK Frequency (f
Minimum Clock Pulse Width High (t
Minimum Clock Pulse Width Low (t
) Full II 15 MHz
SCLK
) Full II 30 ns
PWH
) Full II 30 ns
PWL
Maximum Clock Rise/Fall Full II 1 μs
Minimum Data/Chip-Select Setup Time (tDS) Full II 25 ns
Minimum Data Hold Time (tDH) Full II 0 ns
Maximum Data Valid Time (tDV) Full II 30 ns
CMOS LOGIC INPUTS
Logic 1 Voltage 25°C II DRVDD − 0.7 V
Logic 0 Voltage 25°C II 0.4 V
Logic 1 Current 25°C II 12 μA
Logic 0 Current 25°C II 12 μA
Input Capacitance 25°C III 3 pF
CMOS LOGIC OUTPUTS (1 mA Load)
Logic 1 Voltage 25°C II DRVDD − 0.6 V
Logic 0 Voltage 25°C II 0.4 V
POWER SUPPLY
Supply Current, IS (Full Operation) 25°C II 233 272 mA
Analog Supply Current, I
Digital Supply Current, I
Supply Current, I
S
Standby (PWRDN Pin Active)
AS
DS
25°C III 85 mA
25°C III 228 mA
25°C I 104 113 mA
Full Power-Down (Register 0x02 = 0xF9) 25°C III 10 mA
Power-Down Tx Path (Register 0x02 = 0x20) 25°C III 60 mA
Power-Down Rx Path (Register 0x02 = 0x19) 25°C III 265 mA
Reset (RESET Pin Active)
25°C III 85 mA
Power Supply Rejection (Differential Signal)
Tx DAC 25°C III <0.25 % FS
8-Bit ADC 25°C III <0.004 % FS
12-Bit ADC 25°C III <0.0004 % FS
Level Min Typ Max Unit
cycles
MCLK
cycles
MCLK
/4 − 2.0 T
OSC
/4 + 3.0 ns
OSC
Rev. B | Page 6 of 36
AD9877
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameters Ratings
Power Supply (V
Digital Output Current 5 mA
Digital Inputs −0.3 V to DRVDD + 0.3 V
Analog Inputs −0.3 V to AVDD + 0.3 V
Operating Temperature −40°C to +85°C
Maximum Junction Temperature 150°C
Storage Temperature −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
AVDD
, V
DVDD
, V
) 3.9 V
DRVDD
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
EXPLANATION OF TEST LEVELS
I Devices are 100% production tested at 25°C and
guaranteed by design and characterization testing for
industrial operating temperature range (−40°C to
+85°C).
II Parameter is guaranteed by design and/or
characterization testing.
III Parameter is a typical value only.
N/A Test level definition is not applicable.
THERMAL CHARACTERISTICS
Thermal Resistance
100-Lead MQFP
θ
= 40.5°C/W
JA
Rev. B | Page 7 of 36
AD9877
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AVDD
DRGND
DRVDD
IF(11)
IF(10)
IF(9)
IF(8)
IF(7)
IF(6)
IF(5)
IF(4)
IF(3)
IF(2)
IF(1)
IF(0)
RxIQ(3)
RxIQ(2)
RxIQ(1)
RxIQ(0)
RxSYNC
DRGND
DRVDD
MCLK
DVDD
DGND
TxSYNC
TxIQ(5)
TxIQ(4)
TxIQ(3)
TxIQ(2)
NC
100
1
PIN 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
IF12+
AGND
99
98
IF12–
97
AGND
AVDD
969594
REFT12
REFB12
93
(Not to Scale)
AVDD
AGNDNCNC
929190
AD9877
TOP VIEW
REFB8
REFT8
AGND
AVDD
89888786858483
AVDD
AGND
Q IN+
82
Q IN–
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
AGNDIQ
I IN+
I IN–
AGNDIQ
NC
NC
AGNDIQ
AVDDIQ
DRVDD
REFCLK
DRGND
DGNDSD
SDELTA0
SDELTA1
DVDDSD
CA_EN
CA_DATA
CA_CLK
DVDDOSC
OSCIN
XTAL
DGNDOSC
AGNDPLL
PLLFILT
AVDDPLL
DVDDPLL
DGNDPLL
AVDDTx
Tx+
Tx–
31
32
TxIQ(1)
TxIQ(0)
NC = NO CONNECT
33
DVDD
34
DGND
SCLK
42
CS
44
SDO
SDIO
35
36
38
39
37
DVDD
DGND40DGND
RESET
PROFILE(1)
PROFILE(0)
45
46
DVDDTx
DGNDTx
47
PWRDN
48
REFIO
49
FSADJ
50
AGNDTx
41
43
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1, 84, 87, 92, 95 AVDD 12-Bit ADC Analog 3.3 V Supply.
2, 21, 70 DRGND Pin Driver Digital Ground.
3, 22, 72 DRVDD Pin Driver Digital 3.3 V Supply.
25, 34, 39, 40 DGND Digital Ground.
24, 33, 38 DVDD Digital 3.3 V Supply.
45 DGNDTx Tx Path Digital Ground.
46 DVDDTx Tx Path Digital 3.3 V Supply.
50 AGNDTx Tx Path Analog Ground.
53 AVDDTx Tx Path Analog 3.3 V Supply.
54 DGNDPLL PLL Digital Ground.
55 DVDDPLL PLL Digital 3.3 V Supply.
56 AVDDPLL PLL Analog 3.3 V Supply.
58 AGNDPLL PLL Analog Ground.
Rev. B | Page 8 of 36
02716-002
AD9877
Pin No. Mnemonic Description
59 DGNDOSC Oscillator Digital Ground.
62 DVDDOSC Oscillator Digital 3.3 V Supply.
66 DVDDSD Σ-Δ Digital 3.3 V Supply.
69 DGNDSD Σ-Δ Digital Ground.
73 AVDDIQ 8-Bit ADC Analog 3.3 V Supply.
74, 77, 80 AGNDIQ 8-Bit ADC Analog Ground.
83, 88, 91, 96, 99 AGND 12-Bit ADC Analog Ground.
4:15 IF[11:0] 12-Bit ADC Digital Output.
16:19 RxIQ[3:0] Muxed I and Q ADC Output.
20 RxSYNC Sync Output, IF, I, and Q ADCs.
23 MCLK Master Clock Output.
26 TxSYNC Sync Input for Transmit Port.
27:32 TxIQ[5:0] Digital Input for Transmit Port.
35, 36 PROFILE[1:0] Profile Selection Inputs.
37
41 SCLK SPORT Clock.
42
43 SDIO SPORT Data I/O.
44 SDO SPORT Data Output.
47
48 REFIO TxDAC Decoupling (to AGND).
49 FSADJ DAC Output Adjust (External Resistor).
51, 52 Tx−, Tx+ Tx Path Complementary Outputs.
57 PLLFILT PLL Loop Filter Connection.
60 XTAL Crystal Oscillator Inverse Output.
61 OSCIN Oscillator Clock Input.
63 CA_CLK Serial Clock to Cable Driver.
64 CA_DATA Serial Data to Cable Driver.
65
67 SDELTA1 Σ-Δ Output Stream1.
68 SDELTA0 Σ-Δ Output Stream0.
71 REFCLK Programmable Reference Clock Output.
75, 76, 89, 90, 100 NC No Connect (Leave Floating).
78, 79 I IN−, I IN+ Differential Input to I ADC.
81, 82 Q IN−, Q IN+ Differential Input to Q ADC.
85 REFB8 8-Bit ADC Decoupling Node.
86 REFT8 8-Bit ADC Decoupling Node.
93 REFB12 12-Bit ADC Decoupling Node.
94 REFT12 12-Bit ADC Decoupling Node.
97, 98 IF12−, IF12+ Differential Input to IF ADC.
RESET
CS
PWRDN
CA_EN
Chip Reset Input.
SPORT Chip Select.
Power-Down Transmit Path.
Serial Enable to Cable Driver.
Rev. B | Page 9 of 36
AD9877
TYPICAL PERFORMANCE CHARACTERISTICS
VAS = 3.3 V, VDS = 3.3 V, f
f
, R
OSCIN
= 4.02 kΩ (I
SET
TYPICAL POWER CONSUMPTION CHARACTERISTICS
Transmitted 20 MHz single tone, unless otherwise noted.
340
320
300
280
260
POWER
240
220
200
180
120 240140 160 180 200 220
Figure 3. Power Consumption vs. Clock Speed, f
DUAL SIDEBAND TRANSMIT SPECTRUM
See
Tabl e 11 for dual-tone generation.
0
–10
–20
–30
–40
–50
MAGNITUDE (dB)
–60
–70
–80
–90
022 6 10 12 14
48 1816
Figure 5. Dual Sideband Spectral Plot, f
= 4.02 KΩ, DAC Gain = 7.5 dB, RBW = 1 kHz
R
SET
SINGLE SIDEBAND TRANSMIT SPECTRUM
0
–10
–20
–30
–40
–50
MAGNITUDE (dB)
–60
–70
–80
–90
10 100
20 40 9080
0 11030 50 60 70
Figure 7. Single Sideband @ 65 MHz, RBW = 2 kHz, f
f = 1 MHz, R
= 27 MHz, f
OSCIN
= 10 mA), and 75 Ω DAC load, unless otherwise noted.
OUT
f
(MHz)
SYSCLK
FREQUENCY (MHz)
FREQUENCY (MHz)
= 4.02 KΩ, DAC gain = 7.5 dB
SET
= 216 MHz, f
SYSCLK
SYSCLK
= 5 MHz, f = 1 MHz,
C
= 66 MHz,
C
= 54 MHz (M = 8 and N = 4). ADC sample rate derived directly from
MCLK
02716-003
02716-005
0
02716-007
310
300
290
280
POWER
270
260
250
0 10010 30 50 60 70
20 40 9080
% DUTY CYCLE
Figure 4. Power Consumption vs. Transmit Burst Duty Cycle
0
–10
–20
–30
–40
–50
MAGNITUDE (dB)
–60
–70
–80
–90
57
55 7561 65 67 69
Figure 6. Dual Sideband Spectral Plot, f
0
–10
–20
–30
–40
–50
MAGNITUDE (dB)
–60
–70
–80
–90
0 11030 50 60 70
Figure 8. Single Sideband @ 42 MHz, RBW = 2 kHz, f
59 63 7371
FREQUENCY (MHz)
= 65 MHz, f = 1 MHz,
= 4.02 KΩ, (I
R
SET
20 40 9080
10 100
f = 1 MHz, R
= 10 mA), RBW = 1 kHz
OUT
FREQUENCY (MHz)
= 4.02 KΩ, DAC gain = 7.5 dB
SET
C
= 43 MHz,
C
02716-004
02716-006
02716-008
Rev. B | Page 10 of 36
AD9877
0
–10
–20
–30
–40
–50
MAGNITUDE (dB)
–60
–70
–80
–90
0 11030 50 60 70
20 40 9080
10 100
FREQUENCY (MHz)
Figure 9. Single Sideband @ 5 MHz, RBW = 2 kHz, f
f = 1 MHz, R
0
–10
–20
–30
–40
–50
MAGNITUDE (dB)
–60
–70
–80
–90
62.5 67.564.0 65.0 65.5
63.0 67.0
= 4.02 KΩ, DAC gain = 7.5 dB
SET
63.5 64.5 66.566.0
FREQUENCY (MHz)
Figure 10. Single Sideband @ 65 MHz, RBW = 500 Hz, f
f = 1 MHz, R
70
65
= 4.02 KΩ, DAC gain = 7.5 dB
SET
f
OSCIN
= 6 MHz,
C
= 66 MHz,
C
02716-009
02716-010
90
85
80
75
(dB)
70
65
60
5955
15 45 75
25 35 65 85 105
f
OSCIN
PLL
fIN (MHz)
Figure 12. 12-Bit ADC SFDR vs. Input Frequency
11.0
10.5
10.0
9.5
9.0
8.5
ENOB
8.0
7.5
7.0
6.5
6.0
15 45 75
5955
25 35 65 85 105
f
OSCIN
PLL
fIN (MHz)
Figure 13. 12-Bit ADC ENOBs vs. Input Frequency
–60
–65
02716-012
5
02716-013
5
60
55
(dB)
50
45
40
5955
15 45 75
25 35 65 85 105
PLL
fIN (MHz)
Figure 11. 12-Bit ADC SNR vs. Input Frequency
–70
–75
(dB)
–80
–85
02716-011
5
–90
5955
15 45 75
25 35 65 85 105
Figure 14. 12-Bit ADC THD vs. Input Frequency
Rev. B | Page 11 of 36
PLL
f
OSCIN
fIN (MHz)
02716-014
5
Loading...