Analog Devices AD9870EB, AD9870 Datasheet
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reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
AD9870
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2001
IF Digitizing Subsystem
FUNCTIONAL BLOCK DIAGRAM
IFIN
FREF
AD9870
LNA
–16dB
LO
SYNTH
IOUTL
LOP
LON
IOUTC
CLKP
CLKN
VREFP
VCM
VREFN
PC
PD
PE
SYNCB
LO VCO AND
LOOP FILTER
CLK VCO AND
LOOP FILTER
SAMP CLOCK
SYNTHESIZER
MXOP
MXON
IF2P
IF2N
GCP
GCN
DECIMATION
FILTER
CONTROL LOGIC
f
CLK
= 18MHz
- ADC
DAC
AGC
SPI
VO LTAG E
REFERENCE
FORMATTING/SSI
DOUTA
DOUTB
FS
CLKOUT
VGA /
AAF
FEATURES
10 MHz–300 MHz Input Frequency
Baseband (I/Q) Digital Output
10 kHz–150 kHz Output Signal Bandwidth
12 dB SSB NF
> –1 dBm IIP3 (High IIP3 Mode)
25 dB Continuous AGC Range + 16 dB Gain Step
Support for LO and Sampling Clock Synthesis
Programmable Decimation Rate, Output Format, AAF
Cutoff, AGC and Synthesizer Settings
360 Input Impedance
2.7 V–3.6 V Supply Voltage
Low Current: 42 mA Typ (High IIP3 Mode),
30 mA Typ (Low IIP3, Fixed Gain Mode)
48-Lead LQFP Package (1.4 mm Thick)
APPLICATIONS
Portable and Mobile Radio Products
Digital UHF/VHF FDMA Products
TETRA
PRODUCT DESCRIPTION
The AD9870 is a general-purpose IF subsystem that digitizes a
low-level 10 MHz–300 MHz IF input with a bandwidth of up to
150 kHz. The signal chain of the AD9870 consists of a low-noise
amplifier, a mixer, a variable gain amplifier with integral antialias
filter, a bandpass sigma-delta analog-to-digital converter, and a
decimation filter with programmable decimation factor. An automatic gain control (AGC) circuit provides the AD9870 with
25 dB of continuous gain adjustment. The high dynamic range
of the bandpass sigma-delta converter allows the AD9870 to
cope with blocking signals that are as much as 70 dB stronger
than the desired signal. Auxiliary blocks include clock and LO
synthesizers as well as a serial peripheral interface (SPI) port.
The SPI port programs numerous parameters of the AD9870,
including the synthesizer divide ratios, the AGC attack and decay
times, the AGC target signal level, the decimation factor, the
output data format, the 16 dB attenuator, and the bias currents of
several blocks. Reducing bias currents allows the user to reduce
power consumption at the expense of reduced performance.
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AD9870–SPECIFICATIONS
Parameter Conditions
1
Min Typ Max Unit
OVERALL
Analog Supply Voltage
(VDDA, VDDF, VDDI) 2.7 3.0 3.6 V
Digital Supply Voltage
(VDDD, VDDC, VDDL) 2.7 3.0 3.6 V
Interface Supply Voltage
(VDDH) 1.8 3.6 V
Charge Pump Supply Voltage
(VDDP, VDDQ) 2.7 3.0 5.5 V
Total Current High IIP3 Setting 42 50.6 mA
SSB Noise Figure @ Max VGA Gain High IIP3 Setting 12 dB
Low IIP3 Setting 12 dB
Input Third-Order Intercept (IIP3) High IIP3 Setting –5 –1 dBm
Low IIP3 Setting –10 dBm
Input Impedance 360 Ω
Gain Variation Over Temperature 0.6 dB
PREAMP + MIXER
Maximum Input and LO Frequencies 300 MHz
LO SYNTHESIZER
LO Input Frequency 7.75 300 MHz
LO Input Amplitude 0.3 1.0 V p-p
FREF (Reference) Frequency 0.1 25 MHz
FREF Input Amplitude 0.3 3 V p-p
Minimum Charge Pump Output Current Programmable in 0.625 mA Steps 0.625 mA
Maximum Charge Pump Output Current Programmable in 0.625 mA Steps 5.000 mA
Charge Pump Output Compliance Voltage
2
0.25 VDDP – 0.25 V
Synthesizer Resolution 6.25 kHz
CLOCK SYNTHESIZER
CLK Input Frequency 13 18 MHz
CLK Input Amplitude Clock VCO Off 0.3 V p-p
Minimum Charge Pump Output Current Programmable in 0.625 mA Steps 0.625 mA
Maximum Charge Pump Output Current Programmable in 0.625 mA Steps 5.000 mA
Charge Pump Output Compliance Voltage
2
0.25 VDDQ – 0.25 V
Synthesizer Resolution 2.2 kHz
SIGMA-DELTA ADC
Resolution 16 Bits
Clock Frequency (f
CLK
) 13 18 MHz
Center Frequency f
CLK
/8 MHz
Dynamic Range BW = 10 kHz 88 dB
Passband Gain Variation 0.5 dB
DECIMATOR
Decimation Factor Programmable in Steps of 60 60 960
Passband Width 50 %
Passband Gain Variation 1dB
Alias Attenuation 85 dB
GAIN CONTROL
Programmable Gain Step 16 dB
AGC Gain Range (Continuous) 18 25 60 dB
AGC Attack Time Programmable 40 7000 µs
SPI
PC Clock Frequency 10 MHz
PD Hold Time 10 ns
SSI
CLKOUT Frequency 1 18 MHz
Output Rise/Fall Time CMOS Output Mode, Drive Strength = 0 120 ns
CMOS Output Mode, Drive Strength = 1 45 ns
CMOS Output Mode, Drive Strength = 2 16 ns
CMOS Output Mode, Drive Strength = 3 10 ns
OPERATING TEMPERATURE RANGE
Basic Functions –40 +95 °C
Meets All Specifications –40 +85 °C
NOTES
1
Standard operating mode: high IIP3 setting, synthesizers in normal (not fast acquire) mode, f
CLK
= 18 MHz, 25 pF load on SSI output pins: VDDx = 3.0 V.
2
Voltage span in which LO (or CLK) charge pump output current is maintained within 5% of nominal value of VDDP/2 (or VDDQ/2).
Specifications subject to change without notice.
(VDDI = VDDF = VDDA = 3.3 V, VDDC = VDDL = 3.3 V, VDDD = VDDH = 3.3 V, VDDQ =
VDDP = 5.0 V, CLK = 18 MSPS, FIF = 73.35 MHz, FLO = 71.1 MHz, unless otherwise noted.)
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CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9870 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS*
Parameter With Respect to Min Max Unit
VDDF, VDDA, VDDC, VDDD, VDDH, GNDF, GNDA, GNDC, GNDD, GNDH –0.3 +4.0 V
VDDL, VDDI GNDL, GNDI, GNDS
VDDF, VDDA, VDDC, VDDD, VDDH, VDDR, VDDA, VDDC, VDDD, VDDH, –4.0 +4.0 V
VDDL, VDDI VDDL, VDDI
VDDP, VDDQ GNDP, GNDQ –0.3 +6.0 V
GNDF, GNDA, GNDC, GNDD, GNDH GNDF, GNDA, GNDC, GNDD, GNDH –0.3 +0.3 V
GNDL, GNDI, GNDQ, GNDP, GNDS GNDL, GNDI, GNDQ, GNDP, GNDS
MXOP, MXON, LOP, LON, IFIN, GNDI –0.3 VDDI + 0.3 V
CXIF, CXVL, CXVM
PC, PD, PE, CLKOUT, DOUTA, GNDH –0.3 VDDH + 0.3 V
DOUTB, FS, SYNCB
IF2N, IF2P, GCP, GCN GNDF –0.3 VDDF + 0.3 V
VREFP, VREFN, VCM GNDA –0.3 VDDA + 0.3 V
IOUTC GNDQ –0.3 VDDQ + 0.3 V
IOUTL GNDP –0.3 VDDP + 0.3 V
CLKP, CLKN GNDC –0.3 VDDC + 0.3 V
FREF GNDL –0.3 VDDL + 0.3 V
Junction Temperature 150 °C
Storage Temperature –65 +150 °C
Lead Temperature (10 sec) 300 °C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended
periods may affect device reliability.
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LQFP
θ
JA
= 91°C/W
θ
JC
= 28°C/W
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD9870 –40°C to +85°C 48-Lead Thin Plastic Quad Flatpack (LQFP) ST-48
AD9870EB Evaluation Board
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AD9870
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PIN FUNCTION DESCRIPTIONS
Pin Mnemonic Description Pin Mnemonic Description
1 MXOP Mixer Output, Positive 25 PE Enable Input for SPI Port
2 MXON Mixer Output, Negative 26 VDDD Positive Power Supply for Internal Digital Functions
3 GNDF Ground for VGA 27 VDDH Positive Power Supply for Digital Interface
4 IF2N Second IF Input (to VGA), Negative 28 CLKOUT Clock Output for SSI Port
5 IF2P Second IF Input (to VGA), Positive 29 DOUTA Data Output for SSI Port
6 VDDF Positive Power Supply for Antialias Filter/VGA 30 DOUTB Data Output for SSI Port, Unused
7 GCP Filter Capacitor for VGA Gain Control, Positive 31 FS Frame Sync for SSI Port
8 GCN Filter Capacitor for VGA Gain Control, Negative 32 GNDH Ground for Digital Interface
9 VDDA Positive Power Supply for ADC 33 SYNCB Resets the SSI and Decimator Counters
10 GNDA Ground for ADC 34 GNDS Substrate Ground
11 VREFP Voltage Reference, Positive 35 FREF Reference Frequency Input for Both Synthesizers
12 VREFN Voltage Reference, Negative 36 GNDL Ground for LO Synthesizer
13 VCM Common-Mode Voltage (Requires 20 kΩ to GNDA) 37 GNDP Ground for LO Synthesizer Charge Pump
14 VDDQ Pos. Power Supply for Clock Synth. Charge Pump 38 IOUTL LO Synthesizer Charge Pump Output Current
15 IOUTC Clock Synthesizer Charge Pump Output Current 39 VDDP Positive Power Supply for LO Synth. Charge Pump
16 GNDQ Ground for Clock Synthesizer Charge Pump 40 VDDL Positive Power Supply for LO Synthesizer
17 VDDC Positive Power Supply for Clock Synthesizer 41 CXVM External Capacitor for Mixer Bias
18 GNDC Ground for Clock Synthesizer 42 LON LO Input to Mixer and LO Synthesizer, Negative
19 CLKP Sampling Clock Input/Clock VCO Tank, Positive 43 LOP LO Input to Mixer and LO Synthesizer, Positive
20 CLKN Sampling Clock Input/Clock VCO Tank, Negative 44 CXVL External Capacitor for Preamp Power Supply
21 GNDS Substrate Ground 45 GNDI Ground for Mixer and Preamp
22 GNDD Ground for Digital Functions 46 CXIF External Capacitor for Preamp Bias
23 PC Clock Input for SPI Port 47 IFIN First IF Input (to Preamp)
24 PD Data I/O for SPI Port 48 VDDI Positive Power Supply for Mixer and Preamp
PIN CONFIGURATION
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 39 38 3743 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
GNDL
FREF
GNDS
SYNCB
GNDH
FS
DOUTB
MXOP
MXON
GNDF
IF2N
IF2P
VDDF
GCP
GCN
VDDA
GNDA
VREFP
DOUTA
CLKOUT
VDDH
VDDD
AD9870
VREFN
PE
VDDI
IFIN
CXIF
GNDI
CXVL
LOP
LON
CXVM
VDDL
VDDP
IOUTL
GNDP
VCM
VDDQ
IOUTC
GNDQ
VDDC
GNDC
CLKP
CLKN
GNDS
GNDD
PC
PD
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AD9870
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SERIAL PERIPHERAL INTERFACE (SPI)
The Serial Peripheral Interface (SPI) is a bidirectional serial port. It is used to load configuration information into the registers listed
below as well as to read back their contents. Table I provides a list of the registers that may be programmed through the SPI port.
Addresses and default values are given in hexadecimal form.
Table I. SPI Address Map
Address Bit
(Hex) Breakdown Width Default Value Name Description
POWER CONTROL REGISTERS
0x00 (7:0) 8 0xFF STBY Standby Control Bits (REF, LO, CKO, CK, GC, LNAMX, VGA, ADC).
0x01 (7:6) 2 0 LNAB LNA Bias Current (0 = 0.5 mA, 1 = 1 mA, 2 = 2 mA, 3 = 3 mA).
(5:4) 2 0 MIXB Mixer Bias Current (0 = 1 mA, 1 = 2 mA, 2 = 3 mA, 3 = 4 mA).
(3:2) 2 0 CKOB CK Oscillator Bias (0 = 0.25 mA, 1 = 0.35 mA, 2 = 0.53 mA, 3 = 0.85 mA).
(1:0) 2 1 ADCB ADC Amplifier Bias (0 = 2.4 mA, 1 = 3.2 mA, 2 = 4.0 mA, 3 = 4.8 mA).
0x02 (7:0) 8 0x00 TEST Factory Test Mode.
AGC
0x03 (7) 1 0 ATTEN Apply 16 dB attenuation in the front end.
(6:0) 7 0x3F AGCG(14:8) AGC Gain Setting (7 MSBs of a 15-bit two’s-complement word).
0x04 (7:0) 8 0xFF AGCG(7:0) AGC Gain Setting (8 LSBs of a 15-bit two’s-complement word).
Default corresponds to maximum gain.
0x05 (7:4) 4 0 AGCA AGC Attack Time Setting. Default yields 50 Hz raw loop bandwidth.
(3:0) 4 0 AGCD AGC Decay Time Setting. Default is decay time = attack time.
0x06 (7:4) 4 0 AGCO AGC Overload Update Setting. Default is slowest update.
(3:0) 4 0 AGCD Fast AGC (Minimizes resistance seen between GCN and GCP).
(2:0) 3 0 AGCR AGC Enable/Reference Level (disabled, 3 dB, 6 dB, 9 dB, 12 dB, 15 dB below clip).
DECIMATION FACTOR
0x07 (3:0) 4 4 M Decimation Factor = 60 × (M + 1). Default is decimate-by-300.
LO SYNTHESIZER
0x08 (5:0) 6 0x00 LOR(13:8) Reference Frequency Divisor (6 MSBs of a 14-Bit Word).
0x09 (7:0) 8 0x38 LOR(7:0) Reference Frequency Divisor (8 LSBs of a 14-Bit Word).
Default (56) Yields 300 kHz from f
REF
= 16.8 MHz.
0x0A (7:5) 3 0x5 LOA “A” Counter (Prescaler Control Counter).
(4:0) 5 0x00 LOB(12:8) “B” Counter MSBs (5 MSBs of a 13-Bit Word).
Default LOA and LOB Values Yield 300 kHz from 73.35 MHz–2.25 MHz.
0x0B (7:0) 8 0x1D LOB(7:0) “B” Counter LSBs (8 LSBs of a 13-Bit Word).
0x0C (6) 1 0 LOF Enable Fast Acquire.
(5) 1 0 LOINV Invert Charge Pump (0 = Pump_Up ⇒ IOUTL Sources Current).
(4:2) 3 0 LOI Charge Pump Current in Normal Operation. I
PUMP
= (LOI + 1) × 0.625 mA.
(1:0) 2 0 LOTM Manual Control of LO Charge Pump (3 = Off, 2 = Down, 1 = Up, 0 = Normal).
0x0D (3:0) 4 0x0 LOFA(13:8) LO Fast Acquire Time Unit (4 MSBs of a 14-Bit Word).
0x0E (7:0) 8 0x04 LOFA(7:0) LO Fast Acquire Time Unit (8 LSBs of a 14-Bit Word).
CLOCK SYNTHESIZER
0x10 (5:0) 6 00 CKR(13:8) Reference Frequency Divisor (6 MSBs of a 14-Bit Word).
0x11 (7:0) 8 0x38 CKR(7:0) Reference Frequency Divisor (8 LSBs of a 14-Bit Word).
Default Yields 300 kHz from f
REF
=16.8 MHz.
Min = 3, Max = 16383.
0x12 (4:0) 5 0x00 CKN(12:8) Synthesized Frequency Divisor (5 MSBs of a 13-Bit Word).
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AD9870
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Address Bit
(Hex) Breakdown Width Default Value Name Description
CLOCK SYNTHESIZER (Continued)
0x13 (7:0) 8 0x3C CKN(7:0) Synthesized Frequency Divisor (8 LSBs of a 13-Bit Word).
Default Yields 300 kHz from f
CLK
= 18 MHz.
Min = 3, Max = 8191.
0x14 (6) 1 0 CKF Enable Fast Acquire.
(5) 1 0 CKINV Invert Charge Pump (0 = Pump_Up ⇒ IOUTC Sources Current).
(4:2) 3 0 CKI Charge Pump Current in Normal Operation. I
PUMP
= (CKI + 1) × 0.625 mA.
(1:0) 2 0 CKTM Manual Control of CLK Charge Pump (0 = Off, 1 = Down, 2 = Up, 3 = Normal).
0x15 (3:0) 4 0x0 CKFA(13:8) CK Fast Acquire Time Unit (4 MSBs of a 14-Bit Word).
0x16 (7:0) 8 0x04 CKFA(7:0) CK Fast Acquire Time Unit (8 LSBs of a 14-Bit Word).
SSI CONTROL
0x18 (7:0) 8 0x12 SSICRA SSI Control Register A. See Table III.
(Default is FS and CLKOUT Three-Stated.)
0x19 (1:0) 2 0x0 SSICRB SSI Control Register B. See Table III.
0x1A (3:0) 4 1 SSIORD Output Rate Divisor. f
CLKOUT
= f
CLK
/SSIORD.
AAF CAPACITOR SETTING/CALIBRATION
0x1C (7:0) 8 0x00 AAR Antialias Response Selector. 0x60 Is Recommended.
0x1D 5 1 0 ERRN Error Flag.
(4:0) 5 0x0 CAPN AAF N-Well Capacitor Setting.
0x1E 5 1 0 ERRP Error Flag.
(4:0) 15 0x0 CAPP AAF Poly-Poly Capacitor Setting.
TEST REGISTERS AND SPI PORT READ ENABLE
0x38 (7:0) 8 0x00 TEST Factory Test Mode.
0x39 0 1 0 TEST Factory Test Mode.
0x3A (7:4, 2:0) 7 0x0 TEST Factory Test Mode.
(3) 1 0 SPIREN Enable Read from SPI Port.
0x3B– (7:0) 1 0x00 TEST Factory Test Mode.
0x3F
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