ANALOG DEVICES AD9868 Service Manual

Broadband Modem Mixed-Signal Front End

FEATURES

Low cost 3.3 V CMOS MxFE for broadband modems 10-bit DAC converter

2×/4× interpolation filter

200 MSPS DAC update rate Integrated 17 dBm line driver with 19.5 dB gain control 10-bit, 80 MSPS, ADC converter

−12 dB to +48 dB low noise RxPGA (<3 nV/√Hz) Third-order, programmable low-pass filter Flexible digital data path interface

Half- and full-duplex operation

Pin compatible with the

Various power-down/reduction modes Internal clock multiplier (PLL) 2 auxiliary programmable clock outputs Available in a 64-lead LFCSP_VQ

APPLICATIONS

Broadband wireline networking

GENERAL DESCRIPTION

The AD9868 is a mixed-signal front-end (MxFE®) IC for transceiver applications requiring Tx path and Rx path functionality with data rates up to 80 MSPS. A lower cost, pincompatible version of the current amplifier (IAMP) IOUTP functionality and limits the PLL VCO operating range of 80 MHz to 200 MHz.

The part is well-suited for half- and full-duplex applications. The digital interface is extremely flexible, allowing simple interfacing to digital back ends that support half- or full-duplex data transfers, often allowing the AD9868 to replace discrete ADC and DAC solutions. Power-saving modes include the ability to reduce power consumption of individual functional blocks or power down unused blocks in half-duplex applications. A serial port interface (SPI) allows software programming of the various functional blocks. An on-chip PLL clock multiplier and synthesizer provide all the required internal clocks, as well as two external clocks, from a single crystal or clock source.

The Tx signal path consists of a 2×/4× low-pass interpolation filter, a 10-bit TxDAC, and a line driver. The transmit path signal bandwidth can be as high as 34 MHz at an input data rate

AD9865

AD9865, the AD9868 removes the

AD9868

FUNCTIONAL BLOCK DIAGRAM

IOUTP+

IOUTP–

AD9868

ADC

80MSPS

REGISTER CONTROL

2-4X

CLK SYNC.

0 TO 6dB Δ = 1dB

TxDAC

0 TO –7.5dB

2M CLK

MULTIPLIER

2-POLE

LPF

–6 TO +18dB Δ = 6dB

IAMP

0 TO –12dB

1-POLE

LPF

–6 TO +24dB Δ = 6dB

PWRDWN

MODE

TXEN/TXSYNC

TXCLK/T XQUIET

ADIO[9:4]/

Tx[5:0]

ADIO[3:0]/

Rx[5:0]

RXEN/RXSYNC

RXCLK

AGC[5:0]

PORT

SPI

PORT

10

6

4

Figure 1.

of 80 MSPS. The TxDAC provides differential current outputs that can be steered directly to an external load or to an internal low distortion current amplifier (IAMP) capable of delivering 17 dBm peak signal power. Tx power can be digitally controlled over a 19.5 dB range in 0.5 dB steps.

The receive path consists of a programmable amplifier (RxPGA), a tunable low-pass filter (LPF), and a 10-bit ADC. The low noise RxPGA has a programmable gain range of

−12 dB to +48 dB in 1 dB steps. Its input referred noise is less than 3 nV/√Hz for gain settings beyond 36 dB. The receive path LPF cutoff frequency can be set over a 15 MHz to 35 MHz range or it can be simply bypassed. The 10-bit ADC achieves excellent dynamic performance up to an 80 MSPS span. Both the RxPGA and the ADC offer scalable power consumption allowing power/performance optimization.

The AD9868 provides a highly integrated solution for many broadband modems. It is available in a space-saving package, a 16-lead LFCSP, and is specified over the commercial temperature range (−40°C to +85°C).

IOUT N+

IOUT N–

CLKOUT1 CLKOUT2

OSCIN XTAL

RX+

RX–

6733-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9868

REVISION HISTORY

5/07—Revision 0: Initial Version

Rev. 0 | Page 2 of 36

AD9868

SPECIFICATIONS

Tx PATH SPECIFICATIONS

AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, f

= 50 MHz, f

OSCIN

= 200 MHz, R

DAC

= 2.0 kΩ, unless otherwise noted.

SET

Table 1.

Parameter Temp Test Level

1

Min Typ Max Unit

TxDAC DC CHARACTERISTICS

Resolution Full 10 Bits Update Rate Full II 200 MSPS Full-Scale Output Current (IOUTP_FS) Full IV 2 25 mA Gain Error

2

25°C I ±2 % FS Offset Error 25°C V 2 μA Voltage Compliance Range Full −1 +1.5 V

TxDAC GAIN CONTROL CHARACTERISTICS

Minimum Gain 25°C V −7.5 dB Maximum Gain 25°C V 0 dB Gain Step Size 25°C V 0.5 dB Gain Step Accuracy 25°C IV Monotonic dB Gain Range Error 25°C V ±2 dB

TxDAC AC CHARACTERISTICS

3

Fundamental 0.5 dBm Signal-to-Noise and Distortion (SINAD) Full IV 62.0 63.1 dBc Signal-to-Noise Ratio (SNR) Full IV 62.5 63.2 dBc Total Harmonic Distortion (THD) Full IV −77.7 −67.0 dBc Spurious-Free Dynamic Range (SFDR) Full IV 67.1 79.3 dBc

IAMP DC CHARACTERISTICS

IOUTN Full-Scale Current = IOUTN+ + IOUTN− Full IV 2 105 mA AC Voltage Compliance Range Full IV 1 3.9 V

IAMPN AC CHARACTERISTICS

4

Fundamental 25°C 13 dBm IOUTN SFDR (Third Harmonic) Full IV 43.3 45.2 dBc

REFERENCE

Internal Reference Voltage

5

25°C I 1.23 V Reference Error Full V 0.7 3.4 % Reference Drift Full V 30 ppm/oC

Tx DIGITAL FILTER CHARACTERISTICS (2× Interpolation)

Latency (Relative to 1/f

−0.2 dB Bandwidth Full V 0.2187 f

−3 dB Bandwidth Full V 0.2405 f Stop-Band Rejection (0.289 f

) Full V 43 Cycles

DAC

OUT/fDAC

to 0.711 f

DAC

) Full V 50 dB

DAC

Tx DIGITAL FILTER CHARACTERISTICS (4× Interpolation)

Latency (Relative to 1/f

−0.2 dB Bandwidth Full V 0.1095 f

−3 dB Bandwidth Full V 0.1202 f Stop Band Rejection (0.289 f

) Full V 96 Cycles

DAC

OUT/fDAC

OSCIN

to 0.711 f

) Full V 50 dB

OSCIN

PLL CLK MULTIPLIER

OSCIN Frequency Range

PLL M Factor Set to 2 Full IV 40 80 MHz PLL M Factor Set to 4 Full IV 20 50 MHz

PLL M Factor Set to 8 Full IV 10 25 MHz Internal VCO Frequency Range Full IV 80 200 MHz Duty Cycle Full II 40 60 %

Rev. 0 | Page 3 of 36

AD9868

Parameter Temp Test Level

1

Min Typ Max Unit

OSCIN Impedance 25°C V 10||03 ΜΩ||pF CLKOUT1 Jitter CLKOUT2 Jitter CLKOUT1 and CLKOUT2 Duty Cycle

1

See the Explanation of Test Levels section.

2

Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1.23 V external reference and a 1 V p-p differential analog input).

3

TxDAC IOUTP_FS = 20 mA, differential output with 1:1 transformer with source and load termination of 50 Ω, f

4

IOUTN full-scale current = 80 mA, f

5

Use external amplifier to drive additional load.

6

Internal VCO operates at 200 MHz; set to divide-by-1.

7

Because CLKOUT2 is a divided-down version of OSCIN, its jitter is typically equal to OSCIN.

8

CLKOUT2 is an inverted replica of OSCIN, if set to divide-by-1.

6

7

8

= 80 MHz, f

OSCIN

=160 MHz, 2x interpolation.

DAC

25°C III 12 ps rms 25°C III 6 ps rms Full III 45 55 %

= 5 MHz, 4x interpolation.

OUT

Rx PATH SPECIFICATIONS

AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, half- or full-duplex operation with CONFIG = 0 default power bias settings, unless otherwise noted.

Table 2.

Parameter Temp Test Level1Min Typ Max Unit

Rx INPUT CHARACTERISTICS

Input Voltage Span

RxPGA Gain = −10 dB Full III 6.33 V p-p

RxPGA Gain = +48 dB Full III 8 mV p-p Input Common-Mode Voltage 25°C III 1.3 Differential Input Impedance 25°C III 400||4.0 Ω||pF Input Bandwidth with RxLPF Disabled, RxPGA = 0 dB 25°C III 53 MHz Input Voltage Noise Density

RxPGA Gain = 36 dB, f

RxPGA Gain = 48 dB, f

= 26 MHz 25°C III 3.0 nV/√Hz

−3 dBF

= 26 MHz 25°C III 2.4 nV/√Hz

−3 dBF

RxPGA CHARACTERISTICS

Minimum Gain 25°C III −12 dB Maximum Gain 25°C III 48 dB Gain Step Size 25°C III 1 dB Gain Step Accuracy 25°C III Monotonic dB Gain Range Error 25°C III 0.5 dB

RxLPF CHARACTERISTICS

Cutoff Frequency (f Attenuation at 55.2 MHz with f

) Range Full III 15 35 MHz

−3 dBF

= 21 MHz 25°C III 20 dB

−3 dBF

Pass-Band Ripple 25°C III ±1 dB Settling Time

5 dB RxPGA Gain Step @ f

60 dB RxPGA Gain Step @ f

= 50 MSPS 25°C III 20 ns

ADC

= 50 MSPS 25°C III 100 ns

ADC

ADC DC CHARACTERISTICS

Resolution N/A N/A 10 Bits Conversion Rate Full II 20 80 MSPS

Rx PATH LATENCY2

Full-Duplex Interface Full V 10.5 Cycles Half-Duplex Interface Full V 10.0 Cycles

Rx PATH COMPOSITE AC PERFORMANCE @ f

= 50 MSPS

ADC

3

RxPGA Gain = 48 dB (Full-Scale = 8.0 mV p-p)

Signal-to-Noise and Distortion (SINAD) 25°C III 43.7 dBc

Total Harmonic Distortion (THD) 25°C III −71 dBc

V

Rev. 0 | Page 4 of 36

AD9868

Parameter Temp Test Level1Min Typ Max Unit

RxPGA Gain = 24 dB (Full-Scale = 126 mV p-p)

Signal-to-Noise Ratio (SNR) 25°C III 59 dBc Total Harmonic Distortion (THD) 25°C III −67.2 dBc

RxPGA Gain = 0 dB (Full-Scale = 2.0 V p-p)

Signal-to-Noise and Distortion (SINAD) Full IV 58 59 dBc Total Harmonic Distortion (THD) Full IV −66 −62.9 dBc

Rx PATH COMPOSITE AC PERFORMANCE @ f

= 80 MSPS4

ADC

RxPGA Gain = 48 dB (Full-Scale = 8.0 mV p-p)

Signal-to-Noise Ratio (SNR) 25°C III 41.8 dBc Total Harmonic Distortion (THD) 25°C III −67 dBc

RxPGA Gain = 24 dB (Full-Scale = 126 mV p-p)

Signal-to-Noise Ratio (SNR) 25°C III 58.6 dBc Total Harmonic Distortion (THD) 25°C III −62.9 dBc

RxPGA Gain = 0 dB (Full-Scale = 2.0 V p-p)

Signal-to-Noise Ratio (SNR) 25°C II 58.9 59.6 dBc Total Harmonic Distortion (THD) 25°C II −69.7 −59.8 dBc

Rx-to-Tx PATH FULL-DUPLEX ISOLATION (1 V p-p, 10 MHz Sine Wave Tx Output)

RxPGA Gain = 40 dB

IOUTP± Pins to RX± Pins 25°C III 83 dBc

RxPGA Gain = 0 dB

IOUTP± Pins to RX± Pins 25°C III 123 dBc

1

See the Explanation of Test Levels section.

2

Includes RxPGA, ADC pipeline, and ADIO bus delay relative to f

3

fIN = 5 MHz, AIN = −1.0 dBFS, LPF cutoff frequency set to 15.5 MHz with Register 0x08 = 0x80.

4

fIN = 5 MHz, AIN = −1.0 dBFS, LPF cutoff frequency set to 26 MHz with Register 0x08 = 0x80.

ADC

.

Rev. 0 | Page 5 of 36

AD9868

POWER SUPPLY SPECIFICATIONS

AVDD = 3.3 V, DVDD = CLKVDD = DRVDD = 3.3 V, R

Table 3.

Parameter Temp Test Level2 Min Typ Max Unit

SUPPLY VOLTAGES

AVDD Full V 3.135 3.3 3.465 V CLKVDD Full V 3.0 3.3 3.6 V DVDD Full V 3.0 3.3 3.6 V DRVDD Full V 3.0 3.3 3.6 V IS_TOTAL (Total Supply Current) Full II 406 475 mA

POWER CONSUMPTION

I

AVDD

I

DVDD

+ I + I

(Analog Supply Current) Full IV 311 342 mA

CLKVDD

(Digital Supply Current) Full IV 95 133 mA

DRVDD

POWER CONSUMPTION (Half-Duplex Operation with f

Tx Mode

I

AVDD

I

DVDD

+ I + I

25°C IV 112 130 mA

CLKVDD

25°C IV 46 49.5 mA

DRVDD

Rx Mode

I

+ I

AVDD

I

+ I

DVDD

POWER CONSUMPTION OF FUNCTIONAL BLOCKS1 (I

25°C IV 225 253 mA

CLKVDD

25°C IV 36.5 39 mA

DRVDD

AVDD

RxPGA and LPF 25°C III 87 mA ADC 25°C III 108 mA TxDAC 25°C III 38 mA IAMP (Programmable) 25°C III 10 100 mA Reference 25°C III 170 mA CLK PLL and Synthesizer 25°C III 107 mA

MAXIMUM ALLOWABLE POWER DISSIPATION Full IV 1.66 W STANDBY POWER CONSUMPTION

IS_TOTAL (Total Supply Current) Full

POWER-DOWN DELAY (Using PWRDWN Pin)

RxPGA and LPF 25°C III 440 ns ADC 25°C III 12 ns TxDAC 25°C III 20 ns IAMP 25°C III 20 ns CLK PLL and Synthesizer 25°C III 27 ns

POWER-UP DELAY (Using PWRDWN Pin)

RxPGA and LPF 25°C III 7.8 μs ADC 25°C III 88 ns TxDAC 25°C III 13 μs IAMP 25°C III 20 ns CLK PLL and Synthesizer 25°C III 20 μs

1

Default power-up settings for MODE = high and CONFIG = low, IOUTP_FS = 20 mA, does not include IAMP current consumption, which is application dependent.

2

See the Explanation of Test Levels section.

3

Default power-up settings for MODE = low and CONFIG = low.

= 2 kΩ, full-duplex operation with f

SET

= 50 MSPS)

DATA

+ I

CLKVDD

3

)

= 80 MSPS1, unless otherwise noted.

DATA

13 mA

Rev. 0 | Page 6 of 36

AD9868

DIGITAL SPECIFICATIONS

AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, R

= 2 kΩ, unless otherwise noted.

SET

Table 4.

Parameter Temp Test Level

1

Min Typ Max Unit

CMOS LOGIC INPUTS

High Level Input Voltage Full VI DRVDD − 0.7 V Low Level Input Voltage Full VI 0.4 V Input Leakage Current 12 μA Input Capacitance Full VI 3 pF

CMOS LOGIC OUTPUTS (C

= 5 pF)

LOAD

High Level Output Voltage (IOH = 1 mA) Full VI DRVDD − 0.7 V Low Level Output Voltage (IOH = 1 mA) Full VI 0.4 V Output Rise/Fall Time

High Strength Mode and C Low Strength Mode and C High Strength Mode and C Low Strength Mode and C

= 15 pF Full VI 1.5/2.3 ns

LOAD

= 15 pF Full VI 1.9/2.7 ns

LOAD

= 5 pF Full VI 0.7/0.7 ns

LOAD

= 5 pF Full VI 1.0/1.0 ns

LOAD

RESET

Minimum Low Pulse Width (Relative to f

1

See the Explanation of Test Levels section.

) 1 Clock cycles

ADC

SERIAL PORT TIMING SPECIFICATIONS

AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted.

Table 5.

Parameter Temp Test Level

1

Min Typ Max Unit

WRITE OPERATION (See Figure 5)

SCLK Clock Rate (f

) Full IV 32 MHz

SCLK

SCLK Clock High (tHI) Full IV 14 ns SCLK Clock Low (t

) Full IV 14 ns

LOW

SDIO to SCLK Setup Time (tDS) Full IV 14 ns SCLK to SDIO Hold Time (tDH) Full IV 0 ns SEN to SCLK Setup Time (tS)

SCLK to SEN Hold Time (tH)

Full IV 14 ns Full IV 0 ns

READ OPERATION (See Figure 6 and Figure 7)

SCLK Clock Rate (f

) Full IV 32 MHz

SCLK

SCLK Clock High (tHI) Full IV 14 ns SCLK Clock Low (t

) Full IV 14 ns

LOW

SDIO to SCLK Setup Time (tDS) Full IV 14 ns SCLK to SDIO Hold Time (tDH) Full IV 0 ns SCLK to SDIO (or SDO) Data Valid Time (tDV) Full IV 14 ns SEN to SDIO Output Valid to High-Z (tEZ)

1

See the Explanation of Test Levels section.

Full IV 2 ns

Rev. 0 | Page 7 of 36

AD9868

HALF-DUPLEX DATA INTERFACE (ADIO PORT) TIMING SPECIFICATIONS

AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted.

Table 6.

Parameter Temp Test Level

READ OPERATION2 (See Figure 9)

1

Min Typ Max Unit

Output Data Rate Full II 20 80 MSPS Three-State Output Enable Time (t Three-State Output Disable Time (t

) Full II 3 ns

PZL

) Full II 3

PLZ

ns

Rx Data Valid Time (tVT) Full II 1.5 ns Rx Data Output Delay (tOD) Full II 4 ns

WRITE OPERATION (See Figure 8)

Input Data Rate (2× Interpolation) Full II 40 80 MSPS Input Data Rate (4× Interpolation) Full II 20 50 MSPS Tx Data Setup Time (tDS) Full II 1 ns Tx Data Hold Time (tDH) Full II 2.5 ns Latch Enable Time (tEN) Full II 3 ns Latch Disable Time (t

1

See the Explanation of Test Levels section.

2

C

= 5 pF for digital data outputs.

LOAD

) Full II 3 ns

DIS

FULL-DUPLEX DATA INTERFACE (Tx AND Rx PORT) TIMING SPECIFICATIONS

AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted.

Table 7.

Parameter Temp Test Level

Tx PATH INTERFACE (See Figure 12)

Input Nibble Rate (2× Interpolation) Full II 80 160 MSPS Input Nibble Rate (4× Interpolation) Full II 40 100 MSPS Tx Data Setup Time (tDS) Full II 2.5 ns Tx Data Hold Time (tDH) Full II 1.5 ns

Rx PATH INTERFACE2 (See Figure 13)

Output Nibble Rate Full II 40 160 MSPS Rx Data Valid Time (tDV) Full II 3 ns Rx Data Hold Time (tDH) Full II 0 ns

1

See the Explanation of Test Levels section.

2

C

= 5 pF for digital data outputs.

LOAD

1

Min Typ Max Unit

Rev. 0 | Page 8 of 36

AD9868

ABSOLUTE MAXIMUM RATINGS

Table 8.

Parameter Rating

ELECTRICAL

AVDD, CLKVDD Voltage 3.9 V maximum DVDD, DRVDD Voltage 3.9 V maximum RX+, RX−, REFT, REFB −0.3 V to AVDD + 0.3 V IOUTP+, IOUTP− −1.5 V to AVDD + 0.3 V IOUTN+, IOUTN− −0.3 V to +3.9 V OSCIN, XTAL −0.3 V to CLVDD + 0.3 V REFIO, REFADJ −0.3 V to AVDD + 0.3 V Digital Input and Output Voltage −0.3 V to DRVDD + 0.3 V Digital Output Current 5 mA maximum

ENVIRONMENTAL

Operating Temperature Range

(Ambient) Maximum Junction Temperature 125°C Lead Temperature (Soldering, 10 sec) 150°C Storage Temperature Range (Ambient) −65°C to +150°C

−40°C to +85°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

Thermal Resistance: 64-lead LFCSP (4-layer board).

= 24°C/W (paddle soldered to ground plane, 0 LPM air).

θ

JA

= 30.8°C/W (paddle not soldered to ground plane, 0 LPM air).

θ

JA

EXPLANATION OF TEST LEVELS

I. 100% production tested.

II. 100% production tested at 25°C and guaranteed by design

and characterization at specified temperatures.

III. Sample tested only.

IV. Parameter is guaranteed by design and characterization

testing.

V. Parameter is a typical value only.

VI. 100% production tested at 25°C and guaranteed by design

and characterization for industrial temperature range.

ESD CAUTION

Rev. 0 | Page 9 of 36

AD9868

T

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DRVDD

DRVSS

PWRDWN

CLKOUT2

DVDD

DVSS

CLKVDD

OSCIN

XTAL

CLKVSS

CONFIG

ADIO9/Tx[5]

ADIO8/Tx[4]

ADIO7/Tx[3]

ADIO6/Tx[2]

ADIO5/Tx[1]

ADIO4/Tx[0]

ADIO3/Rx[5]

ADIO2/Rx[4]

ADIO1/Rx[3]

ADIO0/Rx[2]

NC/Rx[1]

NC/Rx[0]

RXEN/RXSYNC

TXEN/TXSYNC

XCLK/TXQUIET

RXCLK

MODE

64

63 62 61 60 595857 56 55 54 535251 50

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

PIN 1 IDENTIFIER

AD9868

TOP VIEW

(Not to Scale)

IOUTP+

NC

IOUTN+

IOUTP–

49

AVSS

48

AVSS

47

46

IOUTN–

45

NC

44

AVS S

43

AVD D

42

REFIO

41

REFADJ

40

AVD D

39

AVSS

38

RX+

37

RX–

AVSS

36

35

AVD D

34

AVSS

REFT

33

3217 18 19 20 21 22 23 24 25 26 27 282930 31

SDIO

DRVSS

DRVDD

CLKOUT 1

SCLK

PGA[4]

PGA[3]

PGA[2]

PGA[1]

GAIN/PGA[5]

AVSS

REFB

RESET

PGA[0]

SEN

SDO

Figure 2. Pin Configuration

Table 9. Pin Function Descriptions

Pin No. Mnemonic Mode

1

Description

1 ADIO9 HD MSB of ADIO Buffer. Tx[5] FD MSB of Tx Nibble Input. 2 to 5 ADIO8 to ADIO5 HD Bit 8 to Bit 5 of ADIO Buffer. Tx[4:1] FD Bit 4 to Bit 1 of Tx Nibble Input. 6 ADIO4 HD Bit 4 of ADIO Buffer. Tx[0] FD LSB of Tx Nibble Input. 7 ADIO3 HD Bit 3 of ADIO Buffer. Rx[5] FD MSB of Rx Nibble Output. 8, 9 ADIO2, ADIO1 HD Bit 2 to Bit 1 of ADIO Buffer. Rx[4:3] FD Bit 4 to Bit 3 of Rx Nibble Output. 10 ADIO0 HD LSB of ADIO Buffer. Rx[2] FD Bit 2 of Rx Nibble Output. 11 NC HD No Connect. Rx[1] FD Bit 1 of Rx Nibble Output. 12 NC HD No Connect. Rx[0] FD LSB of Rx Nibble Output. 13 RXEN HD ADIO Buffer Control Input. RXSYNC FD Rx Data Synchronization Output. 14 TXEN HD Tx Path Enable Input. TXSYNC FD Tx Data Synchronization Input. 15 TXCLK HD ADIO Sample Clock Input.

TXQUIET

FD Fast TxDAC/IAMP Power-Down.

16 RXCLK HD ADIO Request Clock Input. FD Rx and Tx Clock Output at 2 x f

ADC

06733-002

.

Rev. 0 | Page 10 of 36

AD9868

Pin No. Mnemonic Mode

1

Description

17, 64 DRVDD Digital Output Driver Supply Input. 18, 63 DRVSS Digital Output Driver Supply Return. 19 CLKOUT1

f

/N Clock Output (R = 1, 2, or 3).

ADC

20 SDIO Serial Port Data Input/Output. 21 SDO Serial Port Data Output. 22 SCLK Serial Port Clock Input. 23

SEN

Serial Port Enable Input. 24 GAIN FD Tx Data Port (Tx[5:0]) Mode Select. PGA[5] HD or FD MSB of PGA Input Data Port. 25 to 29 PGA[4:0] HD or FD Bit 4 to Bit 0 of PGA Input Data Port. 30

RESET

Reset Input (Active Low). 31, 34, 36, 39, 44, 47, 48 AVSS Analog Supply Return.

32, 33 REFB, REFT ADC Reference Decoupling Nodes. 35, 40, 43 AVDD Analog Power Supply Input. 37, 38 RX−, RX+ Receive Path − and + Analog Inputs. 41 REFADJ TxDAC Full-Scale Current Adjust. 42 REFIO TxDAC Reference Input/Output. 45, 49 NC Do Not Connect; Leave Open. 46 IOUTN− −Tx Mirror Current Output Sink. 50 IOUTN+ +Tx Mirror Current Output Sink. 51 IOUTP− −TxDAC Current Output Source. 52 IOUTP+ +TxDAC Current Output Source. 53 MODE Digital Interface Mode Select Input, Low = HD, High = FD. 54 CONFIG Power-Up SPI Register Default Setting Input. 55 CLKVSS Clock Oscillator/Synthesizer Supply Return. 56 XTAL Crystal Oscillator Inverter Output. 57 OSCIN Crystal Oscillator Inverter Input. 58 CLKVDD Clock Oscillator/Synthesizer Supply. 59 DVSS Digital Supply Return. 60 DVDD Digital Supply Input. 61 CLKOUT2

f

/L Clock Output (L = 1, 2, or 4).

OSCIN

62 PWRDWN Power-Down Input.

1

HD = half-duplex mode; FD = full-duplex mode.

Rev. 0 | Page 11 of 36

ANALOG DEVICES AD9868 Service Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

Tx PATH SPECIFICATIONS

Rx PATH SPECIFICATIONS

POWER SUPPLY SPECIFICATIONS

DIGITAL SPECIFICATIONS

SERIAL PORT TIMING SPECIFICATIONS

HALF-DUPLEX DATA INTERFACE (ADIO PORT) TIMING SPECIFICATIONS

FULL-DUPLEX DATA INTERFACE (Tx AND Rx PORT) TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

EXPLANATION OF TEST LEVELS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS