ANALOG DEVICES AD9861 Service Manual

A

www.BDTIC.com/ADI

Mixed-Signal Front-End (MxFE™) Baseband

Transceiver for Broadband Applications

FEATURES

Receive path includes dual 10-bit analog-to-digital

converters with internal or external reference, 50 MSPS and 80 MSPS versions

Transmit path includes dual 10-bit, 200 MSPS digital-to-

analog converters with 1×, 2×, or 4× interpolation and programmable gain control

Internal clock distribution block includes a programmable

phase-locked loop and timing generation circuitry, allowing single-reference clock operation

20-pin flexible I/O data interface allows various interleaved

or noninterleaved data transfers in half-duplex mode and interleaved data transfers in full-duplex mode

Configurable through register programmability or

optionally limited programmability through mode pins Independent Rx and Tx power-down control pins 64-lead LFCSP package (9 mm × 9 mm footprint) 3 configurable auxiliary converter pins

APPLICATIONS

Broadband access Broadband LAN Communications (modems)

GENERAL DESCRIPTION

The AD9861 is a member of the MxFE family—a group of integrated converters for the communications market. The AD9861 integrates dual 10-bit analog-to-digital converters (ADC) and dual 10-bit digital-to-analog converters (TxDAC®). Two speed grades are available, -50 and -80. The -50 is optimized for ADC sampling of 50 MSPS and less, while the -80 is optimized for ADC sample rates between 50 MSPS and 80 MSPS. The dual TxDACs operate at speeds up to 200 MHz and include a bypassable 2× or 4× interpolation filter. Three auxiliary converters are also available to provide required system level control voltages or to monitor system signals. The AD9861 is optimized for high performance, low power, small form factor, and to provide a cost-effective solution for the broadband communication market.

The AD9861 uses a single input clock pin (CLKIN) to generate all system clocks. The ADC and TxDAC clocks are generated within a timing generation block that provides user programmable options such as divide circuits, PLL multipliers, and switches.

A flexible, bidirectional 20-bit I/O bus accommodates a variety

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9861

FUNCTIONAL BLOCK DIAGRAM

VIN+A VIN–A

VIN+B VIN–B

IOUT+ IOUT–A

IOUT+B IOUT–B

of custom digital back ends or open market DSPs.

In half-duplex systems, the interface supports 20-bit parallel transfers or 10-bit interleaved transfers. In full-duplex systems, the interface supports an interleaved 10-bit ADC bus and an interleaved 10-bit TxDAC bus. The flexible I/O bus reduces pin count and, therefore, reduces the required package size on the AD9861 and the device to which it connects.

The AD9861 can use either mode pins or a serial programmable interface (SPI) to configure the interface bus, operate the ADC in a low power mode, configure the TxDAC interpolation rate, and control ADC and TxDAC power-down. The SPI provides more programmable options for both the TxDAC path (for example, coarse and fine gain control and offset control for channel matching) and the ADC path (for example, the internal duty cycle stabilizer, and twos complement data format).

The AD9861 is packaged in a 64-lead LFCSP (low profile, fine pitched, chip scale package). The 64-lead LFCSP footprint is only 9 mm × 9 mm, and is less than 0.9 mm high, fitting into tightly spaced applications such as PCMCIA cards

ADC

DAC

LOW-PASS

INTERPOLATION

FILTER

AUX ADC

AUX DAC

AUX ADC

AUX DAC

DATA

MUX AND

LATCH

DATA

LATCH

AND

DEMUX

DAC CLOCK PLL

Figure 1.

Rx DATA

I/O

INTERFACE

CONFIGURATION

BLOCK

Tx DATA

AD9861

03606-0-001

I/O INTERFACE CONTROL

FLEXIBLE I/O BUS [0:19]

CLKINADC CLOCK

AD9861

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TABLE OF CONTENTS

Tx Path Specifications...................................................................... 3

Theory of Operation...................................................................... 22

Rx Path Specifications...................................................................... 4

Power Specifications......................................................................... 5

Digital Specifications........................................................................ 5

Timing Specifications....................................................................... 6

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Pin Function Descriptions...................... 8

Typical Performance Characteristics ........................................... 10

Te r m in o l o g y .................................................................................... 21

REVISION HISTORY

Revision 0: Initial Version

System Block ............................................................................... 22

Rx Path Block.............................................................................. 22

Tx Path Block.............................................................................. 24

Auxiliary Converters.................................................................. 27

Digital Block................................................................................ 30

Programmable Registers............................................................ 42

Clock Distribution Block .......................................................... 45

Outline Dimensions....................................................................... 49

Ordering Guide .......................................................................... 50

Rev. 0 | Page 2 of 52

AD9861

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Tx PATH SPECIFICATIONS

Table 1. AD9861-50 and AD9861-80

= 200 MSPS; 4× interpolation; R

F

DAC

unless otherwise noted

Parameter Temp Test Level Min Typ Max Unit

Tx PATH GENERAL

Resolution Full IV 10 Bits Maximum DAC Update Rate Full IV 200 MHz Maximum Full-Scale Output Current Full IV 20 mA Full-Scale Error Full V 1% Gain Mismatch Error 25°C IV –3.5 +3.5 % FS Offset Mismatch Error Full IV –0.1 +0.1 % FS Reference Voltage Full V 1.23 V Output Capacitance Full V 5 pF Phase Noise (1 kHz Offset, 6 MHz Tone) 25°C V –115 dBc/Hz Output Voltage Compliance Range Full IV –1.0 +1.0 V TxPGA Gain Range Full V 20 dB TxPGA Step Size Full V 0.10 dB

Tx PATH DYNAMIC PERFORMANCE (I

= 20 mA; F

OUTFS

SNR Full IV 60.2 60.8 dB SINAD Full IV 59.7 60.7 dB THD Full IV −77.5 −65.8 dBc SFDR, Wideband (DC to Nyquist) Full IV 64.6 76.0 dBc SFDR, Narrowband (1 MHz Window) Full IV 72.5 81.0 dBc

1

See Figure 2 for description of the TxDAC termination scheme.

= 1 MHz)

OUT

= 4.02 kΩ; differential load resistance of 100 Ω1; TxPGA = 20 dB, AVDD = DVDD = 3.3 V,

SET

TxDAC

50Ω 50Ω

03606-0-030

Figure 2. Diagram Showing Termination of 100 Ω Differential

Load for Some TxDAC Measurements

Rev. 0 | Page 3 of 52

AD9861

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Rx PATH SPECIFICATIONS

Table 2. AD9861-50 and AD9861-80 F

= 50 MSPS for the AD9861-50, 80 MSPS for the AD9861-80; internal reference; differential analog inputs,

ADC

ADC_AVDD = DVDD = 3.3V, unless otherwise noted

Parameter Temp Test Level Min Typ Max Unit

Rx PATH GENERAL

Resolution Full V 10 Bits Maximum ADC Sample Rate Full IV 50/80 MSPS Gain Mismatch Error Full V

Offset Mismatch Error Full V Reference Voltage Full V 1.0 V

Reference Voltage (REFT–REFB) Error Full IV –30 Input Resistance (Differential) Full V 2 kΩ

Input Capacitance Full V 5 pF Input Bandwidth Full V 30 MHz Differential Analog Input Voltage Range Full V 2 V p-p differential

Rx PATH DC ACCURACY

Integral Nonlinearity (INL) 25°C V Differential Nonlinearity (DNL) 25°C V Aperature Delay 25°C V 2.0 ns

Aperature Uncertainty (Jitter) 25°C V 1.2 ps rms Input Referred Noise 25°C V 450 uV

AD9861-50 Rx PATH DYNAMIC PERFORMANCE (V

= –0.5 dBFS; FIN = 10 MHz)

IN

SNR Full IV 55.5 60 dBc SINAD Full IV 55.6 60 dBc SINAD 25°C IV 58.5 60 dBc THD (Second to Ninth Harmonics) Full IV −71.5 −64.6 dBc SFDR, Wideband (DC to Nyquist) Full IV 65.7 73.5 dBc Crosstalk between ADC Inputs Full V 80 dB

AD9861-80 Rx PATH DYNAMIC PERFORMANCE (V

= –0.5 dBFS; FIN = 10 MHz)

IN

SNR Full IV 55.4 59.5 dBc SINAD Full IV 52.7 59.0 dBc THD (Second to Ninth Harmonics) Full IV −67 dBc SFDR, Wideband (DC to Nyquist) Full IV 67 dBc Crosstalk between ADC Inputs Full V 80 dB

±0.2 ±0.1

±6

±0.75 ±0.75

% FS % FS

+30 mV

LSB LSB

Rev. 0 | Page 4 of 52

AD9861

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POWER SPECIFICATIONS

Table 3. AD9861-50 and AD9861-80 Analog and digital supplies = 3.3 V; F

Parameter Temp Test Level Min Typ Max Unit

POWER SUPPLY RANGE

Analog Supply Voltage (AVDD) Full IV 2.7 3.6 V Digital Supply Voltage (DVDD) Full IV 2.7 3.6 V Driver Supply Voltage (DRVDD)

ANALOG SUPPLY CURRENTS

TxPath (20 mA Full-Scale Outputs) Full V 70 mA TxPath (2 mA Full-Scale Outputs) Full V 20 mA Rx Path (-80, at 80 MSPS) Full V 165 mA RxPath (-80, at 40 MSPS, Low Power Mode) Full V 82 mA RxPath (-80, at 20 MSPS, Ultralow Power Mode) Full V 35 mA Rx Path (-50, at 50 MSPS) Full V 103 mA RxPath (-50, at 50 MSPS, Low Power Mode) Full V 69 mA RxPath (-50, at 16 MSPS, Ultralow Power Mode) Full V 28 mA TxPath, Power-Down Mode Full V 2 mA RxPath, Power-Down Mode Full V 5 mA PLL Full V 12 mA

DIGITAL SUPPLY CURRENTS

TxPath, 1× Interpolation,

50 MSPS DAC Update for Both DACs, Half-Duplex 24 Mode

TxPath, 2× Interpolation,

100 MSPS DAC Update for Both DACs, Half-Duplex 24 Mode

TxPath, 4× Interpolation,

200 MSPS DAC Update for Both DACs, Half-Duplex 24 Mode

RxPath Digital, Half-Duplex 24 Mode Full V 15 mA

= 50 MHz; PLL 4× setting; normal timing mode

CLKIN

Full IV 2.7 3.6 V

Full V 20 mA

Full V 50 mA

Full V 80 mA

DIGITAL SPECIFICATIONS

Table 4. AD9861-50 and AD9861-80

Parameter Temp Test Level Min Typ Max Unit

LOGIC LEVELS

Input Logic High Voltage, V Input Logic Low Voltage, V Output Logic High Voltage, VOH (1 mA Load) Full IV DRVDD – 0.6 V Output Logic Low Voltage, VOL (1 mA Load) Full IV 0.4 V

DIGITAL PIN

Input Leakage Current Full IV 12 µA Input Capacitance Full IV 3 pF Minimum RESET Low Pulse Width Full IV 5 Input Clock Cycles Digital Output Rise/Fall Time Full IV 2.8 4 ns

IH

IL

Full IV DRVDD – 0.7 V Full IV 0.4 V

Rev. 0 | Page 5 of 52

AD9861

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TIMING SPECIFICATIONS

Table 5. AD9861-50 and AD9861-80

Parameter Temp Test Level Min Typ Max Unit

INPUT CLOCK

CLKIN Clock Rate (PLL Bypassed) Full IV 1 200 MHz PLL Input Frequency Full IV 16 200 MHz PLL Ouput Frequency Full IV 32 350 MHz

TxPATH DATA

Setup Time (HD20 Mode, Time Required Before Data Latching Edge)

Hold Time (HD20 Mode, Time Required After Data Latching Edge)

Latency 1× Interpolation (data in until peak output response) Full V 7 DAC Clock Cycles Latency 2× Interpolation (data in until peak output response) Full V 35 DAC Clock Cycles Latency 4× Interpolation (data in until peak output response) Full V 83 DAC Clock Cycles

RxPATH DATA

Output Delay (HD20 Mode, tOD) Full V –1.5

Latency Full V 5 ADC Clock Cycles

Table 6. Explanation of Test Levels

Level Description

I 100% production tested. II

III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI

100% production tested at 25°C and guaranteed by design and characterizati

Full V 5

Full V –1.5

on at specified temperatures.

on for industrial temperature range.

ns (see Clock Distribution Block section)

ns (see Clock Distribution Blo section)

ck

Rev. 0 | Page 6 of 52

AD9861

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ABSOLUTE MAXIMUM RATINGS

Table 7.

Parameter Rating

Electrical

AVDD Voltage 3.9 V max DRVDD Voltage 3.9 V max Analog Input Voltage –0.3 V to AVDD + 0.3 V Digital Input Voltage –0.3 V to DVDD – 0.3 V Digital Output Current 5 mA max

Environmental

Operating Temperature Range (Ambient)

Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range

(Ambient)

Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

–40°C to +85°C

150°C 300°C

–65°C to +150°C

Thermal Resistance

64-lead LFCSP (4-layer board):

= 24.2 (paddle soldered to ground plan, 0 LPM Air)

θ

JA

θ

= 30.8 (paddle not soldered to ground plan, 0 LPM Air)

JA

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 7 of 52

AD9861

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PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS

SPI_DIO

SPI_CLK

SPI_SDO/AUX_SPI_SDO

ADC_LO_PWR/AUX_SPI_CS

DVDD DVSS

AVDD IOUT–A IOUT+A

AGND

REFIO

FSADJ

AGND IOUT+B IOUT–B

AVDD

SPI_CS64TxPWRDWN63RxPWRDWN62ADC_AVDD61REFT60ADC_AVSS59VIN+A58VIN–A57VREF56VIN–B55VIN+B54ADC_AVSS53REFB52ADC_AVDD51PLL_AVDD50PLL_AVSS

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

18U919U820U721U622U523U424U325U226U127U028

IFACE217IFACE3

AD9861

TOP VIEW

(Not to Scale)

Figure 3. Pin Configuration

30

31

DRVDD

AUX_DACA/AUX_ADCA229AUX_DACB/AUX_ADCA1

49

CLKIN

48

AUXADC_REF

47 46

RESET AUX_DACC/AUX_ADCB

45

L0

44 43

L1 L2

42

L3

41 40

L4 L5

39

L6

38 37

L7 L8

36

L9

35 34

AUX_SPI_CLK IFACE1

33

32

DRVSS

03606-0-019

Table 8. Pin Function Descriptions

Pin No. Name

1 SPI_DIO

2 SPI_CLK

3 SPI_SDO/AUXSPI_SDO

1

(Interp1

(Interp0

(FD/HD)

Description SPI: Serial Port Data Input.

)

No SPI: Tx Interpolation Pin, MSB. SPI: Serial Port Shift Clock.

)

No SPI: Tx Interpolation Pin, LSB. SPI: 4-Wire Serial Port Data Output/Data Output Pin for AuxSPI. No SPI: Configures Full-Duplex or Half-Duplex Mode.

2, 3

4 ADC_LO_PWR/AUX_SPI_CS ADC Low Power Mode Enable. Defined at power-up. CS for AuxSPI. 5, 31 DVDD Digital Supply. 6, 32 DVSS Digital Ground. 7, 16, 50, 51, 61 AVDD Analog Supply. 8, 9 IOUT–A, IOUT+A DAC A Differential Output. 10, 13, 49, 53, 59 AGND, AVSS Analog Ground. 11 REFIO Tx DAC Band Gap Reference Decoupling Pin. 12 FSADJ Tx DAC Full-Scale Adjust Pin. 14, 15 IOUT+B, IOUT−B DAC B Differential Output. 17 IFACE2

(10/20)

SPI: Buffered CLKIN. Can be configured as system clock output. No SPI: For FD: Buffered CLKIN; For HD20 or HD10 : 10/20

Configuration Pin. 18 IFACE3 Clock Output. 19–28 U9–U0 Upper Data Bit 9 to Upper Data Bit 0. 29 AUX1 Configurable as either AuxADC_A2 or AuxDAC_A. 30 AUX2 Configurable as either AuxADC_A1 or AuxDAC_B. 33 IFACE1

SPI: For FD: TxSYNC; For HD20, HD10, or Clone: Tx/Rx. No SPI: FD >> TxSYNC; HD20 or HD10: Tx/Rx.

Rev. 0 | Page 8 of 52

AD9861

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Pin No. Name

34 AUX_SPI_CLK CLK for AuxSPI. 35–44 L9–L0 Lower Data Bit 9 to Lower Data Bit 0. 45 AUX3 Configurable as either AuxADC_B or AuxDAC_C. 46 47 AUX_ADC_REF Decoupling for AuxADC On-Chip Reference. 48 CLKIN Clock Input. 52 REFB ADC Bottom Reference. 54, 55 VIN+B, VIN−B ADC B Differential Input. 56 VREF ADC Band Gap Reference. 57, 58 VIN−A, VIN+A ADC A Differential Input. 60 REFT ADC Top Reference. 62 RxPwrDwn Rx Analog Power-Down Control. 63 TxPwrDwn Tx Analog Power-Down Control. 64 SPI_CS

1

Underlined pin names and descriptions apply when the device is configured without a serial port interface, referred to as no SPI mode.

2

Pin function depends if the serial port is used to configure the AD9861 (called SPI mode) or if mode pins are used to configure the AD9861 (called No SPI mode). The

differences are indicated by the SPI and No SPI labels in the description column.

3

Some pin descriptions depend on the interface configuration, full-duplex (FD), half-duplex interleaved data (HD10), half-duplex parallel data (HD20), and a half-duplex

interface similar to the AD9860 and AD9862 data interface called clone mode (Clone). Clone mode requires a serial port interface.

RESET

1

Description

Chip Reset When Low.

SPI: Serial Port Chip Select. At power-up or reset, this must be high. No SPI: T

2, 3

ie low to disable SPI and use mode pins. This pin must be tied low.

Rev. 0 | Page 9 of 52

AD9861

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TYPICAL PERFORMANCE CHARACTERISTICS

0 –10 –20 –30 –40 –50 –60 –70

AMPLITUDE (dBFS)

–80 –90

–100 –110

0510

FREQUENCY (MHz)

15 20 25

Figure 4. AD9861-50 Rx Path Single-Tone FFT of Rx Channel B Path

Digitizing 2 MHz Tone

03606-0-031

0 –10 –20 –30 –40 –50 –60 –70

AMPLITUDE (dBFS)

–80 –90

–100

–110

0510

FREQUENCY (MHz)

15 20 25

Figure 7. AD9861-50 Rx Path Dual-Tone FFT of Rx Channel A Path

Digitizing 1 MHz and 2 MHz Tones

03606-0-032

0 –10 –20 –30 –40 –50 –60 –70

AMPLITUDE (dBFS)

–80 –90

–100 –110

0510

FREQUENCY (MHz)

15 20 25

Figure 5. AD9861-50 Rx Path Single-Tone FFT of Rx Channel B Path

Digitizing 5 MHz Tone

0 –10 –20 –30 –40 –50 –60 –70

AMPLITUDE (dBFS)

–80 –90

–100 –110

0510

FREQUENCY (MHz)

15 20 25

Figure 6. AD9861-50 Rx Path Single-Tone FFT of Rx Channel B Path

Digitizing 24 MHz Tone

03606-0-033

03606-0-035

0 –10 –20 –30 –40 –50 –60 –70

AMPLITUDE (dBFS)

–80 –90

–100

–110

0510

FREQUENCY (MHz)

15 20 25

Figure 8. AD9861-50 Rx Path Dual-Tone FFT of Rx Channel A Path

Digitizing 5 MHz and 8 MHz Tones

0 –10 –20 –30 –40 –50 –60 –70

AMPLITUDE (dBFS)

–80 –90

–100

–110

0510

FREQUENCY (MHz)

15 20 25

Figure 9. AD9861-50 Rx Path Dual-Tone FFT of Rx Channel A Path

Digitizing 20 MHz and 25 MHz Tones

03606-0-034

03606-0-036

Rev. 0 | Page 10 of 52

AD9861

www.BDTIC.com/ADI

0 –10 –20 –30 –40 –50 –60 –70

AMPLITUDE (dBFS)

–80 –90

–100 –110

0510

FREQUENCY (MHz)

15 20 25

Figure 10. AD9861-50 Rx Path Single-Tone FFT of Rx Channel B Path

Digitizing 76 MHz Tone

62

59

56

SNR (dBc)

53

50

0510

NORMAL POWER @ 50MSPS

LOW POWER ADC @ 25MSPS

ULTRALOW POWER ADC @ 16MSPS

INPUT FREQUENCY (MHz)

15 20 25

Figure 11. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone

SNR Performance vs. Input Frequency

03606-0-037

03606-0-039

0 –10 –20 –30 –40 –50 –60 –70

AMPLITUDE (dBFS)

–80 –90

–100 –110

0510

FREQUENCY (MHz)

15 20 25

Figure 13. AD9861-50 Rx Path Dual-Tone FFT of Rx Channel A Path

Digitizing 70 MHz and 72 MHz Tones

62

59

56

SINAD (dBc)

53

50

0510

NORMAL POWER @ 50MSPS

LOW POWER ADC @ 25MSPS

ULTRALOW POWER ADC @ 16MSPS

INPUT FREQUENCY (MHz)

15 20 25

Figure 14. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone

SINAD Performance vs. Input Frequency

10.0

9.8

9.6

9.4

9.2

9.0

8.8

8.6

8.4

8.2

8.0

03606-0-038

ENOB (Bits)

03606-0-040

80

75

70

65

SFDR (dBc)

60

55

50

0510

INPUT FREQUENCY (MHz)

LOW POWER ADC @ 25MSPS

NORMAL POWER @ 50MSPS

ULTRALOW POWER ADC @ 16MSPS

15 20 25

Figure 12. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone

SFDR Performance vs. Input Frequency

03606-0-041

Rev. 0 | Page 11 of 52

–50

–55

–60

–65

THD (dBc)

–70

–75

–80

0510

NORMAL POWER @ 50MSPS

LOW POWER ADC @ 25MSPS

INPUT FREQUENCY (MHz)

ULTRALOW POWER ADC @ 16MSPS

15 20 25

Figure 15. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone

THD Performance vs. Input Frequency

03606-0-042

AD9861

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70

60

50

40

30

SNR (dBc)

20

10

0

0 –5 –10 –15 –20 –25 –30 –35

INPUT AMPLITUDE (dBFS)

SNR

Figure 16. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone

SNR Performance vs. Input Amplitude

62

AVE (–40

°

AVE (+85

C)

°

C)

61

60

59

SNR (dBc)

58

57

56

2.7 3.0 3.3 3.6

AVE (+25°C)

ADC_AVDD VOLTAGE (V)

Figure 17. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone

SNR Performance vs. ADC_AVDD and Temperature

IDEAL SNR

–40

–45

03606-0-043

03606-0-045

90 –90

80

70

60

50

SFDR (dBFS)

40

30

20

SFDR

THD

0 –5 –10 –15 –20 –25 –30 –35

INPUT AMPLITUDE (dBFS)

Figure 19. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone

THD and SFDR Performance vs. Input Amplitude

62

61

60

59

SINAD (dBc)

58

57

56

2.7 3.0 3.3

AVE (–40°C)

AVE (+25°C)

AVE (+85°C)

ADC_AVDD VOLTAGE (V)

Figure 20. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone

SINAD Performance vs. ADC_AVDD and Temperature

–40

3.6

–80

–70

–60

–50

–40

–30

–20

10.0

9.9

9.8

9.7

9.6

9.5

9.4

9.3

9.2

9.1

9.0

THD (dBFS)

03606-0-044

ENOB (Bits)

03606-0-046

–70.0

–70.5

–71.0

–71.5

–72.0

–72.5

THD (dBc)

–73.0

–73.5

–74.0

–74.5

–75.0

3.6 3.3 3.0 2.7 INPUT AMPLITUDE (dBFS)

AVE (+85

AVE (+25°C)

AVE (–40

°

C)

Figure 18. AD9861-50 Rx Path Single-Tone THD Performance vs.

ADC_AVDD and Temperature

C)

03606-0-047

Rev. 0 | Page 12 of 52

70

71

72

73

74

SFDR (dBc)

75

76

77

78

3.6 3.3 3.0 INPUT AMPLITUDE (dBFS)

AVE (+85°C)

AVE (+25°C)

AVE (–40°C)

2.7

Figure 21. AD9861-50 Rx Path Single-Tone SFDR Performance vs.

ADC_AVDD and Temperature

03606-0-048

AD9861

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0 –10 –20 –30 –40 –50 –60 –70

AMPLITUDE (dBFS)

–80 –90

–100 –110

0 5 10 15 20 25 30 35

FREQUENCY (MHz)

Figure 22. AD9861-80 Rx Path Single-Tone FFT of Rx Channel B Path

Digitizing 2 MHz Tone

0 –10 –20 –30 –40 –50 –60 –70

AMPLITUDE (dBFS)

–80 –90

–100 –110

0 5 10 15 20 25 30 35

FREQUENCY (MHz)

Figure 23. AD9861-80 Rx Path Single-Tone FFT of Rx Channel B Path

Digitizing 5 MHz Tone

40

03606-0-049

03606-0-051

0 –10 –20 –30 –40 –50 –60 –70

AMPLITUDE (dBFS)

–80 –90

–100 –110

0 5 10 15 20

FREQUENCY (MHz)

25

Figure 25. AD9861-80 Rx Path Dual-Tone FFT of Rx Channel A Path

Digitizing 1 MHz and 2 MHz Tones

0 –10 –20 –30 –40 –50 –60 –70

AMPLITUDE (dBFS)

–80 –90

–100 –110

0 5 10 15 20

FREQUENCY (MHz)

25

Figure 26. AD9861-80 Rx Path Dual-Tone FFT of Rx Channel A Path

Digitizing 5 MHz and 8 MHz Tones

03606-0-050

03606-0-052

0 –10 –20 –30 –40 –50 –60 –70

AMPLITUDE (dBFS)

–80 –90

–100 –110

0 5 10 15 20 25 30 35

FREQUENCY (MHz)

40

Figure 24. AD9861-80 Rx Path Single-Tone FFT of Rx Channel B Path

Digitizing 24 MHz Tone

03606-0-053

Rev. 0 | Page 13 of 52

0 –10 –20 –30 –40 –50 –60 –70

AMPLITUDE (dBFS)

–80 –90

–100 –110

0 5 10 15 20

FREQUENCY (MHz)

25

Figure 27. AD9861-80 Rx Path Dual-Tone FFT of Rx Channel A Path

Digitizing 20 MHz and 25 MHz Tones

03606-0-054

AD9861

www.BDTIC.com/ADI

62

LOW POWER ADC @ 40MSPS

59

NORMAL POWER @ 80MSPS

56

SNR (dBc)

53

50

0 5 10 15 20

Figure 28. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone

SNR Performance vs. Input Frequency and Power Setting

ULTRALOW POWER ADC @ 16MSPS

INPUT FREQUENCY (MHz)

3025

03606-0-055

62 10.0

LOW POWER ADC @ 40MSPS

ULTRALOW POWER ADC @ 16MSPS

59

NORMAL POWER @ 80MSPS

56

SINAD (dBc)

53

50

0 5 10 15 20

INPUT FREQUENCY (MHz)

Figure 31. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone

SINAD Performance vs. Input Frequency and Power Setting

9.8

9.6

9.4

9.2

9.0

8.8

ENOB (Bits)

8.6

8.4

8.2

03606-0-056

8.0

3025

85

LOW POWER ADC @ 40MSPS

80

ULTRALOW POWER

75

70

SFDR (dBc)

NORMAL POWER @ 80MSPS

65

60

0 5 10 15 20

INPUT FREQUENCY (MHz)

ADC @ 16MSPS

Figure 29. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone

SFDR Performance vs. Input Frequency and Power Setting

70

60

50

40

30

SNR (dBc)

20

10

IDEAL SNR

SNR

25

03606-0-057

–50

–55

–60

–65

THD (dBc)

–70

–75

–80

0 5 10 15 20

LOW POWER ADC @ 40MSPS

NORMAL POWER @ 80MSPS

INPUT FREQUENCY (MHz)

ULTRALOW POWER

ADC @ 16MSPS

Figure 32. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone

THD Performance vs. Input Frequency and Power Setting

–80 80

–70

–60

–50

THD (dBFS)

–40

–30

THD

SFDR

25

70

60

50

40

30

03606-0-058

SFDR (dBFS)

0

0 –5 –10 –15 –20 –25 –30 –35

INPUT AMPLITUDE (dBFS)

–40

Figure 30. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone

–45

03606-0-059

SNR Performance vs. Input Amplitude

Rev. 0 | Page 14 of 52

–20

0 –5 –10 –15 –20 –25 –30 –35

INPUT AMPLITUDE (dBFS)

Figure 33. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone

THD Performance vs. Input Amplitude

–40

03606-0-060

20

AD9861

www.BDTIC.com/ADI

62

61

60

59

SNR (dBc)

58

57

56

2.7 3.0 3.3 3.6

AVE (+85°C)

AVE (+25°C)

ADC_AVDD VOLTAGE (V)

AVE (–40°C)

Figure 34. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone

SNR Performance vs. AVDD and Temperature

03606-0-065

62

61

60

59

SINAD (dBc)

58

57

56

2.7 3.0 3.3

AVE (+85

°

C)

AVE (–40

C)

°

C)

AVE (+25

ADC_AVDD VOLTAGE (V)

Figure 37. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone

SINAD Performance vs. AVDD and Temperature

3.6

10.0

9.9

9.8

9.7

9.6

9.5

9.4

9.3

9.2

9.1

9.0

ENOB (Bits)

03606-0-066

70

69

68

67

66

65

THD (dBc)

64

63

62

61

60

2.7 3.0 3.3 3.6 ADC_AVDD VOLTAGE (V)

AVE (+25°C)

AVE (–40°C)

AVE (+85°C)

Figure 35. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone

THD Performance vs. AVDD and Temperature

120

100

80

60

40

ADC AVDD CURRENT (mA)

20

0

04302010

ULP

LP

(MHz)

F

CLK

NORM

0

Figure 36. AD9861-50 ADC_AVDD Current vs. Sampling Rate for

Different ADC Power Levels

50

03606-0-061

03606-0-063

65

66

67

68

69

70

71

SFDR (dBc)

72

73

74

75

2.7 3.0 3.3 3.6 ADC_AVDD VOLTAGE (V)

AVE (+85°C)

AVE (–40°C)

AVE (+25°C)

Figure 38. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone

SFDR Performance vs. AVDD and Temperature

180

160

140

120

100

80

60

ADC AVDD CURRENT (mA)

40

20

0

ULP

0 40506070302010

F

CLK

NORM

LP

80

(MHz)

Figure 39. AD9861-80 ADC_AVDD Current vs. ADC Sampling Rate for

Different ADC Power Levels

03606-0-062

03606-0-064

Rev. 0 | Page 15 of 52

AD9861

www.BDTIC.com/ADI

AMPLITUDE (dBc)

–100 –110

0 –10 –20 –30 –40 –50 –60 –70 –80 –90

0 1015205

FREQUENCY (MHz)

Figure 40. AD9861 Tx Path 1 MHz Single-Tone Output FFT of Tx Path

with 20 mA Full-Scale Output into 33 Ω Differential Load

0 –10 –20 –30 –40 –50 –60 –70

AMPLITUDE (dBc)

–80 –90

–100 –110

01015205

FREQUENCY (MHz)

Figure 41. AD9861 Tx Path 1 MHz Single-Tone Output FFT of Tx Path

with 20 mA Full-Scale Output into 60 Ω Differential Load

25

03606-0-068

03606-0-070

0 –10 –20 –30 –40 –50 –60 –70

AMPLITUDE (dBc)

–80 –90

–100 –110

01015205

FREQUENCY (MHz)

25

Figure 43. AD9861 Tx Path 5 MHz Single-Tone Output FFT of Tx Path

with 20 mA Full-Scale Output into 33 Ω Differential Load

0 –10 –20 –30 –40 –50 –60 –70

AMPLITUDE (dBc)

–80 –90

–100 –110

01015205

FREQUENCY (MHz)

25

Figure 44. AD9861 Tx Path 5 MHz Single-Tone Output FFT of Tx Path

with 20 mA Full-Scale Output into 60 Ω Differential Load

03606-0-069

03606-0-071

0 –10 –20 –30 –40 –50 –60 –70

AMPLITUDE (dBc)

–80 –90

–100 –110

01015205

FREQUENCY (MHz)

25

Figure 42. AD9861 Tx Path 1 MHz Single-Tone Output FFT of Tx Path

with 2 mA Full-Scale Output into 600 Ω Differential Load

03606-0-072

Rev. 0 | Page 16 of 52

0 –10 –20 –30 –40 –50 –60 –70

AMPLITUDE (dBc)

–80 –90

–100 –110

01015205

FREQUENCY (MHz)

25

Figure 45. AD9861 Tx Path 5 MHz Single-Tone Output FFT of Tx Path

with 2 mA Full-Scale Output into 600 Ω Differential Load

03606-0-073