ANALOG DEVICES AD9857 Service Manual

CMOS 200 MSPS 14-Bit

www.BDTIC.com/ADI

FEATURES

200 MHz internal clock rate 14-bit data path Excellent dynamic performance:

80 dB SFDR @ 65 MHz (±100 kHz) A 4× to 20× programmable reference clock multiplier Reference clock multiplier PLL lock detect indicator Internal 32-bit quadrature DDS FSK capability 8-bit output amplitude control Single-pin power-down function Four programmable, pin-selectable signal profiles SIN(x)/x correction (inverse SINC function) Simplified control interface

10 MHz serial, 2-wire or 3-wire SPI®-compatible

INVERSE

CIC FILTER

PARALLEL

DATA IN

(14-BIT)

DEMUX

DATA CLOCK

INV CIC

INVERSE CIC CLOCK

OUT

POLATOR

MUX

INVERSE CIC CONTROL

FUNCTIONAL BLOCK DIAGRAM

FIXED

INTER-

PROGRAMMABLE

INTERPOLATOR

(4 )

HALF-BAND CLOCKS

CONTROL REGISTERS

CIC

- 63 )

INTERP CLOCK

INTERP CONTROL

Quadrature Digital Upconverter

AD9857

3.3 V single supply Single-ended or differential input reference clock 80-lead LQFP surface-mount packaging Three modes of operation:

Quadrature modulator mode Single-tone mode Interpolating DAC mode

APPLICATIONS

HFC data, telephony, and video modems Wireless base station Agile, LO frequency synthesis Broadband communications

QUADRATURE

MODULATOR

MUX

SIN

COS

DDS

CORE

TUNING

WORD

TIMING AND CONTROL

MUX

CLOCK

INVERSE

SINC

FILTER

INVERSE

SINC CLOCK

AD9857

MUX

OUTPUT

SCALE VALUE

14-BIT

DAC

DAC CLOCK

DAC_RSET

IOUT IOUT

POWER-

DOWN LOGIC

PDCLK/

TxENABLE

FUD

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

RESET CIC

OVERFLOW

SERIAL

PORT

DIGITAL POWER-

DOWN

PROFILE

SELECT

LOGIC

Figure 1.

SYNCH

SYSCLK

MUX

CLOCK

MULTIPLIER

– 20 )

PS0PS1

PLL

LOCK

MODE

CONTROL

CLOCK

INPUT MODE

REFCLK

01018-C-001

AD9857

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TABLE OF CONTENTS

Revision History ............................................................................... 3

General Description......................................................................... 4

Specifications..................................................................................... 5

Absolute Maximum Ratings............................................................ 8

Explanation of Test Levels........................................................... 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ........................................... 11

Modulated Output Spectral Plots............................................. 11

Single-Tone Output Spectral Plots ........................................... 12

Narrow-band SFDR Spectral Plots........................................... 13

Output Constellations................................................................ 14

Modes Of Operation ...................................................................... 15

Quadrature Modulation Mode .................................................15

Single-Tone Mode ...................................................................... 16

Interpolating DAC Mode .......................................................... 17

Signal Processing Path ...................................................................18

Input Data Assembler ................................................................ 18

Inverse CIC Filter....................................................................... 19

Programmable (2× to 63×) CIC Interpolating Filter............. 21

Quadrature Modulator .............................................................. 21

DDS Core..................................................................................... 21

Inverse SINC Filter .....................................................................22

Output Scale Multiplier .............................................................22

14-Bit D/A Converter ................................................................ 22

Reference Clock Multiplier .......................................................23

Input Data Programming.............................................................. 24

Control Interface—Serial I/O................................................... 24

General Operation of the Serial Interface............................... 24

Instruction Byte.......................................................................... 26

Serial Interface Port Pin Descriptions..................................... 26

Control Register Descriptions.................................................. 27

Profile #0...................................................................................... 27

Profile #1...................................................................................... 28

Profile #2...................................................................................... 28

Profile #3...................................................................................... 28

Latency......................................................................................... 30

Ease of Use Features....................................................................... 32

Profile Select................................................................................ 32

Setting the Phase of the DDS.................................................... 32

Reference Clock Multiplier....................................................... 32

PLL Lock...................................................................................... 32

Single or Differential Clock ...................................................... 33

CIC Overflow Pin....................................................................... 33

Clearing the CIC Filter .............................................................. 33

Digital Power-Down.................................................................. 33

Hardware-Controlled Digital Power-Down ........................... 34

Software-Controlled Digital Power-Down............................. 34

Full Sleep Mode .......................................................................... 34

Power Management Considerations........................................ 34

Support ........................................................................................ 35

Outline Dimensions....................................................................... 38

Ordering Guide .......................................................................... 39

Rev. C | Page 2 of 40

AD9857

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REVISION HISTORY

5/04−Data Sheet Changed from Rev. B to Rev. C

Changes to 14-Bit D/A Converter Section ..................................22

Changes to Register Address 0Ch, Bit 1 Equation ......................28

Changes to Register Address 12h, Bit 1 Equation.......................28

Changes to Register Address 18h, Bit 1 Equation.......................28

Added Support Section...................................................................35

Updated Figure 38...........................................................................38

Updated Ordering Guide ...............................................................39

4/02—Changed from Rev. A to Rev. B

Edit to Functional Block Diagram..................................................1

Edits to Specifications.......................................................................3

Edits to Figure 5 ................................................................................6

Edits to Figure 18 ............................................................................11

Edits to Figure 19 ............................................................................12

Edits to Figure 20 ............................................................................13

Edits to Figure 25 ........................................................................... 16

Edits to Figure 26 ............................................................................16

Edit to Equation 1 ...........................................................................16

Edit to Figure 28..............................................................................19

Edit to Notes on Serial Port Operation section...........................21

Edit to Figure 37..............................................................................31

Rev. C| Page 3 of 40

AD9857

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GENERAL DESCRIPTION

The AD9857 integrates a high speed direct digital synthesizer (DDS), a high performance, high speed, 14-bit digital-to-analog converter (DAC), clock multiplier circuitry, digital filters, and other DSP functions onto a single chip, to form a complete quadrature digital upconverter device. The AD9857 is intended to function as a universal I/Q modulator and agile upconverter, single-tone DDS, or interpolating DAC for communications applications, where cost, size, power dissipation, and dynamic performance are critical attributes.

The AD9857 offers enhanced performance over the industryst

andard AD9856, as well as providing additional features.

The AD9857 is available in a space-saving, surface-mount p

ackage and is specified to operate over the extended industrial

temperature range of −40°C to +85°C.

Rev. C | Page 4 of 40

AD9857

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SPECIFICATIONS

VS = 3.3 V ± 5%, R

Table 1.

Parameter Temp Test Level Min Typ Max Unit

REF CLOCK INPUT CHARACTERISTICS

Frequency Range

REFCLK Multiplier Disabled Full VI 1 200 MHz REFCLK Multiplier Enabled at 4× Full VI 1 50 MHz

REFCLK Multiplier Enabled at 20× Full VI 1 10 MHz Input Capacitance 25°C V 3 pF Input Impedance 25°C V 100 MΩ Duty Cycle 25°C V 50 % Duty Cycle with REFCLK Multiplier Enabled 25°C V 35 65 % Differential Input (VDD/2) ±200 mV 25°C V 1.45 1.85 V

DAC OUTPUT CHARACTERISTICS

Resolution 14 Bits Full-Scale Output Current 5 10 20 mA Gain Error 25°C I 8.5 0 % FS Output Offset 25°C I 2 µA Differential Nonlinearity 25°C V 1.6 LSB Integral Nonlinearity 25°C V 2 LSB Output Capacitance 25°C V 5 pF Residual Phase Noise @ 1 kHz Offset, 40 MHz A

REFCLK Multiplier Enabled at 20× 25°C V −107 dBc/Hz

REFCLK Multiplier at 4× 25°C V −123 dBc/Hz

REFCLK Multiplier Disabled 25°C V −145 dBc/Hz Voltage Compliance Range 25°C I −0.5 +1.0 V Wideband SFDR

1 MHz to 20 MHz Analog Out 25°C V −75 dBc

20 MHz to 40 MHz Analog Out 25°C V −65 dBc

40 MHz to 60 MHz Analog Out 25°C V −62 dBc

60 MHz to 80 MHz Analog Out 25°C V −60 dBc Narrowband SFDR

10 MHz Analog Out (±1 MHz) 25°C V −87 dBc

10 MHz Analog Out (±250 kHz) 25°C V −88 dBc

10 MHz Analog Out (±50 kHz) 25°C V −92 dBc

10 MHz Analog Out (±10 kHz) 25°C V −94 dBc

65 MHz Analog Out (±1 MHz) 25°C V −86 dBc

65 MHz Analog Out (±250 kHz) 25°C V −86 dBc

65 MHz Analog Out (±50 kHz) 25°C V −86 dBc

65 MHz Analog Out (±10 kHz) 25°C V −88 dBc

80 MHz Analog Out (±1 MHz) 25°C V −85 dBc

80 MHz Analog Out (±250 kHz) 25°C V −85 dBc

80 MHz Analog Out (±50 kHz) 25°C V −85 dBc

80 MHz Analog Out (±0 kHz) 25°C V −86 dBc

= 1.96 kΩ, external reference clock frequency = 10 MHz with REFCLK multiplier enabled at 20×.

SET

OUT

Rev. C| Page 5 of 40

AD9857

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Parameter Temp Test Level Min Typ Max Unit

MODULATOR CHARACTERISTICS (65 MHz A

(Input data: 2.5 MS/s, QPSK, 4× oversampled, inverse SINC filter ON, inverse CIC ON)

I/Q Offset 25°C IV 55 65 dB Error Vector Magnitude 25°C IV 0.4 1 %

INVERSE SINC FILTER (variation in gain from DC to 80 MHz,

inverse SINC filter ON)

SPURIOUS POWER (off channel, measured in equivalent

bandwidth), Full-Scale Output

6.4 MHz Bandwidth 25°C IV −65 dBc

3.2 MHz Bandwidth 25°C IV −67 dBc

1.6 MHz Bandwidth 25°C IV −69 dBc

0.8 MHz Bandwidth 25°C IV −69 dBc

0.4 MHz Bandwidth 25°C IV −70 dBc

0.2 MHz Bandwidth 25°C IV −72 dBc

SPURIOUS POWER (Off channel, measured in equivalent

bandwidth), Output Attenuated 18 dB Relative to Full Scale

6.4 MHz Bandwidth 25°C IV −51 dBc

3.2 MHz Bandwidth 25°C IV −54 dBc

1.6 MHz Bandwidth 25°C IV −56 dBc

0.8 MHz Bandwidth 25°C IV −59 dBc

0.4 MHz Bandwidth 25°C IV −62 dBc

0.2 MHz Bandwidth 25°C IV −63 dBc

TIMING CHARACTERISTICS

Serial Control Bus

Maximum Frequency 25°C I 10 MHz Minimum Clock Pulse Width Low (t Minimum Clock Pulse Width High (t Maximum Clock Rise/Fall Time 25°C I 1 ms Minimum Data Setup Time (tDS) 25°C I 30 ns Minimum Data Hold Time (tDH) 25°C I 0 ns Maximum Data Valid Time (tDV) 25°C I 35 ns Wake-Up Time1 25°C I 1 ms Minimum RESET Pulse Width High (tRH) 25°C I 5 SYSCLK22Cycles

Minimum CS Setup Time

CMOS LOGIC INPUTS

Logic 1 Voltage 25°C IV 2.0 V Logic 0 Voltage 25°C IV 0.8 V Logic 1 Current 25°C I 5 µA Logic 0 Current 25°C I 5 µA Input Capacitance 25°C V 3 pF

CMOS LOGIC OUTPUTS (1 mA LOAD)

Logic 1 Voltage 25°C I 2.7 V Logic 0 Voltage 25°C I 0.4 V

)

OUT

) 25°C I 30 ns

PWL

) 25°C I 30 ns

PWH

25°C V ±0.1 dB

25°C I 40 ns

Rev. C | Page 6 of 40

AD9857

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Parameter Temp Test Level Min Typ Max Unit

POWER SUPPLY VSCURRENT3 (all power specifications at

= 3.3 V, 25°C, REFCLK = 200 MHz)

Full Operating Conditions 25°C I 540 615 mA 160 MHz Clock (×16) 25°C I 445 515 mA 120 MHz Clock (×12) 25°C I 345 400 mA Burst Operation (25%) 25°C I 395 450 mA Single-Tone Mode 25°C I 265 310 mA Power-Down Mode 25°C I 71 80 mA Full-Sleep Mode 25°C I 8 13.5 mA

Wake-up time refers to recovery from full-sleep mode. The longest time required is for the reference clock multiplier PLL to lock up (if it is being used). The wake-up

time assumes that there is no capacitor on DAC_BP, and that the recommended PLL loop filter values are used. The state of the reference clock multiplier lock can be determined by observing the signal on the PLL_LOCK pin.

SYSCLK refers to the actual clock frequency used on-chip by the AD9857. If the reference clock multiplier is used to multiply the external reference frequency, the

SYSCLK frequency is the external frequency multiplied by the reference clock multiplier multiplication factor. If the reference clock multiplier is not used, the SYSCLK frequency is the same as the external REFCLK frequency.

CIC = 2, INV SINC ON, FTW = 40%, PLL OFF, auto power-down between burst On, TxENABLE duty cycle = 25%.

Rev. C| Page 7 of 40

AD9857

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ABSOLUTE MAXIMUM RATINGS

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Table 2.

Parameter Rating

Maximum Junction Temperature 150°C V

Digital Input Voltage −0.7 V to +V Digital Output Current 5 mA Storage Temperature −65°C to +150°C Operating Temperature −40°C to +85°C Lead Temperature (Soldering 10 s) 300°C θ

4 V

35°C/W 16°C/W

EXPLANATION OF TEST LEVELS

Table 3.

Test Level

1 100% production tested. 2

3 Sample tested only. 4

5 Parameter is a typical value only. 6

100% production tested at 25°C and sample tested at specific temperatures.

Parameter is guaranteed by design and characterization testing.

Devices are 100% production tested at 25°C and guaranteed by design and characterization testing for industrial operating temperature range.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. C | Page 8 of 40

AD9857

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

RESET

DPD

AGND

AVDD

REFCLK

AVDD

AGND

DIFFCLKEN

AGND

AVDD

AGND

PLL_FILTER

AVDD

AGND

DAC_RSET

DAC_BP

AVDD

AGND

IOUT

AGND

AVDD

AGND

01018-C-000

TxENABLE

PDCLK/FUD

DGND

DVDD

DGND

CIC_OVRFL

DVDD

DGND

PLL_LOCK

34 35 36 37 38 39 40

AVDD

DVDD

AGND

64 63 62 6167 66 65

D13 D12 D11 D10

D9 D8

D7 DVDD DVDD DVDD DGND DGND DGND

NC = NO CONNECT

80 79 78 77 76 71 70 69 6875 74 73 72

PIN 1

INDICATOR 3 4 5 6 7 8 9

10 11 12 13 14 15 16 17 18 19 20

21 22 23 24 25 26 27 28 29 30 31 32 33

PS1

PS0

SDIO

SCLK

SDO

SYNCIO

AD9857

TOP VIEW

(Not to Scale)

DGND

Figure 2. Pin Configuration

Table 4. Pin Function Descriptions

Pin Number Mnemonic I/O Function

20–14, 7–1

D0–D6, D7– D13

14-Bit Parallel Data Bus for I and Q Data. The required numeric format is twos complement with D13 as the sign bit and D12–D0 as the magnitude bits. Alternating 14-bit words are demultiplexed onto the I and Q data pathways (except when operating in the interpolating DAC mode, in which case every word is routed onto the I data path). When the TxENABLE pin is asserted high, the next

accepted word is presumed to be I data, the next Q data, and so forth.

8–10, 31–33,

DVDD 3.3 V Digital Power pin(s).

73–75 11–13, 28–30,

DGND Digital Ground pin(s).

70–72, 76–78 21 PS1 I

Profile Select Pin 1. The LSB of the two profile select pins. In conjunction with PS0, selects one of four profile configurations.

22 PS0 I

Profile Select Pin 0. The MSB of the two profile select pins. In conjunction with P1, selects one of four profile configurations.

Serial Port Chip Select pin. An active low signal that allows multiple devices to operate on a single

serial bus. 24 SCLK I Serial Port Data Clock pin. The serial data CLOCK for the serial port. 25 SDIO I/O

Serial Port Input/Output Data pin. Bidirectional serial DATA pin for the serial port. This pin can be

programmed to operate as a serial input only pin, via the control register bit 00h<7>. The default

state is bidirectional. 26 SDO O

Serial Port Output Data pin. This pin serves as the serial data output pin when the SDIO pin is

configured for serial input only mode. The default state is three-state. 27 SYNCIO I

Serial Port Synchronization pin. Synchronizes the serial port without affecting the programmable

NC No connect.

Rev. C| Page 9 of 40

AD9857

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Pin Number Mnemonic I/O Function

35, 37, 38, 43, 48, 54, 58, 64

36, 39, 40, 42, 44, 47, 53, 56, 59, 61, 65

45 IOUT O DAC Output pin. Normal DAC output current (analog). 46 49 DAC_BP DAC Reference Bypass. Typically not used. 50 DAC_RSET I DAC Current Set pin. Sets DAC reference current. 55 PLL_FILTER O PLL Filter. R-C network for PLL filter. 60 DIFFCLKEN I

62 REFCLK I

63 66 DPD I

67 RESET I Hardware RESET pin. An active high input that forces the device into a predefined state. 68 PLL_LOCK O PLL Lock pin. Active high output signifying, in real time, when PLL is in lock state. 69 CIC_OVRFL O

79 PDCLK/FUD I/O

80 TxENABLE I

AVDD 3.3 V Analog Power pin(s).

AGND Analog Ground pin(s).

IOUT

REFCLK

O DAC Complementary Output pin. Complementary DAC output current (analog).

Clock Mode Select pin. A logic high on this pin low selects the SINGLE-ENDED REFCLK input mode.

Reference Clock pin. In single-ended clock mode, this pin is the clock mode, this pin is the positive clock input.

I Inverted Reference Clock pin. In differential clock mode, this pin is the negative clock input.

Digital Power-Down pin. Assertion of this pin shuts down the di conserve power. However, if selected, the PLL remains operational.

CIC Overflow pin. Activity on this pin indicates that the CIC Filters are in “overf typically low unless a CIC overflow occurs.

Parallel Data Clock/Frequency Update pin. When not in single-t signal that should be used as a clock to synchronize the acceptance of the 14-bit parallel data-words on Pins D13–D0. In single-tone mode, this pin is an input signal that synchronizes the transfer of a changed frequency tuning word (FTW) in the active profile (PSx) to the accumulator (FUD = frequency update signal). When profiles are changed by means of the PS–PS1 pins, the FUD does not have to be asserted to make the FTW active.

When TxENABLE is asserted, the device processes the data through the I and otherwise 0s are internally substituted for the I and Q data entering the signal path. The first data word accepted when the TxENABLE is asserted high is treated as I data, the next data word is Q data, and so forth.

selects DIFFERENTIAL REFCLK input mode. A logic

Reference Clock input. In differential

gital sections of the device to

low” state. This pin is

one mode, this pin is an output

Q data pathways;

Rev. C | Page 10 of 40

AD9857

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TYPICAL PERFORMANCE CHARACTERISTICS

MODULATED OUTPUT SPECTRAL PLOTS

–10

–20 –30

–40

–50

–60 –70 –80

–90

–100

START 0Hz 5MHz/ STOP 50MHz

Figure 3. QPSK at 42 MHz and 2.56 MS/s; 10.24 MHz External Clock

with REFCLK Multiplier = 12, CIC Interpolation Rate = 3,

4× Oversampled Data

–8

–16 –24

–32

–40

–48 –56

–64

–72

–80

START 0Hz 4MHz/ STOP 40MHz

Figure 4. 64-QAM at 28 MHz and 6 MS/s; 36 MHz External Clock

with REFCLK Multiplier = 4, CIC Interpolation Rate = 2,

3× Oversampled Data

01018-C-003

01018-C-004

–10

–20 –30

–40

–50

–60 –70

–80

–90

–100

START 0Hz 8MHz/ STOP 80MHz

Figure 5. 16-QAM at 65 MHz and 1.28 MS/s; 10.24 MHz External Clock

with REFCLK Multiplier = 18, CIC Interpolation Rate = 9,

4× Oversampled Data

–8

–16 –24

–32

–40

–48 –56

–64

–72

–80

START 0HzSTART 0Hz 5MHz/ STOP 50MHz

Figure 6. 256-QAM at 38 MHz and 6 MS/s; 48 MHz External Clock

with REFCLK Multiplier = 4, CIC Interpolation Rate = 2,

4× Oversampled Data

01018-C-005

01018-C-006

Rev. C| Page 11 of 40

AD9857

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SINGLE-TONE OUTPUT SPECTRAL PLOTS

–10

–20 –30

–40

–50

–60 –70

–80

–90

–100

START 0Hz 10MHz/ STOP 100MHz

Figure 7. 21 MHz Single-Tone Output

–10

–20 –30

–40

–50

–60 –70

–80

–90

–100

START 0Hz

Figure 8. 65 MHz Single-Tone Output

10MHz/ STOP 100MHz

01018-C-007

01018-C-008

–10

–20 –30

–40

–50

–60 –70

–80

–90

–100

START 0Hz 10MHz/ STOP 100MHz

Figure 9. 42 MHz Single-Tone Output

–10

–20 –30

–40

–50

–60 –70

–80

–90

–100

START 0Hz 10MHz/ STOP 100MHz

Figure 10. 79 MHz Single-Tone Output

01018-C-009

01018-C-010

Rev. C | Page 12 of 40

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