ANALOG DEVICES AD9854 Service Manual

CMOS 300 MSPS Quadrature

FEATURES

300 MHz internal clock rate
FSK, BPSK, PSK, chirp, AM operation
Dual integrated 12-bit digital-to-analog converters (DACs)
Ultrahigh speed comparator, 3 ps rms jitter
Excellent dynamic performance

80 dB SFDR at 100 MHz (±1 MHz) A
4× to 20× programmable reference clock multiplier
Dual 48-bit programmable frequency registers
Dual 14-bit programmable phase offset registers
12-bit programmable amplitude modulation and

on/off output shaped keying function
Single-pin FSK and BPSK data interfaces
PSK capability via input/output interface
Linear or nonlinear FM chirp functions with single-pin

frequency hold function
Frequency-ramped FSK
<25 ps rms total jitter in clock generator mode

REFERENCE

CLOCK IN

DIFF/SINGLE

SELECT

FSK/BPSK/HOLD

DATA IN

BIDIRECT IONAL

INTERNAL /EXT ERNAL

I/O UPDATE CL OCK

REF
CLK

BUFFER

SYSTEM

CLOCK

DEMUX

2

FREQUENCY

MODE SELECT

SYSTEM

CLOCK

INT

4× TO 20×

REF CLK

MULTIPLIER

MUX

3

DELTA

FREQUENCY

RATE TIMER

48 48 48 14

SYSTEM

CLOCK

DELTA

WORD

CK

Q

D

EXT

OUT

SYSTEM CLOCK

FREQUENCY

ACCUMULATOR

MUX

FREQUENCY

TUNING
WORD 1

÷2

INTERNAL

PROGRAMMABLE

UPDATE CLOCK

FUNCTIONAL BLOCK DIAGRAM

48

48

ACC 1

48

MUX

FREQUENCY

TUNING
WORD 2

PROGRAMMING REGISTERS

SYSTEM
CLOCK

Automatic bidirectional frequency sweeping
Sin(x)/x correction
Simplified control interfaces

10 MHz serial 2- or 3-wire SPI compatible
100 MHz parallel 8-bit programming

3.3 V single supply
Multiple power-down functions
Single-ended or differential input reference clock
Small, 80-lead LQFP or TQFP with exposed pad

APPLICATIONS

Agile, quadrature LO frequency synthesis
Programmable clock generators
FM chirp source for radar and scanning systems
Test and measurement equipment
Commercial and amateur RF exciters

DDS CORE

17

17

ACC 2

PHASE

ACCUMULATO R

MUX

FIRST 14-BIT

PHASE/OFFSET

WORD

READ WRITE SERIAL/

Figure 1.

14

AD9854

PHASE-TO -

SYSTEM

SECOND 14-BIT

PHASE/OFFSET

12

I

12

AMPLITUDE

CONVERTE R

Q

CLOCK

14

WORD

PARALLEL

SELECT

DIGITAL MULTIPLIERS

INV

SINC

FILTER

MUX

INV

SINC

FILTER

MUX

PROGRAMMABLE

AMPLIT UDE AND

RATE CONTROL

12

12

I AND Q 12-BIT

AM MODUL ATIO N

I/O PORT BUFFERS

6-BIT ADDRESS

OR SERIAL

PROGRAMMING

LINES

12

BUS

Complete DDS

AD9854

12

12-BIT

I

DAC

12-BIT
Q DAC OR
CONTROL

DAC

COMPARATOR

MASTER

RESET

SYSTEM

CLOCK

12

12-BIT DC

CONTROL

MUX

12

MUX

8-BIT

PARALLEL

LOAD

ANALOG
OUT

DAC R

ANALOG
OUT

ANALOG
IN

CLOCK
OUT

OSK

GND

+V

S

SET

0636-001

Rev. E

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2002–2007 Analog Devices, Inc. All rights reserved.

AD9854

TABLE OF CONTENTS

Features.............................................................................................. 1

Programming the AD9854............................................................ 32

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

General Description ......................................................................... 4

Specifications..................................................................................... 5

Absolute Maximum Ratings............................................................ 8

Thermal Resistance ...................................................................... 8

Explanation of Test Levels........................................................... 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ........................................... 12

Typical Applications....................................................................... 16

Theory of Operation ...................................................................... 19

Modes of Operation ................................................................... 19

Using the AD9854 .......................................................................... 29

MASTER RESET........................................................................ 32

Parallel I/O Operation............................................................... 34

Serial Port I/O Operation.......................................................... 34

General Operation of the Serial Interface................................... 36

Instruction Byte.......................................................................... 37

Serial Interface Port Pin Descriptions..................................... 37

Notes on Serial Port Operation ................................................ 37

MSB/LSB Transfers......................................................................... 38

Control Register Description.................................................... 38

Power Dissipation and Thermal Considerations....................... 40

Thermal Impedance................................................................... 40

Junction Temperature Considerations .................................... 40

Evaluation of Operating Conditions........................................ 41

Thermally Enhanced Package Mounting Guidelines................ 41

Evaluation Board............................................................................ 42

Internal and External Update Clock ........................................ 29

On/Off Output Shaped Keying (OSK) .................................... 29

I and Q DACs.............................................................................. 30

Control DAC............................................................................... 30

Inverse Sinc Function ................................................................31

REFCLK Multiplier.................................................................... 31

Evaluation Board Instructions.................................................. 42

General Operating Instructions ............................................... 42

Using the Provided Software .................................................... 44

Support ........................................................................................ 44

Outline Dimensions....................................................................... 52

Ordering Guide .......................................................................... 52

Rev. E | Page 2 of 52

AD9854

REVISION HISTORY

7/07—Rev. D to Rev. E

Changed AD9854ASQ to AD9854ASVZ ....................... Universal

Changed AD9854AST to AD9854ASTZ.........................Universal

Changes to General Description .....................................................4

Changes to Table 1 Endnotes...........................................................7

Changes to Absolute Maximum Ratings Section..........................8

Changes to Power Dissipation Section.........................................40

Changes to Thermally Enhanced Package Mounting

Guidelines Section......................................................................41

Changes to Figure 64 ......................................................................47

Changes to Outline Dimensions ...................................................52

Changes to Ordering Guide...........................................................52

11/06—Rev. C to Rev. D

Changes to General Description Section .......................................4

Changes to Endnotes in the Power Supply Parameter .................7

Changes to Absolute Maximum Ratings Section..........................8

Added Endnotes to Table 2..............................................................8

Changes to Figure 50 ......................................................................29

Changes to Power Dissipation Section.........................................39

Changes to Figure 68 ......................................................................45

Updated Outline Dimensions........................................................51

Changes to Ordering Guide...........................................................51

9/04—Rev. B to Rev. C

Updated Format.................................................................. Universal

Changes to Table 1 ............................................................................4

Changes to Footnote 2......................................................................7

Changes to Explanation of Test Levels Section .............................8

Changes to Theory of Operation Section ....................................17

Changes to Single Tone (Mode 000) Section...............................17

Changes to Ramped FSK (Mode 010) Section............................18

Changes to Basic FM Chirp Programming Steps Section.........23

Changes to Figure 50 ......................................................................27

Changes to Evaluation Board Operating Instructions Section.40
Changes to Filtered IOUT1 and the Filtered IOUT2 Section ...41

Changes to Using the Provided Software Section.......................42

Changes to Figure 68 ......................................................................45

Changes to Figure 69 ......................................................................46

Updated Outline Dimensions........................................................50

Changes to Ordering Guide...........................................................50

3/02—Rev. A to Rev. B

Updated Format ................................................................. Universal

Renumbered Figures and Tables ...................................... Universal

Changes to General Description Section.......................................1

Changes to Functional Block Diagram .......................................... 1

Changes to Specifications Section ..................................................4

Changes to Absolute Maximum Ratings Section .........................7

Changes to Pin Function Descriptions ..........................................8

Changes to Figure 3 ........................................................................10

Deleted two Typical Performance Characteristics Graphs........11

Changes to Inverse SINC Function Section ................................28

Changes to Differential REFCLK Enable Section.......................28

Changes to Figure 52 ......................................................................30

Changes to Parallel I/O Operation Section .................................32

Changes to General Operation of the Serial Interface Section .33

Changes to Figure 57 ......................................................................34

Replaced Operating Instructions Section ....................................40

Changes to Figure 68 ......................................................................44

Changes to Figure 69 ......................................................................45

Changes to Customer Evaluation Board Table............................46

Rev. E | Page 3 of 52

AD9854

GENERAL DESCRIPTION

The AD9854 digital synthesizer is a highly integrated device
that uses advanced DDS technology, coupled with two internal
high speed, high performance quadrature DACs to form a digitally
programmable I and Q synthesizer function. When referenced
to an accurate clock source, the AD9854 generates highly stable,
frequency-phase, amplitude-programmable sine and cosine
outputs that can be used as an agile LO in communications, radar,
and many other applications. The innovative high speed DDS core
of the AD9854 provides 48-bit frequency resolution (1 Hz tuning
resolution with 300 MHz SYSCLK). Maintaining 17 bits ensures
excellent SFDR.

The circuit architecture of the AD9854 allows the generation of
simultaneous quadrature output signals at frequencies up to
150 MHz, which can be digitally tuned at a rate of up to
100 million new frequencies per second. The sine wave output
(externally filtered) can be converted to a square wave by the
internal comparator for agile clock generator applications.
The device provides two 14-bit phase registers and a single pin
for BPSK operation.

For higher-order PSK operation, the I/O interface can be used
for phase changes. The 12-bit I and Q DACs, coupled with the
innovative DDS architecture, provide excellent wideband and
narrow-band output SFDR. The Q DAC can also be configured

as a user-programmable control DAC if the quadrature function
is not desired. When configured with the comparator, the 12-bit
control DAC facilitates static duty cycle control in high speed
clock generator applications.

Two 12-bit digital multipliers permit programmable amplitude
modulation, on/off output shaped keying, and precise amplitude
control of the quadrature output. Chirp functionality is also
included to facilitate wide bandwidth frequency sweeping
applications. The programmable 4× to 20× REFCLK multiplier
circuit of the AD9854 internally generates the 300 MHz system
clock from an external lower frequency reference clock. This
saves the user the expense and difficulty of implementing a
300 MHz system clock source.

Direct 300 MHz clocking is also accommodated with either single­ended or differential inputs. Single-pin conventional FSK and
the enhanced spectral qualities of ramped FSK are supported.
The AD9854 uses advanced 0.35 µm CMOS technology to
provide a high level of functionality on a single 3.3 V supply.

The AD9854 is pin-for-pin compatible with the AD9852 single­tone synthesizer. It is specified to operate over the extended
industrial temperature range of −40°C to +85°C.

Rev. E | Page 4 of 52

AD9854

SPECIFICATIONS

VS = 3.3 V ± 5%, R
external reference clock frequency = 20 MHz with REFCLK multiplier enabled at 10× for AD9854ASTZ, unless otherwise noted.

Table 1.

AD9854ASVZ AD9854ASTZ
Parameter Temp

REFERENCE CLOCK INPUT CHARACTERISTICS

Internal System Clock Frequency Range

REFCLK Multiplier Enabled Full VI 20 300 20 200 MHz
REFCLK Multiplier Disabled Full VI DC 300 DC 200 MHz

External Reference Clock Frequency Range

REFCLK Multiplier Enabled Full VI 5 75 5 50 MHz

REFCLK Multiplier Disabled Full VI DC 300 DC 200 MHz
Duty Cycle 25°C IV 45 50 55 45 50 55 %
Input Capacitance 25°C IV 3 3 pF
Input Impedance 25°C IV 100 100 kΩ
Differential Mode Common-Mode Voltage Range

Minimum Signal Amplitude

Common-Mode Range 25°C IV 1.6 1.75 1.9 1.6 1.75 1.9 V
VIH (Single-Ended Mode) 25°C IV 2.3 2.3 V
VIL (Single-Ended Mode) 25°C IV 1 1 V

DAC STATIC OUTPUT CHARACTERISTICS

Output Update Speed Full I 300 200 MSPS
Resolution 25°C IV 12 12 Bits
I and Q Full-Scale Output Current 25°C IV 5 10 20 5 10 20 mA
I and Q DAC DC Gain Imbalance
Gain Error 25°C I −6 +2.25 −6 +2.25 % FS
Output Offset 25°C I 2 2 μA
Differential Nonlinearity 25°C I 0.3 1.25 0.3 1.25 LSB
Integral Nonlinearity 25°C I 0.6 1.66 0.6 1.66 LSB
Output Impedance 25°C IV 100 100 kΩ
Voltage Compliance Range 25°C I −0.5 +1.0 −0.5 +1.0 V

DAC DYNAMIC OUTPUT CHARACTERISTICS

I and Q DAC Quadrature Phase Error 25°C IV 0.2 1 0.2 1 Degrees
DAC Wideband SFDR

1 MHz to 20 MHz A

20 MHz to 40 MHz A

40 MHz to 60 MHz A

60 MHz to 80 MHz A

80 MHz to 100 MHz A

100 MHz to 120 MHz A
DAC Narrow-Band SFDR

10 MHz A

10 MHz A

10 MHz A

41 MHz A

41 MHz A

41 MHz A

119 MHz A

119 MHz A

119 MHz A

= 3.9 kΩ, external reference clock frequency = 30 MHz with REFCLK multiplier enabled at 10× for AD9854ASVZ,

SET

Te st
Level

1

2

3

25°C V 58 58 dBc

OUT

25°C V 56 56 dBc

OUT

25°C V 52 52 dBc

OUT

25°C V 48 48 dBc

OUT

25°C V 48 48 dBc

OUT

25°C V 48 48 dBc

OUT

(±1 MHz) 25°C V 83 83 dBc

OUT

(±250 kHz) 25°C V 83 83 dBc

OUT

(±50 kHz) 25°C V 91 91 dBc

OUT

(±1 MHz) 25°C V 82 82 dBc

OUT

(±250 kHz) 25°C V 84 84 dBc

OUT

(±50 kHz) 25°C V 89 89 dBc

OUT

(±1 MHz) 25°C V 71 71 dBc

OUT

(±250 kHz) 25°C V 77 77 dBc

OUT

(±50 kHz) 25°C V 83 83 dBc

OUT

25°C IV 400 400 mV p-p

25°C I −0.5 +0.15 +0.5 −0.5 +0.15 +0.5 dB

Min Typ Max Min Typ Max Unit

Rev. E | Page 5 of 52

AD9854

AD9854ASVZ AD9854ASTZ
Parameter Temp

Residual Phase Noise

(A

= 5 MHz, External Clock = 30 MHz

OUT

REFCLK Multiplier Engaged at 10×)

1 kHz Offset 25°C V 140 140 dBc/Hz
10 kHz Offset 25°C V 138 138 dBc/Hz
100 kHz Offset 25°C V 142 142 dBc/Hz

(A

= 5 MHz, External Clock = 300 MHz,

OUT

REFCLK Multiplier Bypassed)

1 kHz Offset 25°C V 142 142 dBc/Hz
10 kHz Offset 25°C V 148 148 dBc/Hz
100 kHz Offset 25°C V 152 152 dBc/Hz

PIPELINE DELAYS

DDS Core (Phase Accumulator and

4, 5, 6

25°C IV 33 33 SYSCLK cycles

Phase-to-Amp Converter)
Frequency Accumulator 25°C IV 26 26 SYSCLK cycles
Inverse Sinc Filter 25°C IV 16 16 SYSCLK cycles
Digital Multiplier 25°C IV 9 9 SYSCLK cycles
DAC 25°C IV 1 1 SYSCLK cycles
I/O Update Clock (Internal Mode) 25°C IV 2 2 SYSCLK cycles
I/O Update Clock (External Mode) 25°C IV 3 3 SYSCLK cycles

MASTER RESET DURATION 25°C IV 10 10 SYSCLK cycles
COMPARATOR INPUT CHARACTERISTICS

Input Capacitance 25°C V 3 3 pF
Input Resistance 25°C IV 500 500 kΩ
Input Current 25°C I ±1 ±5 ±1 ±5 μA
Hysteresis 25°C IV 10 20 10 20 mV p-p

COMPARATOR OUTPUT CHARACTERISTICS

Logic 1 Voltage, High-Z Load Full VI 3.1 3.1 V
Logic 0 Voltage, High-Z Load Full VI 0.16 0.16 V
Output Power, 50 Ω Load, 120 MHz Toggle Rate 25°C I 9 11 9 11 dBm
Propagation Delay 25°C IV 3 3 ns
Output Duty Cycle Error

7

25°C I −10 ±1 +10 −10 ±1 +10 %
Rise/Fall Times, 5 pF Load 25°C V 2 2 ns
Toggle Rate, High-Z Load 25°C IV 300 350 300 350 MHz
Toggle Rate, 50 Ω Load 25°C IV 375 400 375 400 MHz
Output Cycle-to-Cycle Jitter

COMPARATOR NARROW-BAND SFDR

8

9

IV 4.0 4.0 ps rms

10 MHz (±1 MHz) 25°C V 84 84 dBc
10 MHz (±250 MHz) 25°C V 84 84 dBc
10 MHz (±50 MHz) 25°C V 92 92 dBc
41 MHz (±1 MHz) 25°C V 76 76 dBc
41 MHz (±250 MHz) 25°C V 82 82 dBc
41 MHz (±50 MHz) 25°C V 89 89 dBc
119 MHz (±1 MHz) 25°C V 73 dBc
119 MHz (±250 MHz) 25°C V 73 dBc
119 MHz (±50 MHz) 25°C V 83 dBc

CLOCK GENERATOR OUTPUT JITTER

5 MHz A
40 MHz A
100 MHz A

25°C V 23 23 ps rms

OUT

25°C V 12 12 ps rms

OUT

25°C V 7 7 ps rms

OUT

9

Te st
Level

Min Typ Max Min Typ Max Unit

Rev. E | Page 6 of 52

AD9854

AD9854ASVZ AD9854ASTZ
Parameter Temp

PARALLEL I/O TIMING CHARACTERISTICS

t

(Address Setup Time to WR Signal Active)

ASU

t

(Address Hold Time to WR Signal Inactive)

ADHW

t

(Data Setup Time to WR Signal Inactive)

DSU

t

(Data Hold Time to WR Signal Inactive)

DHD

t

(WR Signal Minimum Low Time)

WRLOW

t

(WR Signal Minimum High Time)

WRHIGH

tWR (Minimum WR Time)
t

(Address to Data Valid Time) Full V 15 15 15 15 ns

ADV

t

(Address Hold Time to RD Signal Inactive)

ADHR

t

(RD Low to Output Valid)

RDLOV

t

(RD High to Data Three-State)

RDHOZ

Full IV 8.0 7.5 8.0 7.5 ns
Full IV 0 0 ns
Full IV 3.0 1.6 3.0 1.6 ns
Full IV 0 0 ns
Full IV 2.5 1.8 2.5 1.8 ns
Full IV 7 7 ns
Full IV 10.5 10.5 ns

Full IV 5 5 ns
Full IV 15 15 ns
Full IV 10 10 ns

SERIAL I/O TIMING CHARACTERISTICS

t

(CS Setup Time)

PRE

t

(Period of Serial Data Clock) Full IV 100 100 ns

SCLK

t

(Serial Data Setup Time) Full IV 30 30 ns

DSU

t

(Serial Data Clock Pulse Width High) Full IV 40 40 ns

SCLKPWH

t

(Serial Data Clock Pulse Width Low) Full IV 40 40 ns

SCLKPWL

t

(Serial Data Hold Time) Full IV 0 0 ns

DHLD

Full IV 30 30 ns

tDV (Data Valid Time) Full V 30 30 ns

CMOS LOGIC INPUTS

10

Logic 1 Voltage 25°C I 2.2 2.2 V
Logic 0 Voltage 25°C I 0.8 0.8 V
Logic 1 Current 25°C IV ±5 ±12 μA
Logic 0 Current 25°C IV ±5 ±12 μA
Input Capacitance 25°C V 3 3 pF

12, 15

13, 15

11, 15

11, 12 , 15

11, 13 , 15

14

25°C I 1050 1210 755 865 mA
25°C I 710 816 515 585 mA
25°C I 600 685 435 495 mA
25°C I 3.475 4.190 2.490 3.000 W
25°C I 2.345 2.825 1.700 2.025 W
25°C I 1.975 2.375 1.435 1.715 W

POWER SUPPLY

VS Current
VS Current
VS Current

11,

P

DISS

11,

P

DISS

14

P

DISS

P

Power-Down Mode 25°C I 1 50 1 50 mW

DISS

1

The reference clock inputs are configured to accept a 1 V p-p (typical) dc offset square or sine wave centered at one-half the applied VDD or a 3 V TTL-level pulse input.

2

An internal 400 mV p-p differential voltage swing equates to 200 mV p-p applied to both REFCLK input pins.

3

The I and Q gain imbalance is digitally adjustable to less than 0.01 dB.

4

Pipeline delays of each individual block are fixed; however, if the first eight MSBs of a tuning word are 0s, the delay appears longer. This is due to insufficient phase

accumulation per system clock period to produce enough LSB amplitude to the DAC.

5

If a feature such as the inverse sinc, which has 16 pipeline delays, can be bypassed, the total delay is reduced by that amount.

6

The I/O UD CLK transfers data from the I/O port buffers to the programming registers. This transfer is measured in system clocks.

7

Change in duty cycle from 1 MHz to 100 MHz with 1 V p-p sine wave input and 0.5 V threshold.

8

Represents the comparator’s inherent cycle-to-cycle jitter contribution. The input signal is a 1 V, 40 MHz square wave, and the measurement device is a Wavecrest DTS-2075.

9

Comparator input originates from the analog output section via the external 7-pole elliptic low-pass filter. Single-ended input, 0.5 V p-p. Comparator output

terminated in 50 Ω.

10

Avoid overdriving digital inputs. (Refer to the equivalent circuits in Figure 3.)

11

If all device functions are enabled, it is not recommended to simultaneously operate the device at the maximum ambient temperature of 85°C and at the maximum

internal clock frequency. This configuration may result in violating the maximum die junction temperature of 150°C. Refer to the Power Dissipation and Thermal
Considerations section for derating and thermal management information.

12

All functions engaged.

13

All functions except inverse sinc engaged.

14

All functions except inverse sinc and digital multipliers engaged.

15

In most cases, disabling the inverse sinc filter reduces power consumption by approximately 30%.

Te st
Level

Min Typ Max Min Typ Max Unit

Rev. E | Page 7 of 52

AD9854

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Maximum Junction Temperature 150°C
V

4 V

S

Digital Inputs −0.7 V to +V

S

Digital Output Current 5 mA
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering, 10 sec) 300°C
Maximum Clock Frequency (ASVZ) 300 MHz
Maximum Clock Frequency (ASTZ) 200 MHz

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

The heat sink of the AD9854ASVZ 80-lead TQFP package must
be soldered to the PCB.

Table 3.

Thermal Characteristic TQFP LQFP

θJA (0 m/sec airflow)
θ

(1.0 m/sec airflow)

JMA

θ

(2.5 m/sec airflow)

JMA

1, 2

Ψ

JT

6, 7

θ

2.0°C/W

JC

1

Per JEDEC JESD51-2 (heat sink soldered to PCB).

2

2S2P JEDEC test board.

3

Values of θJA are provided for package comparison and PCB design

considerations.

4

Per JEDEC JESD51-6 (heat sink soldered to PCB).

5

Airflow increases heat dissipation, effectively reducing θJA. Furthermore, the

more metal that is directly in contact with the package leads from metal
traces through holes, ground, and power planes, the more θJA is reduced.

6

Per MIL-Std 883, Method 1012.1.

7

Values of θJC are provided for package comparison and PCB design

considerations when an external heat sink is required.

1, 2, 3

16.2°C/W 38°C/W

2, 3, 4, 5

13.7°C/W

2, 3, 4, 5

12.8°C/W

0.3°C/W

To determine the junction temperature on the application PCB
use the following equation:

T

= T

+ (

Ψ

J

case

× PD)

JT

where:

is the junction temperature expressed in degrees Celsius.

T

J

is the case temperature expressed in degrees Celsius, as

T

case

measured by the user at the top center of the package.

Ψ

= 0.3°C/W.

JT

PD is the power dissipation (PD); see the

Thermal Considerations

section for the method to calculate PD.

Power Dissipation and

EXPLANATION OF TEST LEVELS

Table 3.

Test Level Description

I 100% production tested.
III Sample tested only.
IV

Parameter is guaranteed by design and

characterization testing.
V Parameter is a typical value only.
VI

Devices are 100% production tested at 25°C and

guaranteed by design and characterization testing

for industrial operating temperature range.

ESD CAUTION

Rev. E | Page 8 of 52

AD9854

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AGND

AGND

AVD D

DIFF CLK ENABLENCAGND

PLL FILTER

60

AVD D

59

AGND

58

NC

57

NC

56

DAC R

SET

55

DACBP

54

AVD D

53

AGND

52

IOUT2

51

IOUT2

50

AVD D

49

IOUT1

48

IOUT1

47

AGND

46

AGND

45

AGND

44

AVD D

43

VINN

42

VINP

41

AGND

AVD D

AVD D

AGND

AGND

D7

D6

D5

D4

D3

D2

D1

D0

DVDD

DVDD

DGND

DGND

NC

A5

A4

A3

A2/IO RESET

A1/SDO

A0/SDIO

I/O UD CLK

DVDD

DVDD

DGND

DGND

DGND

DGND

DVDD

DVDD

DGND

DGND

DGND

AD9854

TOP VIEW

(Not to Scale)

DGND

80 79 78 77 76 71 70 69 6875 74 73 72

1

PIN 1

2

INDICATOR

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21 22 23 24 25 26 27 28 29 30 31 32 33

DVDD

DVDD

DVDD

RD/CS

WR/SCLK

MASTER RESET

OSK

S/P SELECT

REFCLK

REFCLK

34 35 36 37 38 39 40

AVD D

AVD D

AGND

AGND

NC

64 63 62 6167 66 65

VOUT

NC = NO CONNECT

FSK/BPSK/HO LD

00636-002

Figure 2. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 to 8 D7 to D0 8-Bit Bidirectional Parallel Programming Data Inputs. Used only in parallel programming mode.
9, 10, 23, 24, 25,

73, 74, 79, 80
11, 12, 26, 27, 28,

DVDD

Connections for the Digital Circuitry Supply Voltage. Nominally 3.3 V more positive than AGND
and DGND.

DGND Connections for the Digital Circuitry Ground Return. Same potential as AGND.

72, 75 to 78
13, 35, 57, 58, 63 NC No Internal Connection.
14 to 16 A5 to A3

Parallel Address Inputs for Program Registers (Part of 6-Bit Parallel Address Inputs for Program
Register, A5:A0). Used only in parallel programming mode.

17 A2/IO RESET

Parallel Address Input for Program Registers (Part of 6-Bit Parallel Address Inputs for Program
Register, A5:A0)/IO Reset. A2 is used only in parallel programming mode. IO RESET is used when
the serial programming mode is selected, allowing an IO RESET of the serial communication bus
that is unresponsive due to improper programming protocol. Resetting the serial bus in this
manner does not affect previous programming, nor does it invoke the default programming
values listed in

18 A1/SDO

Parallel Address Input for Program Registers (Part of 6-Bit Parallel Address Inputs for Program

Table 8. Active high.

Register, A5:A0)/Unidirectional Serial Data Output. A1 is used only in parallel programming
mode. SDO is used in 3-wire serial communication mode when the serial programming mode is
selected.

19 A0/SDIO

Parallel Address Input for Program Registers (Part of 6-Bit Parallel Address Inputs for Program
Register, A5:A0)/Bidirectional Serial Data I/O. A0 is used only in parallel programming mode. SDIO
is used in 2-wire serial communication mode.

Rev. E | Page 9 of 52

AD9854

Pin No. Mnemonic Description

20 I/O UD CLK

21

22

WR/SCLK Write Parallel Data to I/O Port Buffers. Shared function with SCLK. Serial clock signal associated

RD/CS Read Parallel Data from Programming Registers. Shared function with CS. Chip-select signal

29 FSK/BPSK/HOLD

30 OSK

31, 32, 37, 38, 44,

AVDD

50, 54, 60, 65
33, 34, 39, 40, 41,

AGND Connections for Analog Circuitry Ground Return. Same potential as DGND.
45, 46, 47, 53, 59,
62, 66, 67

36 VOUT

42 VINP Voltage Input Positive. The noninverting input of the internal high speed comparator.
43 VINN Voltage Input Negative. The inverting input of the internal high speed comparator.
48 IOUT1 Unipolar Current Output of I, or the Cosine DAC. (Refer to Figure 3.)
49

51

IOUT1

IOUT2
52 IOUT2

55 DACBP

56 DAC R

SET

61 PLL FILTER

64 DIFF CLK ENABLE

68

REFCLK Complementary (180° Out of Phase) Differential Clock Signal. User should tie this pin high or low

69 REFCLK

70 S/P SELECT Selects serial programming mode (logic low) or parallel programming mode (logic high).
71 MASTER RESET

Bidirectional I/O Update Clock. Direction is selected in control register. If this pin is selected as an
input, a rising edge transfers the contents of the I/O port buffers to the programming registers. If I/O
UD CLK is selected as an output (default), an output pulse (low to high) with a duration of eight
system clock cycles indicates that an internal frequency update has occurred.

with the serial programming bus. Data is registered on the rising edge. This pin is shared with

WR

when the parallel mode is selected. The mode is dependent on Pin 70 (S/P SELECT).

associated with the serial programming bus. Active low. This pin is shared with

RD when the

parallel mode is selected.
Multifunction pin according to the mode of operation selected in the programming control

register. In FSK mode, logic low selects F1 and logic high selects F2. In BPSK mode, logic low
selects Phase 1 and logic high selects Phase 2. In chirp mode, logic high engages the hold
function, causing the frequency accumulator to halt at its current location. To resume or
commence chirp mode, logic low is asserted.

Output Shaped Keying. Must first be selected in the programming control register to function. A
logic high causes the I and Q DAC outputs to ramp up from zero-scale to full-scale amplitude at a
preprogrammed rate. Logic low causes the full-scale output to ramp down to zero scale at the
preprogrammed rate.

Connections for the Analog Circuitry Supply Voltage. Nominally 3.3 V more positive than AGND
and DGND.

Noninverted Output of the Internal High Speed Comparator. Designed to drive 10 dBm to 50 Ω
load as well as standard CMOS logic levels.

Complementary Unipolar Current Output of I, or the Cosine DAC.
Complementary Unipolar Current Output of Q, or the Sine DAC.
Unipolar Current Output of Q, or the Sine DAC. This DAC can be programmed to accept external

12-bit data in lieu of internal sine data, allowing the AD9854 to emulate the AD9852 control DAC
function.

Common Bypass Capacitor Connection for Both I and Q DACs. A 0.01 μF chip capacitor from this
pin to AVDD improves harmonic distortion and SFDR slightly. No connect is permissible, but
results in a slight degradation in SFDR.

Common Connection for Both I and Q DACs. Used to set the full-scale output current. R
Normal R

range is from 8 kΩ (5 mA) to 2 kΩ (20 mA).

SET

= 39.9/I

SET

OUT

.

Connection for the External Zero-Compensation Network of the REFCLK Multiplier’s PLL Loop
Filter. The zero-compensation network consists of a 1.3 kΩ resistor in series with a 0.01 μF
capacitor. The other side of the network should be connected to AVDD as close as possible to
Pin 60. For optimum phase noise performance, the REFCLK multiplier can be bypassed by setting
the bypass PLL bit in Control Register 1E hex.

Differential REFCLK Enable. A high level of this pin enables the differential clock inputs, REFCLK
and

REFCLK (Pin 69 and Pin 68, respectively).

when single-ended clock mode is selected. Same signal levels as REFCLK.
Single-Ended Reference Clock Input (CMOS Logic Levels Required) or One of Two Differential

Clock Signals. In differential reference clock mode, both inputs can be CMOS logic levels or have
greater than 400 mV p-p square or sine waves centered about 1.6 V dc.

Initializes the serial/parallel programming bus to prepare for user programming; sets
programming registers to a do-nothing state defined by the default values listed in

Table 8.

Active on logic high. Asserting this pin is essential for proper operation upon power-up.

Rev. E | Page 10 of 52

AD9854

AVDD

I

OUTIOUTB

MUST TERMI NATE OUTPUT S
FOR CURRENT FLOW. DO
NOT EXCEED THE OUTPUT
VOLT AGE COMPLIANCE RAT ING.

A. DAC OUTPUTS B. COMPARATOR OUT PUT C. COMPARATO R INPUT D. DIGITAL INPUT S

AVDD

VINP/

COMPARATOR
OUT

VINN

Figure 3. Equivalent Input and Output Circuits

AVDD

DVDD

DIGITAL

IN

AVOID OVERDRIVING
DIGITAL INPUTS. FORWARD
BIASING ESD DIODES MAY
COUPLE DI GITAL NOISE
ONTO POWER PINS.

00636-003

Rev. E | Page 11 of 52

AD9854

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 4 to Figure 9 indicate the wideband harmonic distortion performance of the AD9854 from 19.1 MHz to 119.1 MHz fundamental
output, reference clock = 30 MHz, REFCLK multiplier = 10×. Each graph is plotted from 0 MHz to 150 MHz (Nyquist).

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

START 0Hz

15MHz/ STOP 150MHz

Figure 7. Wideband SFDR, 79.1 MHz

00636-007

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

START 0Hz

15MHz/ STOP 150MHz

Figure 4. Wideband SFDR, 19.1 MHz

0636-004

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

START 0Hz

START 0Hz

15MHz/ STOP 150MHz

Figure 5. Wideband SFDR, 39.1 MHz

15MHz/ STOP 150MHz

Figure 6. Wideband SFDR, 59.1 MHz

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

00636-005

START 0Hz

15MHz/ STOP 150MHz

00636-008

Figure 8. Wideband SFDR, 99.1 MHz

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

00636-006

START 0Hz

15MHz/ STOP 150MHz

00636-009

Figure 9. Wideband SFDR, 119.1 MHz

Rev. E | Page 12 of 52

AD9854

Figure 10 to Figure 15 show the trade-off in elevated noise floor, increased phase noise (PN), and discrete spurious energy when the internal
REFCLK multiplier circuit is engaged. Plots with wide (1 MHz) and narrow (50 kHz) spans are shown. Compare the noise floor of
Figure 11 and Figure 12 with that of Figure 14 and Figure 15. The improvement seen in Figure 11 and Figure 12 is a direct result of
sampling the fundamental at a higher rate. Sampling at a higher rate spreads the quantization noise of the DAC over a wider bandwidth,
which effectively lowers the noise floor.

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

CENTER 39.1MHz

100kHz/ SPAN 1MHz

Figure 10. Narrow-Band SFDR, 39.1 MHz, 1 MHz BW,

300 MHz REFCLK with REFCLK Multiplier Bypassed

0636-010

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

CENTER 39.1MHz

100kHz/ SPAN 1MHz

Figure 13. Narrow-Band SFDR, 39.1 MHz, 1 MHz BW,

30 MHz REFCLK with REFCLK Multiplier = 10×

00636-012

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

CENTER 39.1M Hz

5kHz/ SPAN 50kHz

Figure 11. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,

300 MHz REFCLK with REFCLK Multiplier Bypassed

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

CENTER 39.1M Hz

5kHz/ SPAN 50kHz

Figure 12. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,

100 MHz REFCLK with REFCLK Multiplier Bypassed

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

00636-011

CENTER 39.1MHz

5kHz/ SPAN 50kHz

00636-013

Figure 14. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,

30 MHz REFCLK with REFCLK Multiplier = 10×

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

00636-014

CENTER 39. 1MHz

5kHz/ SPAN 50kHz

00636-015

Figure 15. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,

10 MHz REFCLK with REFCLK Multiplier = 10×

Rev. E | Page 13 of 52

AD9854

–

–

Figure 16 and Figure 17 show the narrow-band performance of the AD9854 when operating with a 200 MHz reference clock with the
REFCLK multiplier bypassed vs. a 20 MHz reference clock and the REFCLK multiplier enabled at 10×.

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

CENTER 39.1MHz

5kHz/ SPAN 50kHz

Figure 16. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,

200 MHz REFCLK with REFCLK Multiplier Bypassed

00636-016

90

–100

–110

–120

–130

–140

PHASE NOISE (dBc/Hz)

–150

A

=5MHz

OUT

–160

10 1M100 100k10k1k

30 MHz REFCLK with REFCLK Multiplier = 10×

A

=80MHz

OUT

FREQUENCY (Hz)

Figure 19. Residual Phase Noise,

00636-019

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

CENTER 39. 1MHz

5kHz/ SPAN 50kHz

Figure 17. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,

20 MHz REFCLK with REFCLK Multiplier = 10×

100

–110

–120

A

= 80MHz

OUT

PHASE NOISE (dBc/Hz)

–130

–140

–150

–160

A

=5MHz

OUT

55

54

53

52

51

SFDR (dBc)

50

49

48

00636-017

0 5 10 15 20 25

Figure 20. SFDR vs. DAC Current, 59.1 A

DAC CURRENT (mA)

OUT

,

00636-020

300 MHz REFCLK with REFCLK Multiplier Bypassed

620

615

610

605

600

SUPPLY CURRENT (mA)

595

–170

10 1M100 100k10k1k

FREQUENCY (Hz)

Figure 18. Residual Phase Noise,

300 MHz REFCLK with REFCLK Multiplier Bypassed

00636-018

590

0

20 40 60 80 100 120 140

FREQUENCY (MHz)

Figu re 21. Supply Current vs . Output Frequency (Variation Is Minimal,

Expressed as a Percentage, and Heavily Dependent on Tuning Word)

00636-021

Rev. E | Page 14 of 52

AD9854

1200

MINIMUM COMPARATOR
INPUT DRI VE
V

=0.5V

CM

1000

RISE TIM E

1.04ns

JITTER

[10.6ps RMS]

–33ps 0ps +33ps

500ps/DIV 232mV/DIV 50

Ω INPUT

Figure 22. Typical Comparator Output Jitter, 40 MHz A

300 MHz RFCLK with REFCLK Multiplier Bypassed

REF1 RISE

1.174ns

C1 FALL

1.286ns

OUT

800

600

400

AMPLITUDE (mV p -p)

200

0636-022

,

0

0

100 200 300 400 500

FREQUENCY (MHz)

Figure 24. Comparator Toggle Voltage Requirement

00636-024

CH1 500mV Ω M 500ps CH1 980mV

Figure 23. Comparator Rise/Fall Times

00636-023

Rev. E | Page 15 of 52

AD9854

TYPICAL APPLICATIONS

DIGITAL

I BASEBAND

Q BASEBAND

RF OUTPUT

AGC

00636-025

00636-026

Rx BASEBAND
DIGITAL DATA
OUT

00636-027

LPF

COS

RF/IF

INPUT

REFCLK

AD9854

LPF

LPF

SIN

CHANNEL
SELECT
FILTERS

LPF

Figure 25. Quadrature Downconversion

I BASEBAND

COS

LPF

LPF

SIN

Q BASEBAND

REFCLK

AD9854

Figure 26. Direct Conversion Quadrature Upconverter

8

8

ADC ENCODE

48

CHIP/SYMBOL/PN

RATE DATA

DEMODULATOR

Rx

RF IN

VCA

I/Q MIXER

AND

LOW-PASS

FILTER

ADC CLOCK FREQUENCY

LOCKED TO Tx CHIP/

SYMBOL/PN RATE

I

DUAL

8-/10-BIT

Q

ADC

AD9854

CLOCK

REFERENCE

CLOCK

GENERATOR

Figure 27. Chip Rate Generator in Spread Spectrum Application

BAND-PASS

FILTER

I

AD9854

C–FO

OUT

50Ω

F

C+FO

IMAGE

F

CLK

AD9854

SPECTRUM

FUNDAMENTAL

F

IMAGE

Figure 28. Using an Aliased Image to Generate a High Frequency

Rev. E | Page 16 of 52

AMPLIFIER

50

Ω

FINAL OUTPUT

SPECTRUM

FC+F
IMAGE

O

BAND-PASS
FILTER

00636-028