Analog Devices AD9852 c Datasheet

CMOS 300 MSPS

L

FEATURES

300 MHz internal clock rate FSK, BPSK, PSK, CHIRP, AM operation Dual integrated 12-bit D/A converters Ultrahigh speed comparator, 3 ps rms jitter Excellent dynamic performance:

80 dB SFDR @ 100 MHz (±1 MHz) A 4× to 20× programmable reference clock multiplier Dual 48-bit programmable frequency registers Dual 14-bit programmable phase offset registers 12-bit programmable amplitude modulation and shaped

on/off keying function Single pin FSK and BPSK data interface PSK capability via I/O interface Linear or nonlinear FM chirp functions with single pin

frequency hold function Frequency-ramped FSK

REFERENCE

CLOCK IN

DIFF/SINGLE

SELECT

FSK/BPSK/HOLD

DATA IN

BIDIRECTIONAL

INTERNAL/EXTERNA

I/O UPDATE CLOCK

REF CLK

BUFFER

SYSTEM

CLOCK

DEMUX

2

MODE SELECT

SYSTEM

CLOCK

3

FREQUENCY

48 48 48 14

DELTA

FREQUENCY

WORD

CK D

INT

EXT

4× – 20×

REF CLK

MULTIPLIER

MUX

DELTA

RATE TIMER

SYSTEM

CLOCK

Q

OUT

FUNCTIONAL BLOCK DIAGRAM

SYSTEM CLOCK

ACC 1

FREQUENCY

ACCUMULATOR

MUX

FREQUENCY

TUNING WORD 1

INTERNAL

PROGRAMMABLE

UPDATE CLOCK

FREQUENCY

÷2

4848

48

MUX MUX

TUNING WORD 2

PROGRAMMING REGISTERS

SYSTEM CLOCK

<25 ps rms total jitter in clock generator mode Automatic bidirectional frequency sweeping SIN(x)/x correction Simplified control interface

3.3 V single supply Multiple power-down functions Single-ended or differential input reference clock Small 80-lead LQFP packaging

APPLICATIONS

Agile LO frequency synthesis Programmable clock generator FM chirp source for radar and scanning systems Test and measurement equipment Commercial and amateur RF exciter

DDS CORE

17

ACC 2

PHASE

ACCUMULATOR

FIRST 14-BIT

PHASE/OFFSET

WORD

READ WRITE SERIAL/

Figure 1.

14

AD9852

PHASE-TO-

Complete DDS

AD9852

10 MHz serial, 2-wire or 3-wire SPI® compatible, or 100 MHz parallel 8-bit programming

DIGITAL MULTIPLIERS

INV.

12

SINC

I

FILTER

AMPLITUDE

CONVERTER

Q

SYSTEM

CLOCK

14

SECOND 14-BIT PHASE/OFFSET

WORD

PARALLEL

SELECT

MUX

PROGRAMMABLE

AMPLITUDE AND

RATE CONTROL

12

AM

MODULATION

BUS

I/O PORT BUFFERS

6-BIT ADDRESS

OR SERIAL

PROGRAMMING

LINES

MUX

SYSTEM

CLOCK

12-BIT DC CONTROL

PARALLEL

12

8-BIT

LOAD

12-BIT

COSINE

DAC

12-BIT

CONTROL

DAC

COMPARATOR

MASTER

RESET

DAC R

CLOCK OUT

OSK

GND

+V

ANALOG OUT

SET

ANALOG OUT

ANALOG IN

S

00634-C-001

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

www.analog.com

AD9852

TABLE OF CONTENTS

General Description......................................................................... 3

Parallel I/O Operation ............................................................... 27

Overview........................................................................................ 3

Specifications..................................................................................... 4

Absolute Maximum Ratings............................................................ 7

Explanation of Test Levels........................................................... 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ........................................... 10

Typical Applications ....................................................................... 14

Modes of Operation ....................................................................... 16

Using the AD9852........................................................................... 24

Internal and External Update Clock ........................................ 24

Output Shaped On/Off Keying (OSK) .................................... 24

Cosine DAC................................................................................. 25

Control DAC............................................................................... 25

Inverse SINC Function .............................................................. 26

REFCLK Multiplier.................................................................... 26

Serial Port I/O Operation.......................................................... 27

General Operation of the Serial Interface................................... 30

Instruction Byte .......................................................................... 30

Serial Interface Port Pin Descriptions..................................... 31

MSB/LSB Transfers .................................................................... 31

Control Register Descriptions.................................................. 32

Power Dissipation and Thermal Considerations....................... 34

Thermal Impedance................................................................... 34

Junction Temperature Considerations .................................... 34

Evaluation of Operating Conditions............................................ 36

Thermally Enhanced Package Mounting Guidelines............ 36

Evaluation Board ............................................................................ 38

Evaluation Board Instructions.................................................. 38

General Operating Instructions ............................................... 38

Using the Provided Software .................................................... 41

Programming the AD9852 ............................................................ 27

Master RESET ............................................................................. 27

REVISION HISTORY

4/04—Data Sheet Changed from Rev. B to Rev. C

Updated Format........................................................... Universal

Changes to Figure 1....................................................................1

Changes to General Description ..............................................3

Changes to Table 1......................................................................4

Changes to Footnote 2 ...............................................................6

Changes to Figure 2....................................................................8

Changes to Table 5....................................................................17

Changes to Equation in Ramped FSK (Mode 010)..............19

Changes to Evaluation Board Instructions ...........................39

Changes to General Operating Instructions Section...........39

Changes to Using the Provided Software Section ................42

Changes to Figure 65................................................................43

Changes to Figure 66................................................................44

Changes to Figure 72 and Figure 73.......................................48

Changes to Ordering Guide....................................................48

Outline Dimensions....................................................................... 48

Ordering Guide .......................................................................... 48

3/02—Changed from Rev. A to Rev. B:

Changes to General Description ..............................................1

Changes to Functional Block Diagram....................................1

Changes to Specifications.......................................................... 3

Changes to Absolute Maximum Ratings.................................5

Changes to Pin Function Descriptions....................................6

Changes to Figure 3....................................................................8

Deleted Two TPCs....................................................................11

Changes to Figure 18 and Figure 19.......................................11

Changes to BPDK Mode Section............................................21

Changes to Differential Refclk Enable Section..................... 24

Changes to Master Reset Section ...........................................24

Changes to Parallel I/O Operation Section...........................24

Changes to General Operation of the Serial

Interface Section .......................................................................27

Changes to Figure 50................................................................27

Changes to Figure 65................................................................36

Rev. C | Page 2 of 48

AD9852

GENERAL DESCRIPTION

The AD9852 digital synthesizer is a highly integrated device that uses advanced DDS technology, coupled with an internal high speed, high performance D/A converter to form a digitally programmable agile synthesizer function. When referenced to an accurate clock source, the AD9852 generates a highly stable, frequency-phase-amplitude-programmable cosine output that can be used as an agile LO in communications, radar, and many other applications. The AD9852’s innovative high speed DDS core provides 48-bit frequency resolution (1 MHz tuning resolution with 300 MHz SYSCLK). Maintaining 17 bits assures excellent SFDR.

The AD9852’s circuit architecture allows the generation of output signals at frequencies up to 150 MHz, which can be digitally tuned at a rate of up to 100 million new frequencies per second. The (externally filtered) cosine wave output can be converted to a square wave by the internal comparator for agile clock generator applications. The device provides two 14-bit phase registers and a single pin for BPSK operation. For high order PSK operation, the I/O interface may be used for phase changes. The 12-bit cosine DAC, coupled with the innovative DDS architecture, provides excellent wideband and narrowband output SFDR. When configured with the comparator, the 12-bit control DAC facilitates static duty cycle control in the high speed clock generator applications. The 12-bit digital multiplier permits programmable amplitude modulation, shaped on/off keying, and precise amplitude control of the cosine DAC output. Chirp functionality is also included for wide bandwidth frequency sweeping applications. The AD9852’s programmable 4 × to 20 × REFCLK multiplier circuit generates the 300 MHz system clock internally from a lower frequency external reference clock. This saves the user the

expense and difficulty of implementing a 300 MHz system clock source. Direct 300 MHz clocking is also accommodated with either single-ended or differential inputs. Single pin conventional FSK and the enhanced spectral qualities of “ramped” FSK are supported. The AD9852 uses advanced

0.35 micron CMOS technology to provide this high level of functionality on a single 3.3 V supply.

The AD9852 is available in a space-saving 80-lead LQFP surface-mount package and a thermally enhanced 80-lead LQFP package. The AD9852 is pin-for-pin compatible with the AD9854 single-tone synthesizer. It is specified to operate over the extended industrial temperature range of –40°C to +85°C.

OVERVIEW

The AD9852 digital synthesizer is a highly flexible device that addresses a wide range of applications. The device consists of an NCO with 48-bit phase accumulator, a programmable reference clock multiplier, an inverse sinc filter, a digital multiplier, two 12-bit/300 MHz DACs, a high speed analog comparator, and interface logic. This highly integrated device can be configured to serve as a synthesized LO agile clock generator and FSK/BPSK modulator. The theory of operation of the functional blocks of the device, and a technical description of the signal flow through a DDS device is provided by Analog Devices in “A Technical Tutorial on Digital Signal Synthesis.” This tutorial is available in the DDS Technical Library of the Analog Devices website at www.analog.com/dds. The tutorial also provides basic applications information for a variety of digital synthesis implementations.

Rev. C | Page 3 of 48

AD9852

SPECIFICATIONS

VS = 3.3 V ± 5%, R

external reference clock frequency = 20 MHz with REFCLK multiplier enabled at 10× for AD9852AST, unless otherwise noted.

Table 1.

Parameter

REF CLOCK INPUT CHARACTERISTICS1

Internal System Clock Frequency Range

REFCLK Multiplier Enabled Full VI 20 300 20 200 MHz REFCLK Multiplier Disabled Full VI DC 300 DC 200 MHz

External REF Clock Frequency Range

REFCLK Multiplier Enabled Full VI 5 75 5 50 MHz

REFCLK Multiplier Disabled Full VI DC 300 DC 200 MHz Duty Cycle 25°C IV 45 50 55 45 50 55 % Input Capacitance 25°C IV 3 3 pF Input Impedance 25°C IV 100 100 kΩ Differential-Mode Common-Mode Voltage Range

Minimum Signal Amplitude2 25°C IV 400 400 mV p-p

Common-Mode Range 25°C IV 1.6 1.75 1.9 1.6 1.75 1.9 V VIH (Single-Ended Mode) 25°C IV 2.3 2.3 V VIL (Single-Ended Mode) 25°C IV 1 1 V

DAC STATIC OUTPUT CHARACTERISTICS

Output Update Speed Full I 300 200 MSPS Resolution 25°C IV 12 12 Bits Cosine and Control DAC Full-Scale Output Current 25°C IV 5 10 20 5 10 20 mA Gain Error 25°C I Output Offset 25°C I 2 2 µA Differential Nonlinearity 25°C I 0.3 1.25 0.3 1.25 LSB Integral Nonlinearity 25°C I 0.6 1.66 0.6 1.66 LSB Output Impedance 25°C IV 100 100 kΩ Voltage Compliance Range 25°C I

DAC DYNAMIC OUTPUT CHARACTERISTICS

DAC Wideband SFDR

1 MHz to 20 MHz A

20 MHz to 40 MHz A

40 MHz to 60 MHz A

60 MHz to 80 MHz A

80 MHz to 100 MHz A

100 MHz to 120 MHz A DAC Narrow-Band SFDR

10 MHz A

41 MHz A

119 MHz A

OUT

= 3.9 kΩ; external reference clock frequency = 30 MHz with REFCLK multiplier enabled at 10× for AD9852ASQ;

SET

Temp

25°C V 58 58 dBc

OUT

25°C V 56 56 dBc

OUT

25°C V 52 52 dBc

OUT

25°C V 48 48 dBc

OUT

25°C V 48 dBc

OUT

25°C V 48 48 dBc

Test Level

AD9852ASQ

Min Typ Max

+2.25

−6

+1.0

−0.5

AD9852AST

Min Typ Max Unit

+2.25 % FS

−6

+1.0 V

−0.5

(± 1 MHz) 25°C V 83 83 dBc (± 250 kHz) 25°C V 83 83 dBc (± 50 kHz) 25°C V 91 91 dBc (± 1 MHz) 25°C V 82 82 dBc (± 250 kHz) 25°C V 84 84 dBc (± 50 kHz) 25°C V 89 89 dBc

(± 1 MHz) 25°C V 71 dBc (± 250 kHz) 25°C V 77 dBc (± 50 kHz) 25°C V 83 dBc

Rev. C | Page 4 of 48

AD9852

Parameter

Residual Phase Noise (A

= 5 MHz, Ext. CLK = 30 MHz, REFCLK

OUT

Multiplier Engaged at 10×)

1 kHz Offset 25°C V 140 140 dBc/Hz 10 kHz Offset 25°C V 138 138 dBc/Hz 100 kHz Offset 25°C V 142 142 dBc/Hz

(A

= 5 MHz, Ext. CLK = 300 MHz, REFCLK

OUT

Multiplier Bypassed)

1 kHz Offset 25°C V 142 142 dBc/Hz 0 kHz Offset 25°C V 148 148 dBc/Hz 100 kHz Offset 25°C V 152 152 dBc/Hz

PIPELINE DELAYS3, 4, 5

DDS Core (Phase Accumulator and Phase-toAmp Converter)

Frequency Accumulator 25°C IV 26 26

Inverse Sinc Filter 25°C IV 16 16

Digital Multiplier 25°C IV 9 9

DAC 25°C IV 1 1

I/O Update Clock (INT Mode) 25°C IV 2 2

I/O Update Clock (EXT Mode) 25°C IV 3 3

MASTER RESET DURATION 25°C IV 10 10

COMPARATOR INPUT CHARACTERISTICS

Input Capacitance 25°C V 3 3 pF Input Resistance 25°C IV 500 500 kΩ Input Current 25°C I ± 1 ± 5 ± 1 ± 5 µA Hysteresis 25°C IV 10 20 10 20 mV p-p

COMPARATOR OUTPUT CHARACTERISTICS

Logic 1 Voltage, High Z Load Full VI 3.1 3.1 V Logic 0 Voltage, High Z Load Full VI 0.16 0.16 V Output Power, 50 Ω Load, 120 MHz Toggle Rate 25°C I 9 11 9 11 dBm Propagation Delay 25°C IV 3 3 ns Output Duty Cycle Error6 25°C I Rise/Fall Time, 5 pF Load 25°C V 2 2 ns Toggle Rate, High Z Load 25°C IV 300 350 300 350 MHz Toggle Rate, 50 Ω Load 25°C IV 375 400 375 400 MHz Output Cycle-to-Cycle Jitter7 25°C IV 4.0 4.0 ps rms

COMPARATOR NARROWBAND SFDR

8

10 MHz (± 1 MHz) 25°C V 84 84 dBc 10 MHz (± 250 MHz) 25°C V 84 84 dBc 10 MHz (± 50 kHz) 25°C V 92 92 dBc 41 MHz (± 1 MHz) 25°C V 76 76 dBc 41 MHz (± 250 kHz) 25°C V 82 82 dBc 41 MHz (± 50 kHz) 25°C V 89 89 dBc 119 MHz (± 1 MHz) 25°C V 73 dBc 119 MHz (± 250 kHz) 25°C V 73 dBc 119 MHz (± 50 kHz) 25°C V 83 dBc

Temp

Test Level

AD9852ASQ

Min Typ Max

AD9852AST

Min Typ Max Unit

25°C IV 33 33

SysClk cycles

−10

± 1 +10

± 1 +10 %

−10

Rev. C | Page 5 of 48

AD9852

Parameter

Temp

Test Level

AD9852ASQ

Min Typ Max

AD9852AST

Min Typ Max

CLOCK GENERATOR OUTPUT JITTER8

5 MHz A 40 MHz A 100 MHz A

25°C V 23 23 ps rms

OUT

25°C V 12 12 ps rms

OUT

25°C V 7 7 ps rms

OUT

PARALLEL I/O TIMING CHARACTERISTICS

T

(Address Setup Time to WR Signal Active)

ASU

T

(Address Hold Time to WR Signal Inactive)

ADHW

T

(Data Setup Time to WR Signal Inactive)

DSU

T

(Data Hold Time to WR Signal Inactive)

DHD

T

(WR Signal Minimum Low Time)

WRLOW

T

(WR Signal Minimum High Time)

WRHIGH

Full IV 8.0 7.5 8.0 7.5 ns Full IV 0 0 ns Full IV 3.0 1.6 3.0 1.6 ns Full IV 0 0 ns Full IV 2.5 1.8 2.5 1.8 ns

Full IV 7 7 ns TWR (Minimum WRITE Time) Full IV 10.5 10.5 ns T

(Address to Data Valid Time) Full V 15 15 15 15 ns

ADV

T

(Address Hold Time to RD Signal Inactive)

ADHR

T

(RD Low-to-Output Valid)

RDLOV

T

(RD High-to-Data Three-State)

RDHOZ

Full IV 5 5 ns

Full IV 15 15 ns

Full IV 10 10 ns

SERIAL I/O TIMING CHARACTERISTICS

T

(CS Setup Time)

PRE

T

(Period of Serial Data Clock) Full IV 100 100 ns

SCLK

T

(Serial Data Setup Time) Full IV 30 30 ns

DSU

T

(Serial Data Clock Pulse Width High) Full IV 40 40 Ns

SCLKPWH

T

(Serial Data Clock Pulse Width Low) Full IV 40 40 Ns

SCLKPWL

T

(Serial Data Hold Time) Full IV 0 0 Ns

DHLD

Full IV 30 30 ns

TDV (Data Valid Time) Full V 30 30 ns

CMOS LOGIC INPUTS 9

Logic 1 Voltage 25°C I 2.2 2.2 V Logic 0 Voltage 25°C I 0.8 0.8 V Logic ” Current 25°C IV ± 5 ± 12 µA Logic 0 Current 25°C IV ± 5 ± 12 µA Input Capacitance 25°C V 3 3 pF

POWER SUPPLY

10

+VS Current11 25°C I 815 922 585 660 mA +VS Current12 25°C I 640 725 465 520 mA +VS Current13 25°C I 585 660 425 475 mA P

11 25°C I 2.70 3.20 1.93 2.39 W

DISS

P

12 25°C I 2.12 2.52 1.53 1.81 W

DISS

P

13 25°C I 1.93 2.29 1.40 1.65 W

DISS

P

Power-Down Mode 25°C I 1 50 1 50 mW

DISS

1

The reference clock inputs are configured to accept a 1 V p-p (typical) dc offset square or sine waves centered at one-half the applied VDD or a 3 V TTL-level pulse input.

2

An internal 400 mV p-p differential voltage swing equates to 200 mV p-p applied to both REFCLK input pins.

3

Pipeline delays of each individual block are fixed; however, if the eight top MSBs of a tuning word are all zeros, the delay appears appear longer. This is due to

insufficient phase accumulation per a system clock period to produce enough LSB amplitude to the D/A converter.

4

If a feature such as inverse sinc, which has 16 pipeline delays, can be bypassed, the total delay is reduced by that amount.

5

The I/O Update CLK transfers data from the I/O port buffers to the programming registers. This transfer takes system clocks to perform.

6

Change in duty cycle from 1 MHz to 100 MHz with 1 V p-p sine wave input and 0.5 V threshold.

7

Represents comparator’s inherent cycle-to-cycle jitter contribution. Input signal is a 1 V, 40 MHz square wave. Measurement device Wavecrest DTS – 2075.

8

Comparator input originates from analog output section via external 7-pole elliptic LPF. Single-ended input, 0.5 V p-p. Comparator output terminated in 50 Ω.

9

Avoid overdriving digital inputs. (Refer to equivalent circuits in .) Figure 3

10

Simultaneous operation at the maximum ambient temperature of 85°C and the maximum internal clock frequency of 200 MHz for the 80-lead LQFP, or 300 MHz for the thermally enhanced 80-lead LQFP may cause the maximum die junction temperature of 150°C to be exceeded. Refer to the Power Dissipation and Thermal Considerations section for derating and thermal management information.

11

All functions engaged.

12

All functions except inverse sinc engaged.

13

All functions except inverse sinc and digital multipliers engaged.

Unit

Rev. C | Page 6 of 48

AD9852

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Maximum Junction Temperature 150°C V

S

Digital Inputs Digital Output Current 5 mA Storage Temperature Operating Temperature Lead Temperature (Soldering, 10 s) 300°C Maximum Clock Frequency (ASQ) 300 MHz Maximum Clock Frequency (AST) 200 MHz θJA (ASQ) 16°C/W θJC (ASQ) 2°C/W θJA (AST) 38°C/W

4 V

−0.7 V to +V

−65°C to +150°C

−40°C to +85°C

S

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition s above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

EXPLANATION OF TEST LEVELS

Tes t Le v el

1. 100% production tested.

2. Sample tested only.

3. Parameter is guaranteed by design and characterization

testing.

4. Parameter is a typical value only.

5. Devices are 100% production tested at 25°C and

guaranteed by design and characterization testing for industrial operating temperature range.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. C | Page 7 of 48

AD9852

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AGND

S/P SELECT

REFCLK

REFCLKB

34 35 36 37 38 39 40

AVDD

AGND

DVDD

DVDD DGND DGND

NC

A2/IO RESET

A1/SDO

A0/SDIO

I/O UD CLK

DVDD

DGND

DVDD

DGND

80 79 78 77 76 71 70 69 6875 74 73 72

1

D7 D6 D5 D4 D3 D2 D1 D0

A5 A4 A3

PIN 1

2

INDICATOR 3 4 5 6 7 8 9

10 11 12 13 14 15 16 17 18 19 20

21 22 23 24 25 26 27 28 29 30 31 32 33

RDB/CSB

WRB/SCLK

DVDD

DGND

AD9852

TOP VIEW

(Not to Scale)

DGND

MASTER RESET

OSK

AGND

AVDD

NC

VOUT

DIFF CLK ENABLENCAGND

64 63 62 6167 66 65

AVDD

PLL FILTER

AGND

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

AVDD AGND NC NC DAC R DACBP AVDD AGND IOUT2 IOUT2B AVDD IOUT1B IOUT1 AGND AGND AGND AVDD VINN VINP AGND

SET

NC = NO CONNECT

RGK/BPSK/HOLD

00634-C-002

Figure 2. Pin Configuration

Table 3.

Pin Number Mnemonic Function

1–8 D7–D0 8-bit bidirectional parallel programming data Inputs. Used only in parallel programming mode. 9, 10, 23, 24, 25,

73, 74, 79, 80 11, 12, 26, 27, 28,

DVDD

Connections for the digital circuitry supply voltage. Nominally 3.3 V more positive than AGND and DGND.

DGND Connections for digital circuitry ground return. Same potential as AGND.

72, 75, 76, 77, 78 13, 35, 57, 58, 63 NC No internal connection 14–19 A5–A0

6-bit parallel address inputs for program registers. Used only in parallel programming mode. A0, A1, and A2 have a second function when the serial programming mode is selected. See following descriptions.

17

A2/IO RESET

Allows an IO RESET of the serial communications bus that is unresponsive due to improper programming protocol. Resetting the serial bus in this manner does not affect previous programming,

nor does it invoke the “default” programming values seen in Table 7. Active HIGH. 18 A1/SDO Unidirectional serial data output for use in 3-wire serial communication mode. 19 A0/SDIO Bidirectional serial data input/output for use in 2-wire serial communication mode. 20 I/O UD CLK

Bidirectional I/O update CLK. Direction is selected in control register. If selected as an input, a rising edge

transfers the contents of the I/O port buffers to the programming registers. If I/O UD is selected as an

output (default), an output pulse (low to high) of eight system clock cycle duration indicates that an

internal frequency update has occurred. 21 WRB/SCLK

Write parallel data to I/O port buffers. Shared function with SCLK. Serial clock signal associated with the

serial programming bus. Data is registered on the rising edge. This pin is shared with WRB when the

parallel mode is selected. Mode dependent on Pin 70 (S/P Select).

Rev. C | Page 8 of 48

AD9852

Pin Number Mnemonic Function

22 RDB/CSB

29

FSK/BPSK/ HOLD

30

OUTPUT SHAPED KEYING

31, 32, 37, 38, 44,

AVDD

50, 54, 60, 65 33, 34, 39, 40, 41,

AGND Connections for analog circuitry ground return. Same potential as DGND. 45, 46, 47, 53, 59, 62, 66, 67

36 VOUT

42 VINP Voltage input positive. The internal high speed comparator’s noninverting input. 43 VINN Voltage input negative. The internal high speed comparator’s inverting input. 48 IOUT1 Unipolar current output of the cosine DAC. (Refer to Figure 3.) 49 IOUT1B Complementary unipolar current output of the cosine DAC. 51 IOUT2B Complementary unipolar current output of the control DAC. 52 IOUT2 Unipolar current output of the control DAC. 55 DACBP

56 DAC R

61 PLL FILTER

64

DIFF CLK

ENABLE 68 REFCLKB

69 REFCLK

70 S/P SELECT Selects between serial programming mode (logic low) and parallel programming mode (logic high). 71

MASTER

RESET

AVDD

Read parallel data from programming registers. Shared function with CSB. Chip select signal associated with the serial programming bus. Active low. This pin is shared with RDB when the parallel mode is selected.

Multifunction pin according to the mode of operation selected in the programming control register. If in the FSK mode, logic low selects F1, logic high selects F2. If in the BPSK mode, logic low selects Phase 1, logic high selects Phase 2. In chirp mode, logic high engages the HOLD function causing the frequency accumulator to halt at its current location. To resume or commence chirp, logic low is asserted.

Must first be selected in the programming control register to function. A logic high causes the cosine DAC outputs to ramp up from zero-scale to full-scale amplitude at a preprogrammed rate. Logic low causes the full-scale output to ramp down to zero scale at the preprogrammed rate.

Connections for the analog circuitry supply voltage. Nominally 3.3 V more positive than AGND and DGND.

Internal high speed comparator’s noninverted output pin. Designed to drive 10 dBm to 50 Ω loads as well as standard CMOS logic levels.

Common bypass capacitor connection for both DACs. A 0.01 µF chip cap from this pin to AVDD improves harmonic distortion and SFDR slightly. No connect is permissible (slight SFDR degradation).

Common connection for both DACs to set the full-scale output current. R

SET

= 39.9/ I

SET

. Normal R

OUT

range is from 8 kΩ (5 mA) to 2 kΩ (20 mA). This pin provides the connection for the external zero compensation network of the REFCLK multiplier’s

PLL loop filter. The zero compensation network consists of a 1.3 kΩ resistor in series with a 0.01 µF capacitor. The other side of the network should be connected to AVDD as close as possible to Pin 60. For optimum phase noise performance, the REFCLK multiplier can be bypassed by setting the “Bypass PLL” bit in control register 1E.

Differential REFCLK ENABLE. A high level of this pin enables the differential clock inputs, REFCLK and REFCLKB (Pins 69 and 68, respectively).

The COMPLEMENTARY (180 Degrees Out-of-Phase) differential clock signal. User should tie this pin high or low when single-ended clock mode is selected. Same signal levels as REF CLK.

Single-ended (CMOS logic levels required) reference clock input or one of two differential clock signals. In differential reference clock mode, both inputs can be CMOS logic levels or have greater than 400 mV p-p square or sine waves centered about 1.6 V dc.

Initializes the serial/parallel programming bus to prepare for user programming; sets programming registers to a “do-nothing” state defined by the default values seen in Table 7. Active on logic high. Asserting MASTER RESET is essential for proper operation upon power-up.

DVDD

SET

AVDD

I

OUTIOUTB

MUST TERMINATE OUTPUTS FOR CURRENT FLOW. DO NOT EXCEED THE OUTPUT VOLTAGE COMPLIANCE RATING.

A. DAC Outputs B. Comparator Output C. Comparator Input D. Digital Inputs

COMPARATOR OUT

Figure 3. Equivalent Input and Output Circuits

Rev. C | Page 9 of 48

VINP/

VINN

AVDD

DIGITAL

IN

AVOID OVERDRIVING DIGITAL INPUTS. FORWARD BIASING ESD DIODES MAY COUPLE DIGITAL NOISE ONTO POWER PINS.

00634-C-003

AD9852

–

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 4 to Figure 9 indicate the wideband harmonic distortion performance of the AD9852 from 19.1 MHz to 119.1 MHz fundamental output, reference clock = 30 MHz, REFCLK multiplier = 10. Each graph plotted from 0 MHz to 150 MHz (Nyquist).

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

START 0Hz

15MHz/ STOP 150MHz

00634-C-004

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

START 0Hz

15MHz/ STOP 150MHz

00634-C-007

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

START 0Hz

0

START 0Hz

Figure 4. Wideband SFDR, 19.1 MHz

15MHz/ STOP 150MHz

Figure 5. Wideband SFDR, 39.1 MHz

15MHz/ STOP 150MHz

Figure 6. Wideband SFDR, 59.1 MHz

00634-C-005

00634-C-006

–10

–20

–30

–40

–50

–60

–70

–80

–90

100

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

START 0Hz

0

START 0Hz

Figure 7. Wideband SFDR, 79.1 MHz

15MHz/ STOP 150MHz

Figure 8. Wideband SFDR, 99.1 MHz

15MHz/ STOP 150MHz

Figure 9. Wideband SFDR, 119.1 MHz

00634-C-008

00634-C-009

Rev. C | Page 10 of 48

AD9852

–

Figure 10 to Figure 13 show the trade-off in elevated noise floor, increased phase noise, and discrete spurious energy when the internal REFCLK multiplier circuit is engaged. Plots with wide (1 MHz) and narrow (50 kHz) spans are shown.

Compare the noise floor of Figure 11 and Figure 13 to Figure 14 and Figure 15. The improvement seen in Figure 11 and Figure 13 is a direct result of sampling the fundamental at a higher rate. Sampling at a higher rate spreads the quantization noise of the DAC over a wider bandwidth, which effectively lowers the noise floor.

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

CENTER 39.1MHz

100kHz/ SPAN 1MHz

00634-C-010

Figure 10. Narrow-band SFDR, 39.1 MHz, 1 MHz BW, 300 MHz REFCLK with

REFCLK Multiply Bypassed

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

100

CENTER 39.1MHz

5kHz/ SPAN 50kHz

00634-C-011

Figure 11. Narrow-band SFDR, 39.1 MHz, 50 kHz BW, 300 MHz REFCLK with

REFCLK Multiplier Bypassed

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

CENTER 39.1MHz

5kHz/ SPAN 50kHz

00634-C-012

Figure 12. Narrow-band SFDR, 39.1 MHz, 50 kHz BW, 100 MHz, REFCLK with

REFCLK Multiplier Bypassed

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

CENTER 39.1MHz

100kHz/ SPAN 1MHz

00634-C-013

Figure 13. Narrow-band SFDR, 39.1 MHz, 1 MHz BW, 30 MHz REFCLK with

REFCLK Multiply =10x

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

CENTER 39.1MHz

5kHz/ SPAN 50kHz

00634-C-014

Figure 14. Narrow-band SFDR, 39.1 MHz, 50 kHz BW, 30 MHz REFCLK with

REFCLK Multiplier = 10x

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

CENTER 39.1MHz

5kHz/ SPAN 50kHz

00634-C-015

Figure 15. Narrow-band SFDR, 39.1 MHz, 50 kHz BW, 10 MHz REFCLK with

REFCLK Multiplier = 10x

Rev. C | Page 11 of 48

AD9852

Figure 17 shows the narrow-band performance of the AD9852 when operating with a 20 MHz reference clock and the REFCLK multiplier enabled at 10×vs. a 200 MHz reference clock with REFCLK multiplier bypassed.

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

CENTER 112.469MHz

50kHz/ SPAN 500kHz

00634-C-016

–90

–100

–110

–120

–130

–140

PHASE NOISE (dBc/Hz)

–150

A

= 5MHz

OUT

–160

10 1M100 100k10k1k

A

= 80MHz

OUT

FREQUENCY (Hz)

00634-C-019

Figure 16. A Slight Change in Tuning Word Yields Dramatically Better Results.

112.469 MHz with All Spurs Shifted Out-of-Band. RECLK is 300 MHz.

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

CENTER 39.1MHz

5kHz/ SPAN 50kHz

00634-C-017

Figure 17. Narrow-band SFDR, 39.1 MHz, 50 kHz BW, 200 MHz REFCLK with

REFCLK Multiplier Bypassed

–100

–110

–120

–130

–140

–150

PHASE NOISE (dBc/Hz)

–160

–170

10 1M100 100k10k1k

A

OUT

= 5MHz

A

= 80MHz

OUT

FREQUENCY (Hz)

00634-C-018

Figure 19. Residual Phase Noise, 30 MHz REFCLK with

REFCLK Multiplier = 10x

55

54

53

52

51

SFDR (dBc)

50

49

48

0

5 10152025

DAC CURRENT (mA)

Figure 20. SFDR vs. DAC Current, 59.1 A

Multiplier Bypassed

620

615

610

605

600

SUPPLY CURRENT (mA)

595

590

0

20 40 60 80 100 120 140

FREQUENCY (MHz)

, 300 MHz REFCLK with REFCLK

OUT

00634-C-020

00634-C-021

Figure 18. Residual Phase Noise, 300 MHz REFCLK with REFCLK Multiplier

Bypassed

Rev. C | Page 12 of 48

Figure 21. Supply Current vs. Output Frequency; Variation Is Minimal as a

Percentage and Heavily Dependent on Tuning Word

AD9852

1200

1000

RISE TIME

1.04ns

800

[10.6ps RMS]

–33ps 0ps +33ps

500ps/DIV 232mV/DIV 50Ω INPUT

Figure 22. Typical Comparator Output Jitter, 40 MHz A

with REFCLK Multiplier Bypassed

CH1 500mVΩ M 500ps CH1

Figure 23. Comparator Rise/Fall Times

JITTER

, 300 MHz REFCLK

OUT

REF1 RISE

1.174ns

C1 FALL

1.286ns

980mV

00634-C-022

00634-C-023

600

400

AMPLITUDE (mV p-p)

200

0

100 200 300 400 500

MINIMUM COMPARATOR INPUT DRIVE V

= 0.5V

CM

FREQUENCY (MHz)

00634-C-024

Figure 24. Comparator Toggle Voltage Requirement

Rev. C | Page 13 of 48

AD9852

TYPICAL APPLICATIONS

RF/IF

INPUT

BASEBAND

REFCLK

Rx

RF IN

VCA

ADC CLOCK FREQUENCY

Figure 26. Chip Rate Generator in Spread Spectrum Application

BAND-PASS

FC + F

IMAGE

FILTER

O

AD9852

SPECTRUM

FUNDAMENTAL

FC– F

IMAGE

I

OUT

50Ω

O

F

CLK

Figure 27. Using an Aliased Image to Generate a High Frequency

AMPLIFIER

50Ω

FINAL OUTPUT

SPECTRUM

FC + F

AD9852

LOW-PASS

FILTER

COS

Figure 25. Synthesized LO Application for the AD9852

I/Q MIXER

AND

LOW-PASS

FILTER

LOCKED TO Tx CHIP/

SYMBOL/PN RATE

REFERENCE

CLOCK

O

IMAGE

BAND-PASS FILTER

I

Q

DUAL

8-/10-BIT

ADC

AD9852

CLOCK

GENERATOR

00634-C-027

8

ADC ENCODE

48

CHIP/SYMBOL/PN

RATE DATA

REFERENCE

CLOCK

DIGITAL

DEMODULATOR

AD9852

DDS

TUNING

WORD

Figure 29. Agile High Frequency Synt hesizer

00634-C-025

AGC

FILTER

Rx BASEBAND DIGITAL DATA OUT

PHASE

COMPARATOR

DIVIDE-BY-N

00634-C-026

LOOP

FILTER

RF FREQUENCY

OUT

VCO

00634-C-029

REFERENCE

CLOCK

LOOP

FILTER

REF CLK IN

“DIVIDE-BY-N” FUNCTION

(WHERE N = 2

VCO

PROGRAMMABLE

48

/TUNING WORD)

FILTER

DAC OUT

PHASE

COMPARATOR

AD9852

DDS

TUNING

WORD

Figure 28. Programmable Fractional Divide-by-N Synthesizer

RF FREQUENCY

OUT

REFERENCE

00634-C-028

Rev. C | Page 14 of 48

DIFFERENTIAL

TRANSFORMER-COUPLED

OUTPUT

I

CLOCK

AD9852

DDS

OUT

I

OUT

50Ω

1:1 TRANSFORMER

I.E., MINI-CIRCUITS T1-1T

Figure 30. Differential Output Connection for Reduction

of Common-Mode Signals

FILTER

50Ω

00634-C-030

AD9852

µPROCESSOR/

CONTROLLER

FPGA, ETC.

REFERENCE

CLOCK

AD9852

8-BIT PARALLEL OR SERIAL PROGRAMMING DATA AND CONTROL SIGNALS

300MHz MAX DIRECT MODE OR 15 TO 75MHZ MAX IN THE 4× – 20× CLOCK MULTIPLIER MODE

2kΩ

R

SET

COSINE

DAC

CONTROL

DAC

1

2

LOW-PASS

FILTER

LOW-PASS

FILTER

NOTES

= APPROX 20mA MAX WHEN R

I

OUT

SWITCH POSTION 1 PROVIDES COMPLEMENTARY SINUSOIDAL SIGNALS TO THE COMPARATOR TO PRODUCE A FIXED 50% DUTY CYCLE FROM THE COMPARATOR.

SWITCH POSTION 2 PROVIDES A USER-PROGRAMMABLE DC THRESHOLD VOLTAGE TO ALLOW SETTING OF THE COMPARATOR DUTY CYCLE.

SET

= 2kΩ

CMOS LOGIC “CLOCK” OUT

00634-C-031

Figure 31. Frequency Agile Clock Generator Applications for the AD9852

Rev. C | Page 15 of 48