Analog Devices AD9849KST, AD9848KST Datasheet

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

a

AD9848/AD9849

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

CCD Signal Processors with

Integrated Timing Driver

FUNCTIONAL BLOCK DIAGRAM

CLAMP

DOUT

CCDIN

PBLK

VRT

VRB

INTERNAL

REGISTERS

2dB TO 36dB

SYNC

GENERATOR

SDATASCK

SL

CLPOB

10 OR 12

VGA

AD9848/AD9849

4ⴞ6dB

PRECISION

TIMING

TM

CORE

ADC

VREF

CLAMP

INTERNAL

CLOCKS

PxGA

CDS

HORIZONTAL

DRIVERS

4

RG

H1–H4

HD

VD

CLI

CLPDM

FEATURES
AD9848: 10-Bit, 20 MHz Version
AD9849: 12-Bit, 30 MHz Version
Correlated Double Sampler (CDS)
–2 dB to +10 dB Pixel Gain Amplifier (

PxGA

®

)
2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)
10-Bit 20 MHz A/D Converter (AD9848)
12-Bit 30 MHz A/D Converter (AD9849)
Black Level Clamp with Variable Level Control
Complete On-Chip Timing Driver

Precision Timing

™

Core with 1 ns Resolution @ 20 MSPS
On-Chip 3 V Horizontal and RG Drivers (AD9848)
On-Chip 5 V Horizontal and RG Drivers (AD9849)
48-Lead LQFP Package

APPLICATIONS
Digital Still Cameras

PRODUCT DESCRIPTION

The AD9848 and AD9849 are highly integrated CCD signal pro­cessors for digital still camera applications. Both include a complete
analog front end with A/D conversion, combined with a program­mable timing driver. The Precision Timing core allows adjustment
of high speed clocks with approximately 1 ns resolution.

The AD9848 is specified at pixel rates of 20 MHz, and the
AD9849 is specified at 30 MHz. The analog front end includes
black level clamping, CDS, PxGA, VGA, and a 10- or 12-bit A/D
converter. The timing driver provides the high-speed CCD clock
drivers for RG and H1-H4. Operation is programmed using a
3-wire serial interface.

Packaged in a space-saving 48-lead LQFP, the AD9848 and
AD9849 are specified over an operating temperature range of
–20°C to +85°C.

PxGA is a registered trademark and Precision Timing is a trademark of Analog Devices, Inc.

REV. 0

–2–

AD9848/AD9849

–TARGET SPECIFICATIONS

GENERAL SPECIFICATIONS

Parameter Min Typ Max Unit

TEMPERATURE RANGE

Operating –20 +85 °C
Storage –65 +150 °C

MAXIMUM CLOCK RATE

AD9848 20 MHz
AD9849 30 MHz

POWER SUPPLY VOLTAGE, AD9848

Analog (AVDD1, 2, 3) 2.7 3.6 V
Digital1 (DVDD1) H1–H4 2.7 3.6 V
Digital2 (DVDD2) RG 2.7 3.6 V
Digital3 (DVDD3) D0–D11 3.0 V
Digital4 (DVDD4) All Other Digital 3.0 V

POWER SUPPLY VOLTAGE, AD9849

Analog (AVDD1, 2, 3) 2.7 3.6 V
Digital1 (DVDD1) H1–H4 3.0 5.5 V
Digital2 (DVDD2) RG 3.0 5.5 V
Digital3 (DVDD3) D0–D11 3.0 V
Digital4 (DVDD4) All Other Digital 3.0 V

POWER DISSIPATION, AD9848

20 MHz, DVDD1, 2 = 3 V, 100 pF H Loading 220 mW
Total Shutdown Mode 1 mW

POWER DISSIPATION, AD9849

30 MHz, DVDD1, 2 = 5 V, 100 pF H Loading 450 mW
Total Shutdown Mode 1 mW

Specifications subject to change without notice.

REV. 0

–3–

AD9848/AD9849

(T

MIN

to T

MAX

, AVDD1 = DVDD3, DVDD4 = 2.7 V, DVDD1, DVDD2 = 2.7 V [AD9848], DVDD1,

DVDD2 = 5.25 V [AD9849], CL = 20 pF, unless otherwise noted.)

DIGITAL SPECIFICATIONS

Parameter Symbol Min Typ Max Unit

LOGIC INPUTS

High Level Input Voltage V

IH

2.1 V

Low Level Input Voltage V

IL

0.6 V

High Level Input Current I

IH

10 µA

Low Level Input Current I

IL

10 µA

Input Capacitance C

IN

10 pF

LOGIC OUTPUTS

High Level Output Voltage, IOH = 2 mA V

OH

2.2 V

Low Level Output Voltage, IOL = 2 mA V

OL

0.5 V

CLI INPUT

High Level Input Voltage

(AVDD1, 2 +0.5 V) V

IH–CLI

1.85 V

Low Level Input Voltage V

IL–CLI

0.85 V

RG AND H-DRIVER OUTPUTS, AD9848

High Level Output Voltage

(DVDD1, 2 –0.5 V) V

OH

2.2 V

Low Level Output Voltage V

OL

0.5 V
Maximum Output Current (Programmable) 24 mA
Maximum Load Capacitance 100 pF

RG AND H-DRIVER OUTPUTS, AD9849

High Level Output Voltage

(DVDD1, 2 –0.5 V) V

OH

4.75 V

Low Level Output Voltage V

OL

0.5 V
Maximum Output Current (Programmable) 24 mA
Maximum Load Capacitance 100 pF

Specifications subject to change without notice.

REV. 0

–4–

AD9848/AD9849

AD9848–ANALOG SPECIFICATIONS

(T

MIN

to T

MAX

, AVDD = DVDD = 3.0 V, f

CLI

= 20 MHz, unless otherwise noted.)

Parameter Min Typ Max Unit Notes

CDS

Gain 0 dB
Allowable CCD Reset Transient

1

500 mV See Input Waveform in Note 1

Max Input Range Before Saturation

1

1.0 V p-p

Max CCD Black Pixel Amplitude

1

150 mV

PIXEL GAIN AMPLIFIER (PxGA)

Max Input Range 1.0 V p-p
Max Output Range 1.6 V p-p
Gain Control Resolution 64 Steps
Gain Monotonicity Guaranteed
Gain Range

Min Gain (32) –2 dB
Med Gain (0) 4 dB Medium Gain (4 dB) Is Default Setting
Max Gain (31) 10 dB

VARIABLE GAIN AMPLIFIER (VGA)

Max Input Range 1.6 V p-p
Max Output Range 2.0 V p-p
Gain Control Resolution 1024 Steps
Gain Monotonicity Guaranteed
Gain Range

Low Gain (91) 2 dB
Max Gain (1023) 36 dB

BLACK LEVEL CLAMP

Clamp Level Resolution 256 Steps
Clamp Level Measured at ADC Output

Min Clamp Level (0) 0 LSB
Max Clamp Level (255) 63.75 LSB

A/D CONVERTER

Resolution 10 Bits
Differential Nonlinearity (DNL) ± 0.4 ± 1.0 LSB
No Missing Codes Guaranteed
Full-Scale Input Voltage 2.0 V

VOLTAGE REFERENCE

Reference Top Voltage (VRT) 2.0 V
Reference Bottom Voltage (VRB) 1.0 V

SYSTEM PERFORMANCE

VGA Gain Accuracy Specifications Include Entire Signal Chain

Gain Includes 4 dB Default PxGA Gain
Low Gain (91) 5 6 7 dB
Max Gain (1023) 38 39.5 41 dB

Peak Nonlinearity, 500 mV Input Signal 0.2 % 12 dB Gain Applied
Total Output Noise 0.2 LSB rms AC Grounded Input, 6 dB Gain Applied
Power Supply Rejection (PSR) 40 dB Measured with Step Change on Supply

NOTES

1

Input signal characteristics defined as follows:

500mV TYP

RESET

TRANSIENT

150mV MAX

OPTICAL

BLACK PIXEL

1V MAX

INPUT

SIGNAL RANGE

Specifications subject to change without notice.

REV. 0

–5–

AD9848/AD9849

AD9849–ANALOG SPECIFICATIONS

(T

MIN

to T

MAX

, AVDD = DVDD = 3.0 V, f

CLI

= 30 MHz, unless otherwise noted.)

Parameter Min Typ Max Unit Notes

CDS

Gain 0 dB
Allowable CCD Reset Transient

1

500 mV See Input Waveform in Note 1

Max Input Range Before Saturation

1

1.0 V p-p

Max CCD Black Pixel Amplitude

1

150 mV

PIXEL GAIN AMPLIFIER (PxGA)

Max Input Range 1.0 V p-p
Max Output Range 1.6 V p-p
Gain Control Resolution 64 Steps
Gain Monotonicity Guaranteed
Gain Range

Min Gain (32) –2 dB
Med Gain (0) 4 dB Medium Gain (4 dB) Is Default Setting
Max Gain (31) 10 dB

VARIABLE GAIN AMPLIFIER (VGA)

Max Input Range 1.6 V p-p
Max Output Range 2.0 V p-p
Gain Control Resolution 1024 Steps
Gain Monotonicity Guaranteed
Gain Range

Low Gain (91) 2 dB
Max Gain (1023) 36 dB

BLACK LEVEL CLAMP

Clamp Level Resolution 256 Steps
Clamp Level Measured at ADC Output

Min Clamp Level (0) 0 LSB
Max Clamp Level (255) 255 LSB

A/D CONVERTER

Resolution 12 Bits
Differential Nonlinearity (DNL) ± 0.5 ± 1.0 LSB
No Missing Codes Guaranteed
Full-Scale Input Voltage 2.0 V

VOLTAGE REFERENCE

Reference Top Voltage (VRT) 2.0 V
Reference Bottom Voltage (VRB) 1.0 V

SYSTEM PERFORMANCE

Gain Accuracy Specifications Include Entire Signal Chain

Gain Includes 4 dB Default PxGA Gain
Low Gain (91) 5 6 7 dB
Max Gain (1023) 38 39.5 41 dB

Peak Nonlinearity, 500 mV Input Signal 0.2 % 12 dB Gain Applied
Total Output Noise 0.6 LSB rms AC Grounded Input, 6 dB Gain Applied
Power Supply Rejection (PSR) 40 dB Measured with Step Change on Supply

NOTES

1

Input signal characteristics defined as follows:

500mV TYP

RESET

TRANSIENT

150mV MAX

OPTICAL

BLACK PIXEL

1V MAX

INPUT

SIGNAL RANGE

Specifications subject to change without notice.

REV. 0

–6–

AD9848/AD9849

TIMING SPECIFICATIONS

(CL = 20 pF, f

CLI

= 20 MHz [AD9848] or 30 MHz [AD9849], Serial Timing in Figure 3, unless

otherwise noted.)

Parameter Symbol Min Typ Max Unit

MASTER CLOCK (CLI), AD9848

CLI Clock Period t

CLI

50 ns

CLI High/Low Pulsewidth t

ADC

25 ns

Delay From CLI to Internal Pixel Period Position t

CLIDLY

6ns

MASTER CLOCK (CLI), AD9849

CLI Clock Period t

CONV

33.33 ns

CLI High/Low Pulsewidth t

ADC

16.67 ns

EXTERNAL MODE CLAMPING

CLPDM Pulsewidth t

CDM

4 10 Pixels

CLPOB Pulsewidth

1

t

COB

2 20 Pixels

SAMPLE CLOCKS

SHP Rising Edge to SHD Rising Edge (AD9848) t

S1

20 ns

SHP Rising Edge to SHD Rising Edge (AD9849) t

S1

13 ns

DATA OUTPUTS

Output Delay from Programmed Edge t

OD

6ns

Pipeline Delay 9 Cycles

SERIAL INTERFACE

Maximum SCK Frequency f

SCLK

10 MHz

SL to SCK Setup Time t

LS

10 ns

SCK to SL Hold Time t

LH

10 ns

SDATA Valid to SCK Rising Edge Setup t

DS

10 ns

SCK Falling Edge to SDATA Valid Hold t

DH

10 ns

SCK Falling Edge to SDATA Valid Read t

DV

10 ns

NOTES

1

Maximum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp reference.

Specifications subject to change without notice.

REV. 0

AD9848/AD9849

–7–

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

AD9848KST –20°C to +85°C Thin Plastic Quad Flatpack (LQFP) ST-48
AD9849KST –20°C to +85°C Thin Plastic Quad Flatpack (LQFP) ST-48

ABSOLUTE MAXIMUM RATINGS

With
Respect

Parameter To Min Max Unit

AVDD1, 2, 3 AVSS –0.3 +3.9 V
DVDD1, DVDD2 (AD9848) DVSS –0.3 +3.9 V
DVDD1, DVDD2 (AD9849) DVSS –0.3 +5.5 V
DVDD3, 4 DVSS –0.3 +3.9 V
Digital Outputs DVSS3 –0.3 DVDD3 + 0.3 V
CLPOB, CLPDM, BLK DVSS4 –0.3 DVDD4 + 0.3 V
CLI AVSS –0.3 AVDD + 0.3 V
SCK, SL, SDATA DVSS4 –0.3 DVDD4 + 0.3 V
VRT, VRB AVSS –0.3 AVDD + 0.3 V
BYP1 – 3, CCDIN AVSS –0.3 AVDD + 0.3 V
Junction Temperature 150 °C
Lead Temperature (10 sec) 300 °C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9848/AD9849 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

THERMAL CHARACTERISTICS

Thermal Resistance

48-Lead LQFP Package

␪

JA

= 92°C

REV. 0

AD9848/AD9849

–8–

36

35

34

33

32

31

30

29

28

27

26

25

13 14 15 16 17 18 19 20 21 22 23 24

1

2

3

4

5

6

7

8

9

10

11

12

48 47 46 45 44 39 38 3743 42 41 40

PIN 1
IDENTIFIER

TOP VIEW

(Not to Scale)

SL

REFT

REFB

CMLEVEL

AVSS3

AVDD3

CCDIN

(LSB) D0

D1

D2

D3

D4

NC = NO CONNECT

DVSS3

DVDD3

D5

D6

BYP2

AVDD2

AD9848

D7

AVSS2

NCNCDVDD4

DVSS4HDVD

PBLK

HBLK

CLPDM

CLPOB

SCK

SDI

H1

H2

DVSS1

DVDD1

H3

H4

DVSS2

RG

DVDD2

AVSS1

CLI

AVDD1

D8

(MSB) D9

BYP1

BYP3

36

35

34

33

32

31

30

29

28

27

26

25

13 14 15 16 17 18 19 20 21 22 23 24

1

2

3

4

5

6

7

8

9

10

11

12

48 47 46 45 44 39 38 3743 42 41 40

PIN 1
IDENTIFIER

TOP VIEW

(Not to Scale)

SL

REFT

REFB

CMLEVEL

AVSS3

AVDD3

CCDIN

D2

D3

D4

DVSS3

DVDD3

D5

D6

BYP2

AVDD2

AD9849

D7

AVSS2

D1

D0 (LSB)

DVDD4

DVSS4HDVD

PBLK

HBLK

CLPDM

CLPOB

SCK

SDI

H1

H2

DVSS1

DVDD1

H3

H4

DVSS2

RG

DVDD2

AVSS1

CLI

AVDD1

D8

(MSB) D11

BYP1

BYP3

D9

D10

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Type Description

1–5 D0–D4 DO Data Outputs AD9848 Only
1–5 D2–D6 DO Data Outputs AD9849 Only
6 DVSS3 P Digital Ground 3 – Data Outputs
7 DVDD3 P Digital Supply 3 – Data Outputs
8–12 D5–D9 DO Data Outputs (D9 is MSB) AD9848 Only
8–12 D7–D11 DO Data Outputs (D9 is MSB) AD9849 Only
13, 14 H1, H2 DO Horizontal Clocks (to CCD)
15 DVSS1 P Digital Ground 1 – H Drivers
16 DVDD1 P Digital Supply 1 – H Drivers
17, 18 H3, H4 DO Horizontal Clocks (to CCD)
19 DVSS2 P Digital Ground 1 – H Drivers
20 RG DO Reset Gate Clock (to CCD)
21 DVDD2 P Digital Supply 2 – RG Driver
22 AVSS1 P Analog Ground 1
23 CLI DI Master Clock Input
24 AVDD1 P Analog Supply 1
25 AVSS2 P Analog Ground 2
26 AVDD2 P Analog Supply 2
27 BYP1 AO Bypass Pin (0.1 µF to AVSS)
28 BYP2 AO Bypass Pin (0.1 µF to AVSS)
29 CCDIN AI Analog Input for CCD Signal
30 BYP3 AO Bypass Pin (0.1 µF to AVSS)
31 AVDD3 P Analog Supply 3
32 AVSS3 P Analog Ground 3
33 CMLEVEL AO Internal Bias Level Decoupling (0.1 µF to AVSS)
34 REFB AO Reference Bottom Decoupling (1.0 µF to AVSS)
35 REFT AO Reference Top Decoupling (1.0 µF to AVSS)
36 SL DI 3-Wire Serial Load (from µP)
37 SDI DI 3-Wire Serial Data Input (from µP)
38 SCK DI 3-Wire Serial Clock (from µP)
39 CLPOB DI Optical Black Clamp Pulse
40 CLPDM DI Dummy Black Clamp Pulse
41 HBLK DI HCLK Blanking Pulse
42 PBLK DI Preblanking Pulse
43 VD DI Vertical Sync Pulse
44 HD DI Horizontal Sync Pulse
45 DVSS4 P Digital Ground 4 – VD, HD, CLPOB, CLPDM, HBLK, PBLK, SCK, SL, SDATA
46 DVDD4 P Digital Supply 4 – VD, HD, CLPOB, CLPDM, HBLK, PBLK, CK, SL, SDATA
47, 48 NC NC Internally Not Connected AD9848 Only
47, 48 D0, D1 DO Data Output (D0 is LSB) AD9849 Only

NOTE
Type: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power

PIN CONFIGURATION

REV. 0

–9–

AD9848/AD9849

EQUIVALENT INPUT/OUTPUT CIRCUITS

R

AVDD2

AVSS2

AVSS2

Circuit 1. CCDIN (Pin 29)

AVDD1

AVSS1

330⍀

CLI

25k⍀

1.4V

Circuit 2. CLI (Pin 23)

DVDD4 DVDD3

DVSS4 DVSS3

DATA

THREE-

STATE

DOUT

Circuit 3. Data Outputs D0–D11 (Pins 1–5, 8–12, 47–48)

DVDD4

DVSS4

330⍀

Circuit 4. Digital Inputs (Pins 36–44)

DVDD1

DVSS1

DATA

ENABLE

OUTPUT

Circuit 5. H1–H4 and RG (Pins 13, 14, 17, 18, 20)

REV. 0

AD9848/AD9849

–10–

—Typical Linearity and Noise Performance Characteristics

–0.50

0

1000

400

200 600 800

–0.25

0

0.25

0.50

TPC 1. AD9848 Typical DNL

VGA GAIN CODE – LSB

0

0

1000

400

OUTPUT NOISE – LSB

200

1

600 800

2

3

4

TPC 2. AD9848 Output Noise vs. VGA Gain Setting

0

1000

500

1500 2000 2500 3000 3500 4000

0

–0.5

0.5

–0.25

0.25

TPC 3. AD9849 Typical DNL

VGA GAIN CODE – LSB

15

0

0

1000

400

OUTPUT NOISE – LSB

200

5

600

10

800

TPC 4. AD9849 Output Noise vs. VGA Gain Setting

REV. 0

AD9848/AD9849

–11–

SYSTEM OVERVIEW

CCD

SERIAL

INTERFACE

DOUT

DIGITAL IMAGE

PROCESSING

ASIC

V-DRIVER

HD, VD

CLI

V1–V4, VSG1–VSG8, SUBCK

H1–H4, RG

CCDIN

AD9848/AD9849

INTEGRATED

AFE+TD

Figure 1a. Typical Application (Internal Mode)

CCD

SERIAL

INTERFACE

DOUT

DIGITAL IMAGE

PROCESSING

ASIC

V-DRIVER

HD, VD

CLI

V1–V4, VSG1–VSG8, SUBCK

H1–H4, RG

CCDIN

AD9848/AD9849

INTEGRATED

AFE+TD

PBLK

HBLK

CLPDM

CLPOB

Figure 1b. Typical Application (External Mode)

Figure 1a and 1b show the typical system application diagrams
for the AD9848/AD9849. The CCD output is processed by the
AD9848/AD9849’s AFE circuitry, which consists of a CDS,
PxGA, VGA, black level clamp, and A/D converter. The digi­tized pixel information is sent to the digital image processor
chip, where all post-processing and compression occurs. To
operate the CCD, CCD timing parameters are programmed
into the AD9848/AD9849 from the image processor, through
the 3-wire serial interface. From the system master clock, CLI,
provided by the image processor, the AD9848/AD9849 gener­ates the high speed CCD clocks and all internal AFE clocks. All
AD9848/AD9849 clocks are synchronized with VD and HD.

Figure 1a shows the AD9848/AD9849 used in Internal mode,
in which all the horizontal pulses (CLPOB, CLPDM, PBLK,
and HBLK) are programmed and generated internally. Figure 1b
shows the AD9848/AD9849 operating in external mode, in
which the horizontal pulses are supplied externally by the
image processor.

The H-drivers for H1–H4 and RG are included in the AD9848/
AD9849, allowing these clocks to be directly connected to the
CCD. H-drive voltage of 5 V is supported in the AD9849.

Figure 2 shows the horizontal and vertical counter dimensions
for the AD9848/AD9849. All internal horizontal clocking is
programmed using these dimensions, to specify line and
pixel locations.

MAXIMUM FIELD DIMENSIONS

12-BIT HORIZONTAL = 4096 PIXELS MAX

12-BIT VERTICAL = 4096 LINES MAX

Figure 2. Vertical and Horizontal Counters