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AD9847 A
Datasheet
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Analog Devices AD9847 A Datasheet

10-Bit 40 MSPS CCD Signal Processor
a
FEATURES Correlated Double Sampler (CDS) –2 dB to +10 dB Pixel Gain Amplifier ( 2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA) 10-Bit 40 MHz A/D Converter Black Level Clamp with Variable Level Control Complete On-Chip Timing Driver
Precision Timing
™ Core with 500 ps
Resolution at 40 MSPS On-Chip 5 V Horizontal and RG Drivers 48-Lead LQFP Package
APPLICATIONS Digital Still Cameras
®
PxGA
)

FUNCTIONAL BLOCK DIAGRAM

with Integrated Timing Driver
AD9847

GENERAL DESCRIPTION

The AD9847 is a highly integrated CCD signal processor for digital still camera applications. The AD9847 includes a com­plete analog front end with A/D conversion, combined with a programmable timing driver. The Precision Timing core allows adjustment of high speed clocks with approximately 500 ps resolution at clock speeds of 40 MHz.
The AD9847 is specified at pixel rates of 40 MHz. The analog front end includes black level clamping, CDS, PxGA, VGA, and a 10-bit A/D converter. The timing driver provides the high speed CCD clock drivers for RG and H1–H4. Operation is programmed using a 3-wire serial interface.
Packaged in a space-saving 48-lead LQFP, the AD9847 is speci­fied over an operating temperature range of –20°C to +85°C.
VRB
VRT
CCDIN
RG
H1–H4
4
AD9847
CDS
HORIZONTAL
DRIVERS
CLAMP
4 6dB
PxGA
2dB TO 36dB
VGA
INTERNAL
CLOCKS
PRECISION
TIMING
CORE
SYNC
GENERATOR
HD VD
VREF
ADC
CLAMP
INTERNAL
REGISTERS
SL
10
DOUT
CLPOB
CLPDM
PBLK
CLI
SDATASCK
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
AD9847
–SPECIFICATIONS
GENERAL SPECIFICATIONS
Parameter Min Typ Max Unit
TEMPERATURE RANGE
Operating –20 +85 °C Storage –65 +150 °C
MAXIMUM CLOCK RATE 40 MHz
POWER SUPPLY VOLTAGE
Analog (AVDD1, 2, 3) 2.7 3.6 V Digital1 (DVDD1) H1–H4 3.0 5.5 V Digital2 (DVDD2) RG 3.0 5.5 V Digital3 (DVDD3) D0–D11 3.0 V Digital4 (DVDD4) All Other Digital 3.0 V
POWER DISSIPATION
DVDD1 (@ 5 V, 100 pF H Loading, 40 MSPS) 450 mW DVDD2 (@ 5 V, 20 pF RG Loading, 40 MSPS) 45 mW DVDD1 (@ 3 V, 100 pF H Loading, 40 MSPS) 180 mW DVDD2 (@ 3 V, 20 pF H Loading, 40 MSPS) 15 mW AVDD1, 2, 3, DVDD3, 4 (@ 3 V, 40 MSPS) 200 mW Total Shutdown Mode 1 mW
Specifications subject to change without notice.
(T
to T
MIN
DIGITAL SPECIFICATIONS
Parameter Symbol Min Typ Max Unit
LOGIC INPUTS
High Level Input Voltage V Low Level Input Voltage V High Level Input Current I Low Level Input Current I Input Capacitance C
LOGIC OUTPUTS
High Level Output Voltage, I Low Level Output Voltage, IOL = 2 mA V
CLI INPUT
High Level Input Voltage
(AVDD1, 2 + 0.5 V) V
Low Level Input Voltage V
RG AND H-DRIVER OUTPUTS
High Level Output Voltage
(DVDD1, 2 – 0.5 V) V Low Level Output Voltage V Maximum Output Current (Programmable) 24 mA Maximum Load Capacitance 100 pF
Specifications subject to change without notice.
OH
otherwise noted.)
= 2 mA V
, AVDD1 = DVDD3, DVDD4 = 2.7 V, DVDD1, DVDD2 = 5.25 V, CL = 20 pF, unless
MAX
IH
IL
IH
IL
IN
OH
OL
IH–CLI
IL–CLI
OH
OL
2.1 V
0.6 V 10 µA 10 µA 10 pF
2.2 V
0.5 V
1.85 V
0.85 V
4.75 V
0.5 V
–2–
REV. A
AD9847
(T
to T
ANALOG SPECIFICATIONS
MIN
, AVDD = DVDD = 3.0 V, f
MAX
Parameter Min Typ Max Unit Notes
CDS
Gain 0 dB Allowable CCD Reset Transient* 500 mV Max Input Range before Saturation* 1.0 V p-p Max CCD Black Pixel Amplitude* 150 mV
PIXEL GAIN AMPLIFIER (PxGA)
Max Input Range 1.0 V p-p Max Output Range 1.6 V p-p Gain Control Resolution 64 Steps Gain Monotonicity Guaranteed Gain Range
Min Gain (32) –2 dB Med Gain (0) 4 dB Max Gain (31) 10 dB
VARIABLE GAIN AMPLIFIER (VGA)
Max Input Range 1.6 V p-p Max Output Range 2.0 V p-p Gain Control Resolution 1024 Steps Gain Monotonicity Guaranteed Gain Range
Low Gain (91) 2 dB Max Gain (1023) 36 dB
BLACK LEVEL CLAMP
Clamp Level Resolution 256 Steps Clamp Level Measured at ADC Output
Min Clamp Level (0) 0 LSB Max Clamp Level (255) 63.75 LSB
A/D CONVERTER
Resolution 10 Bits Differential Nonlinearity (DNL) ± 0.4 ± 1.0 LSB No Missing Codes Guaranteed Full-Scale Input Voltage 2.0 V
VOLTAGE REFERENCE
Reference Top Voltage (VRT) 2.0 V Reference Bottom Voltage (VRB) 1.0 V
SYSTEM PERFORMANCE Specifications Include Entire
Gain Accuracy Gain Includes 4 dB Default PxGA
Low Gain (91) 5 6 7 dB
Max Gain (1023) 38 dB Peak Nonlinearity, 500 mV Input Signal 0.2 % 12 dB Gain Applied Total Output Noise 0.25 LSB rms AC Grounded Input, 6 dB Gain Applied Power Supply Rejection (PSR) 40 dB Measured with Step Change on Supply
*Input signal characteristics defined as follows:
= 40 MHz, unless otherwise noted.)
CLI
Med Gain (4 dB) Is Default Setting
Signal Chain
500mV TYP
RESET
TRANSIENT
Specifications subject to change without notice.
150mV MAX
OPTICAL
BLACK PIXEL
1V MAX
INPUT
SIGNAL RANGE
REV. A
–3–
AD9847
TIMING SPECIFICATIONS
(CL to 29 pF, f
= 40 MHz, Serial Timing in Figures 3a and 3b, unless otherwise noted.)
CLI
Parameter Symbol Min Typ Max Unit
MASTER CLOCK (CLI)
CLI Clock Period t CLI High/Low Pulsewidth t
CLI
ADC
25 ns
12.5 ns
Delay from CLI to Internal Pixel
Period Position t
CLIDLY
6ns
EXTERNAL MODE CLAMPING
CLPDM Pulsewidth t CLPOB Pulsewidth* t
CDM
COB
410Pixels 220 Pixels
SAMPLE CLOCKS
SHP Rising Edge to SHD Rising Edge t
S1
10 ns
DATA OUTPUTS
Output Delay from Programmed Edge t
OD
6ns
Pipeline Delay 9 Cycles
SERIAL INTERFACE
Maximum SCK Frequency f SL to SCK Setup Time t SCK to SL Hold Time t SDATA Valid to SCK Rising Edge Setup t SCK Falling Edge to SDATA Valid Hold t SCK Falling Edge to SDATA Valid Read t
*Maximum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp reference.
Specifications subject to change without notice.
SCLK
LS
LH
DS
DH
DV
10 MHz 10 ns 10 ns 10 ns 10 ns 10 ns
–4–
REV. A
AD9847

ABSOLUTE MAXIMUM RATINGS

AVDD1, 2, 3 to AVSS . . . . . . . . . . . . . . . . . . . –0.3 to +3.9 V
DVDD1, 2 to DVSS . . . . . . . . . . . . . . . . . . . . –0.3 to +5.5 V
DVDD3, 4 to DVSS . . . . . . . . . . . . . . . . . . . . –0.3 to +3.9 V
Digital Outputs to DVSS3 . . . . . . . . –0.3 to DVDD3 + 0.3 V
CLPOB, CLPDM, BLK to DVSS4 . –0.3 to DVDD4 + 0.3 V
CLI to AVSS . . . . . . . . . . . . . . . . . . . –0.3 to AVDD + 0.3 V
SCK, SL, SDATA to DVSS4 . . . . . –0.3 to DVDD4 + 0.3 V
VRT, VRB to AVSS . . . . . . . . . . . . . –0.3 to AVDD + 0.3 V
BYP1–3, CCDIN to AVSS . . . . . . . . –0.3 to AVDD + 0.3 V
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead Temperature (10 sec) . . . . . . . . . . . . . . . . . . . . . . 300°C

ORDERING GUIDE

Temperature Package Package
Model Range Description Option
AD9847AKST –20°C to +85°CThin Plastic Quad Flatpack (LQFP) ST-48
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9847 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
THERMAL CHARACTERISTICS Thermal Resistance
48-Lead LQFP Package . . . . . . . . . . . . . . . . . . . ␪
= 92°C/W
JA
REV. A
–5–
AD9847

PIN CONFIGURATION

NCNCDVDD4
DVSS4HDVD
PBLK
HBLK
CLPDM
CLPOB
SCK
AVSS1
DVDD2
CLI
SDI
36
35
34
33
32
31
30
29
28
27
26
25
AVDD1
SL
REFT
REFB
CMLEVEL
AVSS3
AVDD3
BYP3 CCDIN
BYP2
BYP1 AVDD2
AVSS2
48 47 46 4 5 44 39 38 3743 42 41 40
D1
D2 D3
D4 DVSS3
DVDD3
D5
D6
D7
D8
1
PIN 1
2
IDENTIFIER
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
H1
H2
DVSS1
AD9847
TOP VIEW
(Not to Scale)
H3
H4
DVSS2
DVDD1
RG
(LSB) D0
(MSB) D9
NC = NO CONNECT

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Type* Description
1–5 D0–D4 DO Data Outputs 6 DVSS3 P Digital Ground 3—Data Outputs 7 DVDD3 P Digital Supply 3—Data Outputs
S
8–12 D5–D9 DO Data Outputs (D9 I
MSB) 13, 14 H1, H2 DO Horizontal Clocks (to CCD) 15 DVSS1 P Digital Ground 1—H Drivers 16 DVDD1 P Digital Supply 1—H Drivers 17, 18 H3, H4 DO Horizontal Clocks (to CCD) 19 DVSS2 P Digital Ground 1—RG Driver 20 RG DO Reset Gate Clock (to CCD) 21 DVDD2 P Digital Supply 2—RG Driver 22 AVSS1 P Analog Ground 1 23 CLI DI Master Clock Input 24 AVDD1 P Analog Supply 1 25 AVSS2 P Analog Ground 2 26 AVDD2 P Analog Supply 2 27 BYP1 AO Bypass Pin (0.1 µF to AVSS) 28 BYP2 AO Bypass Pin (0.1 µF to AVSS) 29 CCDIN AI Analog Input for CCD Signal 30 BYP3 AO Bypass Pin (0.1 µF to AVSS) 31 AVDD3 P Analog Supply 3 32 AVSS3 P Analog Ground 3 33 CMLEVEL AO Internal Bias Level Decoupling (0.1 µF to AVSS) 34 REFB AO Reference Bottom Decoupling (1.0 µF to AVSS) 35 REFT AO Reference Top Decoupling (1.0 µF to AVSS) 36 SL DI 3-Wire Serial Load (from µP) 37 SDI DI 3-Wire Serial Data Input (from µP) 38 SCK DI 3-Wire Serial Clock (from µP) 39 CLPOB DI Optical Black Clamp Pulse 40 CLPDM DI Dummy Black Clamp Pulse 41 HBLK DI HCLK Blanking Pulse 42 PBLK DI Preblanking Pulse 43 VD DI Vertical Sync Pulse 44 HD DI Horizontal Sync Pulse 45 DVSS4 P Digital Ground 4—VD, HD, CLPOB, CLPDM, HBLK, PBLK, SCK, SL, SDATA 46 DVDD4 P Digital Supply 4—VD, HD, CLPOB, CLPDM, HBLK, PBLK, CK, SL 47, 48 NC NC Internally Not Connected
*Type: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power
–6–
REV. A

Equivalent Input/Output Circuits

AD9847
DATA
AVDD2
R
AVSS2
Circuit 1. CCDIN (Pin 29)
AVDD1
330
CLI
25k
1.4V
AVSS1
Circuit 2. CLI (Pin 23)
DVDD4 DVDD3
AVSS2
DVDD4
330
DVSS4
Circuit 4. Digital Inputs (Pins 36–44)
DVDD1
DATA
ENABLE
DVSS1
Circuit 5. H1–H4 and RG (Pins 13, 14, 17, 18, 20)
OUTPUT
THREE-
STATE
DVSS4 DVSS3
DOUT
Circuit 3. Data Outputs D0–D9 (Pins 1–5, 8–12)

Typical Performance Characteristics

0.50
0.25
0
–0.25
–0.50
0
200 600 800
400
TPC 1. Typical DNL
1000
4
3
2
OUTPUT NOISE – LSB
1
0
0
200
400
VGA GAIN CODE – LSB
600 800
TPC 2. Output Noise vs. VGA Gain Setting
1000
REV. A
–7–
AD9847

SYSTEM OVERVIEW

Figures 1a and 1b show the typical system application diagrams for the AD9847. The CCD output is processed by the AD9847’s AFE circuitry, which consists of a CDS, PxGA, VGA, black level clamp, and A/D converter. The digitized pixel information is sent to the digital image processor chip, where all post-processing and compression occurs. To operate the CCD, CCD timing param­eters are programmed into the AD9847 from the image processor through the 3-wire serial interface. From the system master clock, CLI, provided by the image processor, the AD9847 generates the high speed CCD clocks and all internal AFE clocks. All AD9847 clocks are synchronized with VD and HD.
V-DRIVER
V1–V4, VSG1–VSG8, SUBCK
H1–H4, RG
DOUT
CCD
CCDIN
INTEGRATED
SERIAL
INTERFACE
AD9847
AFE + TD
HD, VD
CLI
DIGITAL IMAGE
PROCESSING
ASIC
V-DRIVER
V1–V4, VSG1–VSG8, SUBCK
H1–H4, RG
DOUT
CLPOB
CCD
CCDIN
INTEGRATED
SERIAL
INTERFACE
AD9847
AFE + TD
CLPDM
PBLK
HBLK
HD, VD
CLI
DIGITAL IMAGE
PROCESSING
ASIC
Figure 1b. Typical Application (External Mode)
Figure 2 shows the horizontal and vertical counter dimensions for the AD9847. All internal horizontal clocking is programmed using these dimensions to specify line and pixel locations.
MAXIMUM FIELD DIMENSIONS
12-BIT HORIZONTAL = 4096 PIXELS MAX
Figure 1a. Typical Application (Internal Mode)
Figure 1a shows the AD9847 used in internal mode, in which all the horizontal pulses (CLPOB, CLPDM, PBLK, and HBLK) are programmed and generated internally. Figure 1b shows the AD9847 operating in external mode, in which the horizontal pulses are supplied externally by the image processor.
The H-drivers for H1–H4 and RG are included in the AD9847, allowing these clocks to be directly connected to the CCD. The AD9847 supports H-drive voltage of 5 V.
12-BIT VERTICAL = 4096 LINES MAX
Figure 2. Vertical and Horizontal Counters
–8–
REV. A

SERIAL INTERFACE TIMING

AD9847
SDATA
SCK
SDATA
SCK
A0 A1 A2 A4 A5 A6 A7
t
DS
t
LS
SL
VD
HD
NOTES
1. SDATA BITS ARE LATCHED ON SCK RISING EDGES.
2. 14 SCK EDGES ARE NEEDED TO WRITE ADDRESS AND DATA BITS.
3. FOR 16-BIT SYSTEMS, TWO EXTRA DUMMY BITS MAY BE WRITTEN. DUMMY BITS ARE IGNORED.
4. NEW DATA IS UPDATED EITHER AT THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE.
5. VD/HD UPDATE POSITION MAY BE DELAYED TO ANY HD FALLING EDGE IN THE FIELD USING THE UPDATE REGISTER.
A3
t
DH
D1 D2 D3 D4 D5 XX XX
D0
t
LH
SL UPDATED
Figure 3a. Serial Write Operation
DATA FOR STARTING
REGISTER ADDRESS
A0 A1 A2 A4 A5 A6 A7 D0 D1 D2 D3 D4 D5
A3
DATA FOR NEXT
REGISTER ADDRESS
D0 D1 D2 D3 D4 D5
VD/HD UPDATED
D0
...
D2D1
...
SL
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 6-BIT DATA-WORDS.
3. THE ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 6-BIT DATA-WORD (ALL SIX BITS MUST BE WRITTEN).
4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
5. NEW DATA IS UPDATED EITHER AT THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE.
Figure 3b. Continuous Serial Write Operation
COMPLETE REGISTER LISTING
Table I. SL Updated Registers
Register Description Register Description
oprmode AFE Operation Modes ctlmode AFE Control Modes preventpdate Prevents Loading of VD-Updated Registers readback Enables Serial Register Readback Mode vdhdpol VD/HD Active Polarity fieldval Internal Field Pulse Value hblkretime Retimes the H1 hblk to Internal Clock tgcore_rstb Reset Bar Signal for Internal TG Core h12pol H1/H2 Polarity Control h1posloc H1 Positive Edge Location
h1drv H1 Drive Current h2drv H2 Drive Current h3drv H3 Drive Current h4drv H4 Drive Current rgpol RG Polarity rgposloc RG Positive Edge Location rgnegloc RG Negative Edge Location rgdrv RG Drive Current shpposloc SHP Sample Location shdposloc SHD Sample Location
h1negloc H1 Negative Edge Location
NOTES All addresses and default values are expressed in hexadecimal. All registers are VD/HD updated as shown in Figure 3a, except for those that are SL updated.
...
REV. A
–9–
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