Analog Devices AD9846AJST Datasheet
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
AD9846A
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2001
Complete 10-Bit 30 MSPS
CCD Signal Processor
FUNCTIONAL BLOCK DIAGRAM
DATACLKSHDSHP
BANDGAP
REFERENCE
2:1
MUX
DOUT
AUX2IN
CLPDM
CCDIN
OFFSET
DAC
PBLK
AUX1IN
VRT
VRB
INTERNAL
TIMING
INTERNAL
BIAS
2dB~36dB
AVDD
DVDD
DVSS
AVSS
DRVDD
DRVSS
10
8
CML
DIGITAL
INTERFACE
SDATASCK
SL
CLPOB
10
CDS
VGA
CLP
BUF
2:1
MUX
CLP
AD9846A
CONTROL
REGISTERS
CLP
ADC
4dB6 dB
COLOR
STEERING
HD VD
PxGA
6
FEATURES
30 MSPS Correlated Double Sampler (CDS)
4 dB 6 dB 6-Bit Pixel Gain Amplifier (
PxGA
®
)
2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)
Low Noise Clamp Circuits
Analog Preblanking Function
10-Bit 30 MSPS A/D Converter
Auxiliary Inputs with VGA and Input Clamp
3-Wire Serial Digital Interface
3 V Single Supply Operation
Low Power: 100 mW @ 2.7 V
48-Lead LQFP Package
APPLICATIONS
Digital Still Cameras
Digital Video Camcorders
Industrial Imaging
PRODUCT DESCRIPTION
The AD9846A is a complete analog signal processor for CCD
applications. It features a 30 MHz single-channel architecture
designed to sample and condition the outputs of interlaced and
progressive scan area CCD arrays. The AD9846A’s signal chain
consists of an input clamp, correlated double sampler (CDS),
Pixel Gain Amplifier (PxGA), digitally controlled variable gain
amplifier (VGA), black level clamp, and a 10-bit A/D converter. Additional input modes are provided for processing
analog video signals.
The internal registers are programmed through a 3-wire
serial digital interface. Programmable features include gain
adjustment, black level adjustment, input configuration, and
power-down modes.
The AD9846A operates from a single 3 V power supply, typically dissipates 117 mW, and is packaged in a 48-lead LQFP.
PxGA is a registered trademark of Analog Devices, Inc.
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–2–
AD9846A–SPECIFICATIONS
GENERAL SPECIFICATIONS
Parameter Min Typ Max Unit
TEMPERATURE RANGE
Operating –20 +85 °C
Storage –65 +150 °C
POWER SUPPLY VOLTAGE
Analog, Digital, Digital Driver 2.7 3.6 V
POWER CONSUMPTION
Normal Operation (Specified Under Each Mode of Operation)
Power-Down Modes
Fast Recovery Mode 85 mW
Standby 5 mW
Total Power-Down 1 mW
MAXIMUM CLOCK RATE 30 MHz
A/D CONVERTER
Resolution 10 Bits
Differential Nonlinearity (DNL) ± 0.5 ± 1.0 LSB
No Missing Codes 10 Bits Guaranteed
Full-Scale Input Voltage 2.0 V
Data Output Coding Straight Binary
VOLTAGE REFERENCE
Reference Top Voltage (VRT) 2.0 V
Reference Bottom Voltage (VRB) 1.0 V
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
Parameter Symbol Min Typ Max Unit
LOGIC INPUTS
High Level Input Voltage V
IH
2.1 V
Low Level Input Voltage V
IL
0.6 V
High Level Input Current I
IH
10 µA
Low Level Input Current I
IL
10 µA
Input Capacitance C
IN
10 pF
LOGIC OUTPUTS
High Level Output Voltage, IOH = 2 mA V
OH
2.2 V
Low Level Output Voltage, IOL = 2 mA V
OL
0.5 V
Specifications subject to change without notice.
(DRVDD = 2.7 V, CL = 20 pF unless otherwise noted.)
(T
MIN
to T
MAX
, AVDD = DVDD = 3.0 V, f
DATACLK
= 30 MHz, unless otherwise noted.)
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–3–
AD9846A
Parameter Min Typ Max Unit Note
P
OWER CONSUMPTION 117 mW See TPC 1 for Power Curves
MAXIMUM CLOCK RATE 30 MHz
CDS
Gain 0 dB
Allowable CCD Reset Transient
1
500 mV See Input Waveform in Footnote 1
Max Input Range Before Saturation
1
1.0 V p-p PxGA Gain at 4 dB
Max CCD Black Pixel Amplitude
1
200 mV
PIXEL GAIN AMPLIFIER (PxGA)
Max Input Range 1.0 V p-p
Max Output Range 1.6 V p-p
Gain Control Resolution 64 Steps
Gain Monotonicity Guaranteed
Gain Range (Two’s Complement Coding) See Figure 28 for PxGA
Gain Curve
Min Gain (PxGA Gain Code 32) –2dB
Max Gain (PxGA Gain Code 31) 10 dB
VARIABLE GAIN AMPLIFIER (VGA)
Max Input Range 1.6 V p-p
Max Output Range 2.0 V p-p
Gain Control Resolution 1024 Steps
Gain Monotonicity Guaranteed
Gain Range See Figure 29 for VGA Gain Curve
Low Gain (VGA Gain Code 91) 2 dB
Max Gain (VGA Gain Code 1023) 36 dB
BLACK LEVEL CLAMP
Clamp Level Resolution 256 Steps
Clamp Level Measured at ADC Output
Min Clamp Level 0 LSB
Max Clamp Level 63.75 LSB
SYSTEM PERFORMANCE Specifications Include Entire Signal Chain
Gain Accuracy (VGA Code 91 to 1023)
2
–0.5 +0.5 Use Equations on Page 18 to Calculate Gain
PxGA
Gain Accuracy
Min Gain (PxGA Register Code 32) –1 0 +1 dB VGA Gain Fixed at 2 dB (Code 91)
Max Gain (PxGA
Code 31) 11 12 12 dB VGA Gain Fixed at 2 dB (Code 91)
Peak Nonlinearity, 500 mV Input Signal 0.1 % 12 dB Gain Applied
Total Output Noise 0.2 LSB rms AC Grounded Input, 6 dB Gain Applied
Power Supply Rejection (PSR) 40 dB Measured with Step Change on Supply
POWER-UP RECOVERY TIME Normal Clock Signals Applied
Fast Recovery Mode 0.1 ms
Reference Standby Mode 1 ms
Total Power-Down Mode 3 ms
Power-Off Condition 15 ms
NOTES
1
Input Signal Characteristics defined as follows:
200mV MAX
OPTICAL BLACK PIXEL
500mV TYP
RESET TRANSIENT
1V MAX
INPUT SIGNAL RANGE
2
PxGA gain fixed at 4 dB (Code 63).
Specifications subject to change without notice.
CCD-MODE SPECIFICATIONS
(T
MIN
to T
MAX
, AVDD = DVDD = 3.0 V, f
DATACLK
= f
SHP
= f
SHD
= 30 MHz, unless otherwise noted.)
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–4–
AD9846A–SPECIFICATIONS
AUX1-MODE SPECIFICATIONS
Parameter Min Typ Max Unit
POWER CONSUMPTION 82 mW
MAXIMUM CLOCK RATE 30 MHz
INPUT BUFFER
Gain 0dB
Max Input Range 1.0 V p-p
VGA
Max Output Range 2.0 V p-p
Gain Control Resolution 1023 Steps
Gain (Selected Using VGA Gain Register)
Min Gain 0 dB
Max Gain 36 dB
Specifications subject to change without notice.
AUX2-MODE SPECIFICATIONS
Parameter Min Typ Max Unit
POWER CONSUMPTION 86 mW
MAXIMUM CLOCK RATE 30 MHz
INPUT BUFFER (Same as AUX1-MODE)
VGA
Max Output Range 2.0 V p-p
Gain Control Resolution 512 Steps
Gain (Selected Using VGA Gain Register)
Min Gain 0 dB
Max Gain 18 dB
ACTIVE CLAMP
Clamp Level Resolution 256 Steps
Clamp Level (Measured at ADC Output)
Min Clamp Level 0 LSB
Max Clamp Level 63.75 LSB
Specifications subject to change without notice.
(T
MIN
to T
MAX
, AVDD = DVDD = 3.0 V, f
DATACLK
= 30 MHz, unless otherwise noted.)
(T
MIN
to T
MAX
, AVDD = DVDD = 3.0 V, f
DATACLK
= 30 MHz, unless otherwise noted.)
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AD9846A
–5–
TIMING SPECIFICATIONS
Parameter Symbol Min Typ Max Unit
SAMPLE CLOCKS
DATACLK, SHP, SHD Clock Period t
CONV
32 33 ns
DATACLK Hi/Low Pulsewidth t
ADC
13 16.7 ns
SHP Pulsewidth t
SHP
5 8.3 ns
SHD Pulsewidth t
SHD
5 8.3 ns
CLPDM Pulsewidth t
CDM
4 10 Pixels
CLPOB Pulsewidth
1
t
COB
2 20 Pixels
SHP Rising Edge to SHD Falling Edge t
S1
0 8.3 ns
SHP Rising Edge to SHD Rising Edge t
S2
13 16.7 ns
Internal Clock Delay t
ID
3.0 ns
Inhibited Clock Period t
INH
10 ns
DATA OUTPUTS
Output Delay t
OD
14.5 16 ns
Output Hold Time t
H
7.0 7.6 ns
Pipeline Delay 9 Cycles
SERIAL INTERFACE
Maximum SCK Frequency f
SCLK
10 MHz
SL to SCK Setup Time t
LS
10 ns
SCK to SL Hold Time t
LH
10 ns
SDATA Valid to SCK Rising Edge Setup t
DS
10 ns
SCK Falling Edge to SDATA Valid Hold t
DH
10 ns
SCK Falling Edge to SDATA Valid Read t
DV
10 ns
NOTES
1
Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
Specifications subject to change without notice.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9846A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
(CL = 20 pF, f
SAMP
= 30 MHz, CCD-Mode Timing in Figures 5 and 6, AUX-Mode Timing in Figure 7.
Serial Timing in Figures 21–24.)
ABSOLUTE MAXIMUM RATINGS
With
Respect
Parameter To Min Max Unit
AVDD1, AVDD2 AVSS –0.3 +3.9 V
DVDD1, DVDD2 DVSS –0.3 +3.9 V
DRVDD DRVSS –0.3 +3.9 V
Digital Outputs DRVSS –0.3 DRVDD + 0.3 V
SHP, SHD, DATACLK DVSS –0.3 DVDD + 0.3 V
CLPOB, CLPDM, PBLK DVSS –0.3 DVDD + 0.3 V
SCK, SL, SDATA DVSS –0.3 DVDD + 0.3 V
VRT, VRB, CMLEVEL AVSS –0.3 AVDD + 0.3 V
BYP1-4, CCDIN AVSS –0.3 AVDD + 0.3 V
Junction Temperature 150 °C
Lead Temperature 300 °C
(10 sec)
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
AD9846AJST –20°C to +85°C Thin Plastic ST-48
Quad Flatpack
(LQFP)
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LQFP Package
θ
JA
= 92°C
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AD9846A
–6–
PIN FUNCTION DESCRIPTIONS
Pin Number Name Type Description
1, 2 NC Internally not Connected
3–12 D0–D9 DO Digital Data Outputs
13 DRVDD P Digital Output Driver Supply
14 DRVSS P Digital Output Driver Ground
15, 41 DVSS P Digital Ground
16 DATACLK DI Digital Data Output Latch Clock
17 DVDD1 P Digital Supply
18 HD DI Horizontal Drive. Used with VD for Color Steering Control
19 PBLK DI Preblanking Clock Input
20 CLPOB DI Black Level Clamp Clock Input
21 SHP DI CDS Sampling Clock for CCD’s Reference Level
22 SHD DI CDS Sampling Clock for CCD’s Data Level
23 CLPDM DI Input Clamp Clock Input
24 VD DI Vertical Drive. Used with HD for Color Steering Control
25, 26, 35 AVSS P Analog Ground
27 AVDD1 P Analog Supply
28 BYP1 AO Internal Bias Level Decoupling
29 BYP2 AO Internal Bias Level Decoupling
30 CCDIN AI Analog Input for CCD Signal
31 NC NC Internally Not Connected
32 BYP4 AO Internal Bias Level Decoupling
33 AVDD2 P Analog Supply
34 AUX2IN AI Analog Input
36 AUX1IN AI Analog Input
37 CML AO Internal Bias Level Decoupling
38 VRT AO A/D Converter Top Reference Voltage Decoupling
39 VRB AO A/D Converter Bottom Reference Voltage Decoupling
40 DVDD2 P Digital Supply
42 THREE-STATE DI Digital Output Disable. Active High
43 NC NC May be tied high or low. Do not leave floating.
44 STBY DI Standby Mode, Active High. Same as Serial Interface
45 NC NC Internally Not Connected. May be Tied High or Low
46 SL DI Serial Digital Interface Load Pulse
47 SDATA DI Serial Digital Interface Data
48 SCK DI Serial Digital Interface Clock
TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
PIN CONFIGURATIONS
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 39 38 3743 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AUX1IN
AVSS
AUX2IN
AVDD2
BYP4
NC
CCDIN
(LSB) D0
D1
D2
D3
D4
D5
D6
NC = NO CONNECT
D7
D8
BYP2
BYP1
AVDD1
AVSS
AD9846A
(MSB) D9
AVSS
SCK
SDATASLNC
STBYNCTHREE-STATE
DVSS
DVDD2
VRB
VRT
CML
DRVDD
DRVSS
DVSS
ATACLK
DVDD1
HD
PBLK
CLPOB
SHP
SHD
CLPDM
VD
NC
NC
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AD9846A
–7–
DEFINITIONS OF SPECIFICATIONS
DIFFERENTIAL NONLINEARITY (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every code
must have a finite width. No missing codes guaranteed to 10-bit
resolution indicates that all 1024 codes, respectively, must be
present over all operating conditions.
PEAK NONLINEARITY
Peak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD9846A from a true straight
line. The point used as “zero scale” occurs 1/2 LSB before the
first code transition. “Positive full scale” is defined as a Level 1,
1/2 LSB beyond the last code transition. The deviation is measured
from the middle of each particular output code to the true straight
line. The error is then expressed as a percentage of the 2 V ADC
full-scale signal. The input signal is always appropriately gained up
to fill the ADC’s full-scale range.
TOTAL OUTPUT NOISE
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB, and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage, using the relationship 1 LSB
= (ADC Full Scale/2
N
codes) when N is the bit resolution of the
ADC. For the AD9846A, 1 LSB is 2 mV.
POWER SUPPLY REJECTION (PSR)
The PSR is measured with a step change applied to the supply
pins. This represents a very high frequency disturbance on the
AD9846A’s power supply. The PSR specification is calculated
from the change in the data outputs for a given step change in
the supply voltage.
INTERNAL DELAY FOR SHP/SHD
The internal delay (also called aperture delay) is the time delay
that occurs from when a sampling edge is applied to the AD9846A
until the actual sample of the input signal is held. Both SHP and
SHD sample the input signal during the transition from low to
high, so the internal delay is measured from each clock’s rising
edge to the instant the actual internal sample is taken.
EQUIVALENT INPUT CIRCUITS
330
DVDD
DVSS
Figure 1. Digital Inputs—SHP, SHD, DATACLK, CLPOB,
CLPDM, HD, VD, PBLK, SCK, SL
DVDD
DVSS
DRVSS
DRVDD
THREE-
STATE
DATA
DOUT
Figure 2. Data Outputs—D0–D9
AVDD1
AVSS
AVSS
Figure 3. CCDIN (Pin 30)
330
DVDD
DVSS
DVDD
DVSS
DVSS
DATA IN
RNW
DATA OUT
Figure 4. SDATA (Pin 47)
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AD9846A
–8–
–Typical Performance Characteristics
SAMPLE RATE – MHz
140
110
80
10 30
20
POWER DISSIPATION – mW
90
100
120
130
VDD = 3.3V
VDD = 3.0V
VDD = 2.7V
TPC 1. Power vs. Sample Rate
0
1000
400
200 600 800
0
–0.50
0.50
0.25
–0.25
TPC 2. Typical DNL Performance
VGA GAIN CODE – LSB
4
2
0
0 1000400
OUTPUT NOISE – LSB
200
1
600
3
800
TPC 3. Output Noise vs. VGA Gain
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