FEATURES
20 MSPS Correlated Double Sampler (CDS)
4 dB ⴞ 6 dB Variable CDS Gain with 6-Bit Resolution
2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)
Low Noise Clamp Circuits
Analog Preblanking Function
12-Bit 20 MSPS A/D Converter
Auxiliary Inputs with VGA and Input Clamp
3-Wire Serial Digital Interface
3 V Single Supply Operation
Low Power: 65 mW @ 2.7 V Supply
48-Lead LQFP Package
APPLICATIONS
Digital Still Cameras
Digital Video Camcorders
PC Cameras
FUNCTIONAL BLOCK DIAGRAM
CCD Signal Processor
AD9844A
PRODUCT DESCRIPTION
The AD9844A is a complete analog signal processor for CCD
applications. It features a 20 MHz single-channel architecture
designed to sample and condition the outputs of interlaced and
progressive scan area CCD arrays. The AD9844A’s signal chain
consists of an input clamp, correlated double sampler (CDS),
digitally controlled variable gain amplifier (VGA), black level
clamp, and 12-bit A/D converter. Additional input modes are
provided for processing analog video signals.
The internal registers are programmed through a 3-wire serial
digital interface. Programmable features include gain adjustment,
black level adjustment, input configuration, and power-down
modes.
The AD9844A operates from a single 3 V power supply, typically dissipates 78 mW, and is packaged in a 48-lead LQFP.
CCDIN
CLPDM
AUX1IN
AUX2IN
PBLK
CLP
AVDD
4dBⴞ6dB
CDS
CLP
2:1
MUX
AD9844A
BUF
AVSS
2:1
MUX
SL
2dB~36dB
VGA
6
INTERNAL
REGISTERS
DIGITAL
INTERFACE
CLPOB
CLP
12-BIT
ADC
BANDGAP
OFFSET
10
DAC
8
SDATASCK
REFERENCE
INTERNAL
BIAS
INTERNAL
TIMING
DATACLKSHDSHP
DRVDD
DRVSS
12
DOUT
VRT
VRB
CML
DVDD
DVSS
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
High Level Input VoltageV
Low Level Input VoltageV
High Level Input CurrentI
Low Level Input CurrentI
Input CapacitanceC
IH
IL
IH
IL
IN
2.1V
0.6V
10µA
10µA
10pF
LOGIC OUTPUTS
High Level Output Voltage, I
Low Level Output Voltage, I
Specifications subject to change without notice.
= 2 mAV
OH
= 2 mAV
OL
OH
OL
2.2V
0.5V
–2–
REV. 0
AD9844A
(T
to T
CCD-MODE SPECIFICATIONS
MIN
, AVDD = DVDD = 3.0 V, f
MAX
ParameterMinTypMaxUnitNotes
P
OWER CONSUMPTION78mWSee TPC 1 for Power Curves
MAXIMUM CLOCK RATE20MHz
CDS
Allowable CCD Reset Transient
Max CCD Black Pixel Amplitude
Max Input Range Before Saturation
1
1
1
1.0V p-pWith 4 dB CDS Gain
500mVSee Input Waveform in Note 1
200mV
Max Input Range Before Saturation1.5V p-pWith –2 dB CDS Gain
Max Input Range Before Saturation0.5V p-pWith 10 dB CDS Gain
Max Output Range1.6V p-pAt Any CDS Gain Setting
Gain Resolution64Steps
Gain Range (Two’s Complement Coding)See Figure 12 for CDS Gain Curve
Min Gain (CDS Gain Register Code 32)–2dB
Medium Gain (CDS Gain Code 63)4dB4 dB Is Default with CDS Gain Disabled
Max Gain (CDS Gain Code 31)10dB
VARIABLE GAIN AMPLIFIER (VGA)
Max Input Range1.6V p-p
Max Output Range2.0V p-p
Gain Control Resolution1024Steps
Gain Monotonicity Guaranteed
Gain RangeSee Figure 13 for VGA
Low Gain (VGA Register Code 91)2dBSee Figure 13 for Gain Equations
Max Gain (VGA Code 1023)36dB
BLACK LEVEL CLAMP
Clamp Level Resolution256Steps
Clamp LevelMeasured at ADC Output
Min Clamp Level0LSB
Max Clamp Level255LSB
SYSTEM PERFORMANCESpecifications Include Entire Signal Chain
Gain Accuracy, VGA Code 91 to 1023–0.5+0.5dBUse Equations on Page 13 to Calculate Gain
Peak Nonlinearity, 500 mV Input Signal0.1%12 dB Gain Applied (4 dB CDS Gain)
Peak Nonlinearity, 800 mV Input Signal0.4%8 dB Gain Applied (4 dB CDS Gain)
Total Output Noise0.6LSB rmsAC Grounded Input, 6 dB Gain Applied
Power Supply Rejection (PSR)40dBMeasured with Step Change on Supply
POWER-UP RECOVERY TIMEClocks Must Be Applied, as in Figures 5 and 6
From Fast Recovery Mode0.1ms
From Reference Standby Mode1ms
From Total Shutdown Mode3ms
From Power-Off Condition15ms
NOTES
1
Input Signal Characteristics defined as follows, with 4 dB CDS gain:
DATACLK
= f
SHP
= f
= 20 MHz, unless otherwise noted.)
SHD
Gain Curve
500mV TYP
RESET
TRANSIENT
Specifications subject to change without notice.
200mV MAX
OPTICAL
BLACK PIXEL
1V MAX
INPUT
SIGNAL RANGE
REV. 0
–3–
AD9844A–SPECIFICATIONS
(T
to T
AUX1-MODE SPECIFICATIONS
ParameterMinTypMaxUnit
POWER CONSUMPTION60mW
MAXIMUM CLOCK RATE20MHz
INPUT BUFFER
Gain0dB
Max Input Range1.0V p-p
VGA
Max Output Range2.0V p-p
Gain Control Resolution1023Steps
Gain (Selected Using VGA Gain Register)
Min Gain0dB
Max Gain36dB
Specifications subject to change without notice.
AUX2-MODE SPECIFICATIONS
ParameterMinTypMaxUnit
POWER CONSUMPTION60mW
MAXIMUM CLOCK RATE20MHz
INPUT BUFFER (Same as AUX1-MODE)
VGA
Max Output Range2.0V p-p
Gain Control Resolution512Steps
Gain (Selected Using VGA Gain Register)
Min Gain0dB
Max Gain18dB
ACTIVE CLAMP
Clamp Level Resolution256Steps
Clamp Level (Measured at ADC Output)
Min Clamp Level0LSB
Max Clamp Level255LSB
Specification subject to change without notice.
MIN
(T
MIN
, AVDD = DVDD = 3.0 V, f
MAX
to T
, AVDD = DVDD = 3.0 V, f
MAX
= 20 MHz, unless otherwise noted.)
DATACLK
= 20 MHz, unless otherwise noted.)
DATACLK
–4–
REV. 0
AD9844A
WARNING!
ESD SENSITIVE DEVICE
TIMING SPECIFICATIONS
(CL = 20 pF, f
Serial Timing in Figures 8–10.)
= 20 MHz, CCD-Mode Timing in Figures 5 and 6, AUX-Mode Timing in Figure 7.
SHP Rising Edge to SHD Falling Edget
SHP Rising Edge to SHD Rising Edget
Internal Clock Delayt
Inhibited Clock Periodt
CONV
ADC
SHP
SHD
CDM
t
COB
S1
S2
ID
INH
4850ns
2025ns
712.5ns
712.5ns
410Pixels
220Pixels
012.5ns
2025ns
3.0ns
10ns
DATA OUTPUTS
Output Delayt
Output Hold Timet
OD
H
7.07.6ns
14.516ns
Pipeline Delay9Cycles
SERIAL INTERFACE
Maximum SCK Frequencyf
SL to SCK Setup Timet
SCK to SL Hold Timet
SDATA Valid to SCK Rising Edge Setupt
SCK Falling Edge to SDATA Valid Holdt
SCK Falling Edge to SDATA Valid Readt
NOTES
1
Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
BYP1-4, CCDINAVSS–0.3 AVDD + 0.3V
Junction Temperature150°C
Lead Temperature300°C
(10 sec)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9844A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
Quad Flatpack
(LQFP)
REV. 0
–5–
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