Analog Devices AD9843AJST Datasheet

REV. 0

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reliable. However, no responsibility is assumed by Analog Devices for its
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otherwise under any patent or patent rights of Analog Devices.

a

AD9843A

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

Complete 10-Bit 20 MSPS

CCD Signal Processor

FUNCTIONAL BLOCK DIAGRAM

DATACLKSHDSHP

BANDGAP

REFERENCE

2:1

MUX

DOUT

AUX2IN

CLPDM

CCDIN

OFFSET

DAC

PBLK

AUX1IN

VRT

VRB

INTERNAL

TIMING

INTERNAL

BIAS

2dB~36dB

AVDD

DVDD

DVSS

AVSS

DRVDD

DRVSS

10

8

CML

DIGITAL

INTERFACE

SDATASCK

SL

CLPOB

10

CDS

VGA

CLP

BUF

2:1

MUX

CLP

AD9843A

4dB6dB

INTERNAL

REGISTERS

CLP

10-BIT

ADC

6

FEATURES
20 MSPS Correlated Double Sampler (CDS)
4 dB  6 dB Variable CDS Gain with 6-Bit Resolution
2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)
Low Noise Clamp Circuits
Analog Preblanking Function
10-Bit 20 MSPS A/D Converter
Auxiliary Inputs with VGA and Input Clamp
3-Wire Serial Digital Interface
3 V Single Supply Operation
Low Power: 65 mW @ 2.7 V Supply
48-Lead LQFP Package

APPLICATIONS
Digital Still Cameras
Digital Video Camcorders
PC Cameras

PRODUCT DESCRIPTION

The AD9843A is a complete analog signal processor for CCD
applications. It features a 20 MHz single-channel architecture
designed to sample and condition the outputs of interlaced and
progressive scan area CCD arrays. The AD9843A’s signal chain
consists of an input clamp, correlated double sampler (CDS),
digitally controlled variable gain amplifier (VGA), black level
clamp, and 10-bit A/D converter. Additional input modes are
provided for processing analog video signals.

The internal registers are programmed through a 3-wire serial
digital interface. Programmable features include gain adjust­ment, black level adjustment, input configuration, and power­down modes.

The AD9843A operates from a single 3 V power supply, typi­cally dissipates 78 mW, and is packaged in a 48-lead LQFP.

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AD9843A–SPECIFICATIONS

GENERAL SPECIFICATIONS

Parameter Min Typ Max Unit

TEMPERATURE RANGE

Operating –20 +85 °C
Storage –65 +150 °C

POWER SUPPLY VOLTAGE

Analog, Digital, Digital Driver 2.7 3.6 V

POWER CONSUMPTION

Normal Operation (Specified Under Each Mode of Operation)
Power-Down Modes

Fast Recovery Mode 45 mW
Standby 5 mW
Total Power-Down 1 mW

MAXIMUM CLOCK RATE 20 MHz

A/D CONVERTER

Resolution 10 Bits
Differential Nonlinearity (DNL) ± 0.4 ± 1.0 LSB
No Missing Codes 10 Bits Guaranteed
Full-Scale Input Voltage 2.0 V
Data Output Coding Straight Binary

VOLTAGE REFERENCE

Reference Top Voltage (VRT) 2.0 V
Reference Bottom Voltage (VRB) 1.0 V

Specifications subject to change without notice.

DIGITAL SPECIFICATIONS

Parameter Symbol Min Typ Max Unit

LOGIC INPUTS

High Level Input Voltage V

IH

2.1 V

Low Level Input Voltage V

IL

0.6 V

High Level Input Current I

IH

10 µA

Low Level Input Current I

IL

10 µA

Input Capacitance C

IN

10 pF

LOGIC OUTPUTS

High Level Output Voltage, IOH = 2 mA V

OH

2.2 V

Low Level Output Voltage, IOL = 2 mA V

OL

0.5 V

Specifications subject to change without notice.

(T

MIN

to T

MAX

, AVDD = DVDD = 3.0 V, f

DATACLK

= 20 MHz, unless otherwise noted.)

(DRVDD = 2.7 V, CL = 20 pF unless otherwise noted.)

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AD9843A

Parameter Min Typ Max Unit Notes

P

OWER CONSUMPTION 78 mW See TPC 1 for Power Curves

MAXIMUM CLOCK RATE 20 MHz

CDS

Allowable CCD Reset Transient

1

500 mV See Input Waveform in Note 1

Max CCD Black Pixel Amplitude

1

200 mV

Max Input Range Before Saturation

1

1.0 V p-p With 4 dB CDS Gain
Max Input Range Before Saturation 1.5 V p-p With –2 dB CDS Gain
Max Input Range Before Saturation 0.5 V p-p With 10 dB CDS Gain
Max Output Range 1.6 V p-p At Any CDS Gain Setting
Gain Resolution 64 Steps
Gain Range (Two’s Complement Coding) See Figure 12 for CDS Gain Curve

Min Gain (CDS Gain Register Code 32) –2 dB
Medium Gain (CDS Gain Code 63) 4 dB 4 dB Is Default with CDS Gain Disabled
Max Gain (CDS Gain Code 31) 10 dB

VARIABLE GAIN AMPLIFIER (VGA)

Max Input Range 1.6 V p-p
Max Output Range 2.0 V p-p
Gain Control Resolution 1024 Steps
Gain Monotonicity Guaranteed
Gain Range See Figure 13 for VGA

Gain Curve
Low Gain (VGA Register Code 91) 2 dB See Page 13 for Gain Equations
Max Gain (VGA Code 1023) 36 dB

BLACK LEVEL CLAMP

Clamp Level Resolution 256 Steps
Clamp Level Measured at ADC Output

Min Clamp Level 0 LSB
Max Clamp Level 63.75 LSB

SYSTEM PERFORMANCE Specifications Include Entire Signal Chain

Gain Accuracy, VGA Code 91 to 1023 –0.5 +0.5 dB Use Equations on Page 13 to Calculate Gain
Peak Nonlinearity, 500 mV Input Signal 0.1 % 12 dB Gain Applied (4 dB CDS Gain)
Peak Nonlinearity, 800 mV Input Signal 0.4 % 8 dB Gain Applied (4 dB CDS Gain)
Total Output Noise 0.2 LSB rms AC Grounded Input, 6 dB Gain Applied
Power Supply Rejection (PSR) 40 dB Measured with Step Change on Supply

POWER-UP RECOVERY TIME Clocks Must Be Applied, as in Figures 5 and 6

From Fast Recovery Mode 0.1 ms
From Reference Standby Mode 1 ms
From Total Shutdown Mode 3 ms
From Power-Off Condition 15 ms

NOTES

1

Input Signal Characteristics defined as follows, with 4 dB CDS gain:

1V MAX

INPUT

SIGNAL RANGE

200mV MAX

OPTICAL

BLACK PIXEL

500mV TYP

RESET

TRANSIENT

Specifications subject to change without notice.

CCD-MODE SPECIFICATIONS

(T

MIN

to T

MAX

, AVDD = DVDD = 3.0 V, f

DATACLK

= f

SHP

= f

SHD

= 20 MHz, unless otherwise noted.)

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AD9843A–SPECIFICATIONS

AUX1-MODE SPECIFICATIONS

Parameter Min Typ Max Unit

POWER CONSUMPTION 60 mW

MAXIMUM CLOCK RATE 20 MHz

INPUT BUFFER

Gain 0dB
Max Input Range 1.0 V p-p

VGA

Max Output Range 2.0 V p-p
Gain Control Resolution 1023 Steps
Gain (Selected Using VGA Gain Register)

Min Gain 0 dB
Max Gain 36 dB

Specifications subject to change without notice.

AUX2-MODE SPECIFICATIONS

Parameter Min Typ Max Unit

POWER CONSUMPTION 60 mW

MAXIMUM CLOCK RATE 20 MHz

INPUT BUFFER (Same as AUX1-MODE)

VGA

Max Output Range 2.0 V p-p
Gain Control Resolution 512 Steps
Gain (Selected Using VGA Gain Register)

Min Gain 0 dB
Max Gain 18 dB

ACTIVE CLAMP

Clamp Level Resolution 256 Steps
Clamp Level (Measured at ADC Output)

Min Clamp Level 0 LSB
Max Clamp Level 63.75 LSB

Specification subject to change without notice.

(T

MIN

to T

MAX

, AVDD = DVDD = 3.0 V, f

DATACLK

= 20 MHz, unless otherwise noted.)

(T

MIN

to T

MAX

, AVDD = DVDD = 3.0 V, f

DATACLK

= 20 MHz, unless otherwise noted.)

AD9843A

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TIMING SPECIFICATIONS

Parameter Symbol Min Typ Max Unit

SAMPLE CLOCKS

DATACLK, SHP, SHD Clock Period t

CONV

48 50 ns

DATACLK High/Low Pulsewidth t

ADC

20 25 ns

SHP Pulsewidth t

SHP

712.5 ns

SHD Pulsewidth t

SHD

712.5 ns

CLPDM Pulsewidth t

CDM

4 10 Pixels

CLPOB Pulsewidth

1

t

COB

2 20 Pixels

SHP Rising Edge to SHD Falling Edge t

S1

012.5 ns

SHP Rising Edge to SHD Rising Edge t

S2

20 25 ns

Internal Clock Delay t

ID

3.0 ns

Inhibited Clock Period t

INH

10 ns

DATA OUTPUTS

Output Delay t

OD

14.5 16 ns

Output Hold Time t

H

7.0 7.6 ns

Pipeline Delay 9 Cycles

SERIAL INTERFACE

Maximum SCK Frequency f

SCLK

10 MHz

SL to SCK Setup Time t

LS

10 ns

SCK to SL Hold Time t

LH

10 ns

SDATA Valid to SCK Rising Edge Setup t

DS

10 ns

SCK Falling Edge to SDATA Valid Hold t

DH

10 ns

SCK Falling Edge to SDATA Valid Read t

DV

10 ns

NOTES

1

Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.

Specifications subject to change without notice.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9843A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

(CL = 20 pF, f

SAMP

= 20 MHz, CCD-Mode Timing in Figures 5 and 6, AUX-Mode Timing in Figure 7.

Serial Timing in Figures 8–10.)

ABSOLUTE MAXIMUM RATINGS

With
Respect

Parameter To Min Max Unit

AVDD1, AVDD2 AVSS –0.3 +3.9 V
DVDD1, DVDD2 DVSS –0.3 +3.9 V
DRVDD DRVSS –0.3 +3.9 V
Digital Outputs DRVSS –0.3 DRVDD + 0.3 V
SHP, SHD, DATACLK DVSS –0.3 DVDD + 0.3 V
CLPOB, CLPDM, PBLK DVSS –0.3 DVDD + 0.3 V
SCK, SL, SDATA DVSS –0.3 DVDD + 0.3 V
VRT, VRB, CMLEVEL AVSS –0.3 AVDD + 0.3 V
BYP1-4, CCDIN AVSS –0.3 AVDD + 0.3 V
Junction Temperature 150 °C
Lead Temperature 300 °C

(10 sec)

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

AD9843AJST –20°C to +85°C Thin Plastic ST-48

Quad Flatpack
(LQFP)

THERMAL CHARACTERISTICS

Thermal Resistance

48-Lead LQFP Package

θ

JA

= 92°C

WARNING!

ESD SENSITIVE DEVICE