ANALOG DEVICES AD9841A, AD9842A Service Manual

a

Complete 20 MSPS

CCD Signal Processors

AD9841A/AD9842A

FEATURES
20 MSPS Correlated Double Sampler (CDS)
4 dB  6 dB 6-Bit Pixel Gain Amplifier (

PxGA

®

)
2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)
Low Noise Clamp Circuits
Analog Preblanking Function
10-Bit (9841) or 12-Bit (9842) 20 MSPS A/D Converter
Auxiliary Inputs with VGA and Input Clamp
3-Wire Serial Digital Interface
3 V Single Supply Operation
Low Power: 65 mW @ 2.7 V Supply
48-Lead LQFP Package

APPLICATIONS
Digital Still Cameras
Digital Video Camcorders

FUNCTIONAL BLOCK DIAGRAM

CCDIN

CLPDM

AUX1IN

AUX2IN

PBLK

CLP

AVDD

4dB  6dB

CDS

CLP

2:1

MUX

AD9841A/AD9842A

AVSS

PxGA

6

BUF

HD VD

COLOR

STEERING

2:1

MUX

CONTROL

REGISTERS

DIGITAL

INTERFACE

PRODUCT DESCRIPTION

The AD9841A and AD9842A are complete analog signal proces­sors for CCD applications. Both products feature a 20 MHz
single-channel architecture designed to sample and condition
the outputs of interlaced and progressive scan area CCD arrays.
The AD9841A/AD9842A’s signal chain consists of an input
clamp, correlated double sampler (CDS), Pixel Gain Amplifier
(PxGA), digitally controlled variable gain amplifier (VGA),
black level clamp, and A/D converter. The AD9841A offers 10-bit
ADC resolution, while the AD9842A contains a true 12-bit
ADC. Additional input modes are provided for processing analog
video signals.

The internal registers are programmed through a 3-wire serial
digital interface. Programmable features include gain adjustment,
black level adjustment, input configuration, and power-down modes.

The AD9841A and AD9842A operate from a single 3 V power
supply, typically dissipate 78 mW, and are packaged in a 48­lead LQFP.

CLPOB

DRVDD

DRVSS

DOUT

VRT

VRB

CML

DVDD

DVSS

2dB–36dB

VGA

10

OFFSET

DAC

8

CLP

ADC

BANDGAP

REFERENCE

INTERNAL

INTERNAL

TIMING

10/12

BIAS

SL

PxGA is a registered trademark of Analog Devices, Inc.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

SDATASCK

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

DATACLKSHDSHP

AD9841A/AD9842A–SPECIFICATIONS

(T

to T

GENERAL SPECIFICATIONS

MIN

, AVDD = DVDD = 3.0 V, f

MAX

Parameter Min Typ Max Unit

TEMPERATURE RANGE

Operating –20 +85 °C
Storage –65 +150 °C

POWER SUPPLY VOLTAGE

Analog, Digital, Digital Driver 2.7 3.6 V

POWER CONSUMPTION

Normal Operation (Specified Under Each Mode of Operation)
Power-Down Modes

Fast Recovery Mode 30 mW
Standby 5 mW
Total Power-Down 1 mW

MAXIMUM CLOCK RATE 20 MHz

A/D CONVERTER (AD9841A)

Resolution 10 Bits
Differential Nonlinearity (DNL) ± 0.4 ± 1.0 LSB
No Missing Codes 10 Bits Guaranteed
Full-Scale Input Voltage 2.0 V
Data Output Coding Straight Binary

A/D CONVERTER (AD9842A)

Resolution 12 Bits
Differential Nonlinearity (DNL) ± 0.5 ± 1.0 LSB
No Missing Codes 12 Bits Guaranteed
Full-Scale Input Voltage 2.0 V
Data Output Coding Straight Binary

VOLTAGE REFERENCE

Reference Top Voltage (VRT) 2.0 V
Reference Bottom Voltage (VRB) 1.0 V

Specifications subject to change without notice.

= 20 MHz, unless otherwise noted.)

DATACLK

DIGITAL SPECIFICATIONS

(DRVDD = 2.7 V, CL = 20 pF unless otherwise noted.)

Parameter Symbol Min Typ Max Unit

LOGIC INPUTS

High Level Input Voltage V
Low Level Input Voltage V
High Level Input Current I
Low Level Input Current I
Input Capacitance C

IH

IL

IH

IL

IN

2.1 V

0.6 V
10 µA
10 µA
10 pF

LOGIC OUTPUTS

High Level Output Voltage, IOH = 2 mA V
Low Level Output Voltage, IOL = 2 mA V

Specifications subject to change without notice.

OH

OL

2.2 V

0.5 V

–2–

REV. 0

AD9841A/AD9842A

(T

to T

, AVDD = DVDD = 3.0 V, f

MAX

AD9841A CCD-MODE SPECIFICATIONS

MIN

wise noted.)

Parameter Min Typ Max Unit Notes

P

OWER CONSUMPTION 78 mW See TPC 1 for Power Curves

MAXIMUM CLOCK RATE 20 MHz

CDS

Gain 0 dB
Allowable CCD Reset Transient
Max Input Range Before Saturation
Max CCD Black Pixel Amplitude

1

1

1

1.0 V p-p PxGA Gain at 4 dB

500 mV See Input Waveform in Footnote 1

200 mV

PIXEL GAIN AMPLIFIER (PxGA)

Max Input Range 1.0 V p-p PxGA
Max Output Range 1.6 V p-p At Any PxGA
Gain Control Resolution 64 Steps
Gain Monotonicity Guaranteed
Gain Range (Two’s Complement Coding) See Figure 28 for PxGA

Min Gain (PxGA Gain Code 32) –2 dB
Max Gain (PxGA Gain Code 31) 10 dB

VARIABLE GAIN AMPLIFIER (VGA)

Max Input Range 1.6 V p-p
Max Output Range 2.0 V p-p
Gain Control Resolution 1024 Steps
Gain Monotonicity . Guaranteed
Gain Range See Figure 29 for VGA Gain Curve

Low Gain (VGA Gain Code 91) 2 dB
Max Gain (VGA Gain Code 1023) 36 dB

BLACK LEVEL CLAMP

Clamp Level Resolution 256 Steps
Clamp Level Measured at ADC Output

Min Clamp Level 0 LSB
Max Clamp Level 63.75 LSB

SYSTEM PERFORMANCE Specifications Include Entire Signal Chain

Gain Accuracy, VGA Code 91 to 1023

PxGA

Gain Accuracy
Min Gain (PxGA Register Code 32) –1 0 +1 dB VGA Gain Fixed at 2 dB (Code 91)
Max Gain (PxGA

Code 31) 11 12 13 dB VGA Gain Fixed at 2 dB (Code 91)

2

–0.5 +0.5 Use Equations on Page 19 to Calculate Gain

Peak Nonlinearity, 500 mV Input Signal 0.1 % 12 dB Gain Applied
Peak Nonlinearity, 800 mV Input Signal 0.4 % 8 dB Gain Applied
Total Output Noise 0.2 LSB rms AC Grounded Input, 6 dB Gain Applied
Power Supply Rejection (PSR) 40 dB Measured with Step Change on Supply

POWER-UP RECOVERY TIME Normal Clock Signals Applied

Fast Recovery Mode 0.1 ms
Reference Standby Mode 1 ms
Total Shutdown Mode 3 ms
Power-Off Condition 15 ms

NOTES

1

Input Signal Characteristics defined as follows:

= f

DATACLK

SHP

Gain at 4 dB

= f

Gain

= 20 MHz, unless other-

SHD

Gain Curve

500mV TYP

RESET TRANSIENT

2

PxGA gain fixed at 4 dB.

Specifications subject to change without notice.

200mV MAX

OPTICAL BLACK PIXEL

1V MAX

INPUT SIGNAL RANGE

REV. 0

–3–

AD9841A/AD9842A–SPECIFICATIONS

(T

to T

, AVDD = DVDD = 3.0 V, f

MAX

AD9842A CCD-MODE SPECIFICATIONS

MIN

otherwise noted)

Parameter Min Typ Max Unit Notes

P

OWER CONSUMPTION 78 mW See TPC 1 for Power Curves

MAXIMUM CLOCK RATE 20 MHz

CDS

Gain 0 dB
Allowable CCD Reset Transient
Max Input Range Before Saturation
Max CCD Black Pixel Amplitude

1

1

1

1.0 V p-p PxGA Gain at 4 dB

500 mV See Input Waveform in Footnote 1

200 mV

PIXEL GAIN AMPLIFIER (PxGA)

Max Input Range 1.0 V p-p
Max Output Range 1.6 V p-p
Gain Control Resolution 64 Steps
Gain Monotonicity Guaranteed

Gain Range (Two’s Complement Coding) See Figure 28 for PxGA

Min Gain (PxGA Gain Code 32) –2 dB
Max Gain (PxGA Gain Code 31) 10 dB

VARIABLE GAIN AMPLIFIER (VGA)

Max Input Range 1.6 V p-p
Max Output Range 2.0 V p-p
Gain Control Resolution 1024 Steps
Gain Monotonicity Guaranteed
Gain Range See Figure 29 for VGA Gain Curve

Low Gain (VGA Gain Code 91) 2 dB
Max Gain (VGA Gain Code 1023) 36 dB

BLACK LEVEL CLAMP

Clamp Level Resolution 256 Steps
Clamp Level Measured at ADC Output

Min Clamp Level 0 LSB
Max Clamp Level 255 LSB

SYSTEM PERFORMANCE Specifications Include Entire Signal Chain

Gain Accuracy, (VGA Code 91 to 1023)

PxGA

Gain Accuracy
Min Gain (PxGA Register Code 32) –1 0 +1 dB VGA Gain Fixed at 2 dB (Code 91)
Max Gain (PxGA

Code 31) 11 12 13 dB VGA Gain Fixed at 2 dB (Code 91)

2

–0.5 +0.5 Use Equations on Page 19 to Calculate Gain

Peak Nonlinearity, 500 mV Input Signal 0.1 % 12 dB Gain Applied
Total Output Noise 0.6 LSB rms AC Grounded Input, 6 dB Gain Applied
Power Supply Rejection (PSR) 40 dB Measured with step change on supply

POWER-UP RECOVERY TIME Normal Clock Signals Applied

Fast Recovery Mode 0.1 ms
Reference Standby Mode 1 ms
Total Shutdown Mode 3 ms
Power-Off Condition 15 ms

NOTES

1

Input Signal Characteristics defined as follows:

DATACLK

= f

SHP

= f

= 20 MHz, unless

SHD

Gain Curve

500mV TYP

RESET TRANSIENT

2

PxGA gain fixed at 4 dB.

Specifications subject to change without notice.

200mV MAX

OPTICAL BLACK PIXEL

1V MAX

INPUT SIGNAL RANGE

–4–

REV. 0

AD9841A/AD9842A

(T

to T

AUX1-MODE SPECIFICATIONS

Parameter Min Typ Max Unit

POWER CONSUMPTION 60 mW

MAXIMUM CLOCK RATE 20 MHz

INPUT BUFFER

Gain 0dB
Max Input Range 1.0 V p-p

VGA

Max Output Range 2.0 V p-p
Gain Control Resolution 1023 Steps
Gain (Selected Using VGA Gain Register)

Min Gain 0 dB
Max Gain 36 dB

Specifications subject to change without notice.

AUX2-MODE SPECIFICATIONS

Parameter Min Typ Max Unit

POWER CONSUMPTION 60 mW

MAXIMUM CLOCK RATE 20 MHz

INPUT BUFFER (Same as AUX1-MODE)

VGA

Max Output Range 2.0 V p-p
Gain Control Resolution 512 Steps
Gain (Selected Using VGA Gain Register)

Min Gain 0 dB
Max Gain 18 dB

ACTIVE CLAMP (AD9841A)

Clamp Level Resolution 256 Steps
Clamp Level (Measured at ADC Output)

Min Clamp Level 0 LSB
Max Clamp Level 63.75 LSB

ACTIVE CLAMP (AD9842A)

Clamp Level Resolution 256 Steps
Clamp Level (Measured at ADC Output)

Min Clamp Level 0 LSB
Max Clamp Level 255 LSB

Specifications subject to change without notice.

MIN

(T

MIN

, AVDD = DVDD = 3.0 V, f

MAX

to T

, AVDD = DVDD = 3.0 V, f

MAX

= 20 MHz, unless otherwise noted.)

DATACLK

= 20 MHz, unless otherwise noted.)

DATACLK

REV. 0

–5–

AD9841A/AD9842A

TIMING SPECIFICATIONS

(CL = 20 pF, f
Serial Timing in Figures 21–24.)

= 20 MHz, CCD-Mode Timing in Figures 5 and 6, AUX-Mode Timing in Figure 7.

SAMP

Parameter Symbol Min Typ Max Unit

SAMPLE CLOCKS

DATACLK, SHP, SHD Clock Period t
DATACLK Hi/Low Pulsewidth t
SHP Pulsewidth t
SHD Pulsewidth t
CLPDM Pulsewidth t
CLPOB Pulsewidth

1

SHP Rising Edge to SHD Falling Edge t
SHP Rising Edge to SHD Rising Edge t
Internal Clock Delay t
Inhibited Clock Period t

CONV

ADC

SHP

SHD

CDM

t

COB

S1

S2

ID

INH

48 50 ns
20 25 ns

712.5 ns

712.5 ns
4 10 Pixels
2 20 Pixels

012.5 ns
20 25 ns

3.0 ns

10 ns

DATA OUTPUTS

Output Delay t
Output Hold Time t

OD

H

7.0 7.6 ns

14.5 16 ns

Pipeline Delay 9 Cycles

SERIAL INTERFACE

Maximum SCK Frequency f
SL to SCK Setup Time t
SCK to SL Hold Time t
SDATA Valid to SCK Rising Edge Setup t
SCK Falling Edge to SDATA Valid Hold t
SCK Falling Edge to SDATA Valid Read t

NOTES

1

Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.

Specifications subject to change without notice.

SCLK

LS

LH

DS

DH

DV

10 MHz
10 ns
10 ns
10 ns
10 ns
10 ns

ABSOLUTE MAXIMUM RATINGS

With
Respect

Parameter To Min Max Unit

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

AD9841AJST –20°C to +85°C Thin Plastic ST-48

AVDD1, AVDD2 AVSS –0.3 +3.9 V
DVDD1, DVDD2 DVSS –0.3 +3.9 V
DRVDD DRVSS –0.3 +3.9 V

AD9842AJST –20°C to +85°C Thin Plastic ST-48

Digital Outputs DRVSS –0.3 DRVDD + 0.3 V
SHP, SHD, DATACLK DVSS –0.3 DVDD + 0.3 V
CLPOB, CLPDM, PBLK DVSS –0.3 DVDD + 0.3 V
SCK, SL, SDATA DVSS –0.3 DVDD + 0.3 V
VRT, VRB, CMLEVEL AVSS –0.3 AVDD + 0.3 V
BYP1-4, CCDIN AVSS –0.3 AVDD + 0.3 V
Junction Temperature 150 °C
Lead Temperature 300 °C

THERMAL CHARACTERISTICS

Thermal Resistance

48-Lead LQFP Package

θ

= 92°C

JA

(10 sec)

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9841A/AD9842A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

Quad Flatpack
(LQFP)

Quad Flatpack
(LQFP)

WARNING!

ESD SENSITIVE DEVICE

–6–

REV. 0

AD9841A/AD9842A

PIN CONFIGURATIONS

SCK

SDATASLNC

STBY

NC

DVSS

DVDD2

VRB

VRT

SHP

CML

36

AUX1IN

35

AVSS

34

AUX2IN

33

AVDD2

32

BYP4

31

NC

30

CCDIN

29

BYP2

28

BYP1

27

AVDD1

26

AVSS

25

AVSS

NC = NO CONNECT

SHD

VD

CLPDM

PIN FUNCTION DESCRIPTIONS

(LSB) D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

(MSB) D11

SCK

SDATASLNC

STBYNCTHREE-STATE

HD

DVDD1

PBLK

DVSS

CLPOB

48 47 46 45 44 39 38 3743 42 41 40

1

PIN 1

2

IDENTIFIER

3

4

5

6

7

8

9

10

11

12

13 14 15 16 17 18 19 20 21 22 23 24

DRVDD

DVSS

DRVSS

AD9842A

TOP VIEW

(Not to Scale)

DATACLK

DVDD2

VRB

SHP

SHD

VRT

CML

VD

CLPDM

36

35

34

33

32

31

30

29

28

27

26

25

AUX1IN

AVSS

AUX2IN

AVDD2

BYP4

NC

CCDIN

BYP2

BYP1

AVDD1

AVSS
AVSS

AD9841A

TOP VIEW

(Not to Scale)

HD

DVDD1

DATACLK

THREE-STATE

PBLK

CLPOB

NC

NC

(LSB) D0

D1

D2

D3

D4

D5

D6

D7

D8

(MSB) D9

NC = NO CONNECT

48 47 46 45 44 39 38 3743 42 41 40

1

PIN 1

2

IDENTIFIER

3

4

5

6

7

8

9

10

11

12

13 14 15 16 17 18 19 20 21 22 23 24

DVSS

DRVSS

DRVDD

Pin Number Name Type Description

1, 2 NC NC Internally Not Connected (AD9841A ONLY)
3–12 D0–D9 DO Digital Data Outputs (AD9841A ONLY)
1–12 D0–D11 DO Digital Data Outputs (AD9842A ONLY)
13 DRVDD P Digital Output Driver Supply
14 DRVSS P Digital Output Driver Ground
15, 41 DVSS P Digital Ground
16 DATACLK DI Digital Data Output Latch Clock
17 DVDD1 P Digital Supply
18 HD DI Horizontal Drive. Used with VD for Color Steering Control
19 PBLK DI Preblanking Clock Input
20 CLPOB DI Black Level Clamp Clock Input
21 SHP DI CDS Sampling Clock for CCD’s Reference Level
22 SHD DI CDS Sampling Clock for CCD’s Data Level
23 CLPDM DI Input Clamp Clock Input
24 VD DI Vertical Drive. Used with HD for Color Steering Control
25, 26, 35 AVSS P Analog Ground
27 AVDD1 P Analog Supply
28 BYP1 AO Internal Bias Level Decoupling
29 BYP2 AO Internal Bias Level Decoupling
30 CCDIN AI Analog Input for CCD Signal
31 NC NC Internally Not Connected
32 BYP4 AO Internal Bias Level Decoupling
33 AVDD2 P Analog Supply
34 AUX2IN AI Analog Input
36 AUX1IN AI Analog Input
37 CML AO Internal Bias Level Decoupling
38 VRT AO A/D Converter Top Reference Voltage Decoupling
39 VRB AO A/D Converter Bottom Reference Voltage Decoupling
40 DVDD2 P Digital Supply
42 THREE-STATE DI Digital Output Disable. Active High
43 NC NC May be tied high or low. Do not leave floating.
44 STBY DI Standby Mode, Active High. Same as Serial Interface
45 NC NC Internally Not Connected. May be Tied High or Low
46 SL DI Serial Digital Interface Load Pulse
47 SDATA DI Serial Digital Interface Data
48 SCK DI Serial Digital Interface Clock

TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.

REV. 0

–7–