ANALOG DEVICES AD9838 Service Manual
11 mW Power, 2.3 V to 5.5 V,
FEATURES
2.3 V to 5.5 V power supply
MCLK speed: 16 MHz (B grade), 5 MHz (A grade)
Output frequency up to 8 MHz
Sinusoidal and triangular outputs
On-board comparator
3-wire SPI interface
Extended temperature range: −40°C to +125°C
Power-down option
11 mW power consumption at 2.3 V
20-lead LFCSP
APPLICATIONS
Frequency stimulus/waveform generation
Frequency phase tuning and modulation
Low power RF/communications systems
Liquid and gas flow measurement
Sensory applications: proximity, motion, and defect detection
Test and medical equipment
GENERAL DESCRIPTION
The AD9838 is a low power DDS device capable of producing high
performance sine and triangular outputs. It also has an on-board
comparator that allows a square wave to be produced for clock
generation. Consuming only 11 mW of power at 2.3 V, the
AD9838 is an ideal candidate for power-sensitive applications.
FUNCTIONAL BLOCK DIAGRAM
DGND
CAP/2.5VDVDDAGNDAVDD
Complete DDS
AD9838
Capability for phase modulation and frequency modulation is
provided. The frequency registers are 28 bits wide: with a 16 MHz
clock rate, resolution of 0.06 Hz can be achieved; with a 5 MHz
clock rate, the AD9838 can be tuned to 0.02 Hz resolution.
Frequency and phase modulation are configured by loading
registers through the serial interface and by toggling the registers
using software or the FSELECT and PSELECT pins, respectively.
The AD9838 is written to via a 3-wire serial interface. This serial
interface operates at clock rates up to 40 MHz and is compatible
with DSP and microcontroller standards.
The device operates with a power supply from 2.3 V to 5.5 V. The
analog and digital sections are independent and can be run from
different power supplies; for example, AVDD can equal 5 V with
DVDD equal to 3 V.
The AD9838 has a power-down pin (SLEEP) that allows external
control of the power-down mode. Sections of the device that are
not being used can be powered down to minimize current consumption. For example, the DAC can be powered down when
a clock output is being generated.
The AD9838 is available in a 20-lead LFCSP_WQ package.
REFOUT FSADJUST
MCLK
FSELECT
28-BIT FREQ0
REG
28-BIT FREQ1
REG
SERIAL INT ERFACE
CONTROL L OGIC
FSYNC SCLK SDATA
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
MUX
12-BIT PHASE0 REG
12-BIT PHASE1 REG
AND
REGULATOR
PHASE
ACCUMULATOR
(28-BIT)
16-BIT CONTRO L
REGIS TER
Σ
MUX
VCC
2.5V
12
MUX
MUX
Figure 1.
ON-BOARD
REFERENCE
SIN
ROM
SLEEP RESETPSELECT
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.
DIVIDE
BY 2
MUX
MSB
FULL-SCALE
CONTROL
10-BIT
DAC
COMPARATOR
AD9838
COMP
IOUT
IOUTB
SIGN BIT OUT
VIN
09077-001
AD9838
TABLE OF CONTENTS
Features.............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 9
Test Circuit ...................................................................................... 12
Terminology .................................................................................... 13
Theory of Operation ...................................................................... 14
Circuit Description......................................................................... 15
Numerically Controlled Oscillator Plus Phase Modulator... 15
SIN ROM..................................................................................... 15
Digital-to-Analog Converter (DAC) ....................................... 15
Comparator................................................................................. 15
Regulator...................................................................................... 16
Functional Description.................................................................. 17
Serial Interface............................................................................ 17
Latency Period ............................................................................ 17
Control Register ......................................................................... 17
Frequency and Phase Registers ................................................ 19
Reset Function ............................................................................ 20
Sleep Function ............................................................................ 20
SIGN BIT OUT Pin.................................................................... 21
IOUT and IOUTB Pins ............................................................. 21
Powering Up the AD9838 ......................................................... 21
Applications Information.............................................................. 24
Grounding and Layout.............................................................. 24
Interfacing to Microprocessors................................................. 24
Evaluation Board............................................................................ 26
System Demonstration Platform.............................................. 26
AD9838 to SPORT Interface..................................................... 26
Evaluation Kit ............................................................................. 26
Crystal Oscillator vs. External Clock....................................... 26
Power Supply............................................................................... 26
Evaluation Board Schematics ................................................... 27
Evaluation Board Layout........................................................... 29
Outline Dimensions....................................................................... 30
Ordering Guide .......................................................................... 30
REVISION HISTORY
4/11—Rev. 0 to Rev. A
Change to Title.................................................................................. 1
Change to Figure 3 ........................................................................... 5
Change to Figure 8 ........................................................................... 9
4/11—Revision 0: Initial Version
Rev. A | Page 2 of 32
AD9838
SPECIFICATIONS
AVDD = DVDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, TA = T
otherwise noted.
Table 1.
Parameter1 Min Typ Max Unit Test Conditions/Comments
SIGNAL DAC SPECIFICATIONS
Resolution 10 Bits
Update Rate
A Grade 5 MSPS
B Grade 16 MSPS
I
Full Scale2 3.0 mA
OUT
V
Maximum 0.6 V
OUT
V
Minimum 30 mV
OUT
Output Compliance3 0.8 V
DC Accuracy
Integral Nonlinearity (INL) ±1 LSB
Differential Nonlinearity (DNL) ±0.5 LSB
DDS SPECIFICATIONS
Dynamic Specifications
Signal-to-Noise Ratio (SNR)
A Grade −63 dB f
B Grade −64 dB f
Total Harmonic Distortion (THD)
A Grade −64 dBc f
B Grade −64 dBc f
Spurious-Free Dynamic Range (SFDR)
Wideband (0 to Nyquist)
A Grade −68 dBc f
B Grade −66 dBc f
Narrow-Band (±200 kHz)
A Grade −97 dBc f
B Grade −92 dBc f
Clock Feedthrough
A Grade −68 dBc f
B Grade −65 dBc f
Wake-Up Time 1 ms
COMPARATOR
Input Voltage Range 1 V p-p AC-coupled internally
Input Capacitance 10 pF
Input High-Pass Cutoff Frequency 3 MHz
Input DC Resistance 5 MΩ
Input Leakage Current 10 μA
OUTPUT BUFFER
Output Rise/Fall Time 12 ns Using a 15 pF load
Output Jitter 120 ps rms 3 MHz sine wave 0.6 V p-p
VOLTAGE REFERENCE
Internal Reference 1.11 1.18 1.24 V
REFOUT Output Impedance4 1 kΩ
Reference TC 100 ppm/°C
FSADJUST Voltage 1.14 V
MIN
to T
MAX
, R
SET
= 6.8 kΩ, R
= 200 Ω for IOUT and IOUTB, unless
LOAD
= 5 MHz, f
MCLK
= 16 MHz, f
MCLK
= 5 MHz, f
MCLK
= 16 MHz, f
MCLK
= 5 MHz, f
MCLK
= 16 MHz, f
MCLK
= 5 MHz, f
MCLK
= 16 MHz, f
MCLK
= 5 MHz, f
MCLK
= 16 MHz, f
MCLK
= f
OUT
OUT
= f
OUT
OUT
= f
OUT
OUT
= f
OUT
OUT
= reset
OUT
OUT
/4096
MCLK
= f
MCLK
/4096
MCLK
= f
MCLK
/50
MCLK
= f
MCLK
/50
MCLK
= f
MCLK
= reset
/4096
/4096
/50
/50
Rev. A | Page 3 of 32
AD9838
Parameter1 Min Typ Max Unit Test Conditions/Comments
LOGIC INPUTS
Input High Voltage, V
2.0 V 2.7 V to 3.6 V power supply
2.8 V 4.5 V to 5.5 V power supply
Input Low Voltage, V
0.7 V 2.7 V to 3.6 V power supply
0.8 V 4.5 V to 5.5 V power supply
Input Current, I
INH/IINL
Input Capacitance, CIN 3 pF
POWER SUPPLIES
AVDD 2.3 5.5 V f
DVDD 2.3 5.5 V
5
I
3.7 5 mA
AA
5
I
I
DD
A Grade 0.9 2 mA
B Grade 1.2 2.4 mA
5
IAA + I
See Figure 6
DD
A Grade 4.6 7 mA
B Grade 4.9 7.4 mA
Low Power Sleep Mode DAC powered down; see Table 17
A Grade 0.4 mA
B Grade 0.4 mA
1
Operating temperature range is −40°C to +125°C; typical specifications are at 25°C.
2
For compliance with the specified load of 200 Ω, I
3
Guaranteed by design.
4
Applies when REFOUT is sourcing current. The impedance is higher when REFOUT is sinking current.
5
Measured with the digital inputs static and equal to 0 V or DVDD.
1.7 V 2.3 V to 2.7 V power supply
INH
0.6 V 2.3 V to 2.7 V power supply
INL
10 μA
full scale should not exceed 4 mA.
OUT
= 16 MHz, f
MCLK
code dependent; see Figure 7
DD
OUT
= f
MCLK
/4096
Rev. A | Page 4 of 32
AD9838
TIMING CHARACTERISTICS
DVDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted.
Table 2.
Parameter1 Limit at T
t1 200/62.5 ns min MCLK period (5 MHz/16 MHz)
t2 80/26 ns min MCLK high duration (5 MHz/16 MHz)
t3 80/26 ns min MCLK low duration (5 MHz/16 MHz)
t4 25 ns min SCLK period
t5 10 ns min SCLK high duration
t6 10 ns min SCLK low duration
t7 5 ns min FSYNC to SCLK falling edge setup time
t8 10 ns min SCLK falling edge to FSYNC rising edge time
t
− 5 ns max
4
t9 5 ns min Data setup time
t10 3 ns min Data hold time
t11 8 ns min FSELECT, PSELECT setup time before MCLK rising edge
t
8 ns min FSELECT, PSELECT setup time after MCLK rising edge
11A
t12 5 ns min SCLK high to FSYNC falling edge setup time
1
Guaranteed by design; not production tested.
Timing Diagrams
MIN
to T
Unit Description
MAX
MCLK
t
2
Figure 2. Master Clock
t
1
t
3
09077-003
MCLK
t
11A
09077-004
FSELECT,
PSELECT
t
11
VALID DATA VALID DATA VALID DATA
Figure 3. Control Timing
SCLK
FSYNC
SDATA
t
12
t
7
D15 D14 D2 D1 D15 D14
t
5
t
6
Figure 4. Serial Timing
t
4
t
8
t
10
t
9
D0
09077-005
Rev. A | Page 5 of 32
AD9838
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
AVDD to AGND −0.3 V to +6 V
DVDD to DGND −0.3 V to +6 V
AVDD to DVDD −0.3 V to +0.3 V
AGND to DGND −0.3 V to +0.3 V
CAP/2.5V 2.75 V
Digital I/O Voltage to DGND −0.3 V to DVDD + 0.3 V
Analog I/O Voltage to AGND −0.3 V to AVDD + 0.3 V
Operating Temperature Range
Industrial (B Version) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
Lead Temperature, Soldering (10 sec) 300°C
IR Reflow, Peak Temperature 220°C
Reflow Soldering (Pb Free)
Peak Temperature 260°C (+0/−5)
Time at Peak Temperature 10 sec to 40 sec
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type θJA θJC Unit
20-Lead LFCSP_WQ (CP-20-10) 49.5 5.3 °C/W
ESD CAUTION
Rev. A | Page 6 of 32
AD9838
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
T
UST
FSADJ
IOUTB
IOUT
19 REFO U
20 COMP
16
18
17
1
AVD D
2
DVDD
CAP/2.5V
DGND
MCLK
NOTES
1. CONNECT EXP OSED PAD TO GROUND.
3
4
5
AD9838
TOP
VIEW
(Not to Scale)
8
7
6
RESET
FSELECT
PSELECT
15 AGND
VIN
14
13
SIGN BIT OUT
12
FSYNC
11
SCLK
9
10
TA
SLEEP
SDA
09077-006
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 AVDD
Positive Power Supply for the Analog Section. AVDD can have a value from 2.3 V to 5.5 V. A 0.1 μF decoupling
capacitor should be connected between AVDD and AGND.
2 DVDD
Positive Power Supply for the Digital Section. DVDD can have a value from 2.3 V to 5.5 V. A 0.1 μF decoupling
capacitor should be connected between DVDD and DGND.
3 CAP/2.5V
The digital circuitry operates from a 2.5 V power supply. This 2.5 V is generated from DVDD using an on-board
regulator when DVDD exceeds 2.7 V. The regulator requires a decoupling capacitor of 100 nF typical, which is
connected from CAP/2.5V to DGND. If DVDD is less than or equal to 2.7 V, CAP/2.5V should be shorted to DVDD.
4 DGND Digital Ground.
5 MCLK
Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The
output frequency accuracy and phase noise are determined by this clock.
6 FSELECT
Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase
accumulator. The frequency register to be used can be selected using the FSELECT pin or the FSEL bit. When
the FSEL bit is used to select the frequency register, the FSELECT pin should be tied to CMOS high or low.
7 PSELECT
Phase Select Input. PSELECT controls which phase register, PHASE0 or PHASE1, is added to the phase accumulator
output. The phase register to be used can be selected using the PSELECT pin or the PSEL bit. When the PSEL bit
is used to select the phase register, the PSELECT pin should be tied to CMOS high or low.
8 RESET
Active High Digital Input. This pin resets the appropriate internal registers to 0 (this corresponds to an analog
output of midscale). RESET does not affect any of the addressable registers.
9 SLEEP
Active High Digital Input. When this pin is high, the DAC is powered down. This pin has the same function as
the SLEEP12 control bit.
10 SDATA Serial Data Input. The 16-bit serial data-word is applied to this input.
11 SCLK Serial Clock Input. Data is clocked into the AD9838 on each falling edge of SCLK.
12 FSYNC
Active Low Control Input. FSYNC is the frame synchronization signal for the input data. When FSYNC is taken
low, the internal logic is informed that a new word is being loaded into the device.
13 SIGN BIT OUT
Logic Output. The comparator output is available on this pin or, alternatively, the MSB from the NCO can be
output on this pin. Setting the OPBITEN bit in the control register to 1 enables this output pin. The SIGN/PIB bit
determines whether the comparator output or the MSB from the NCO is output on this pin.
14 VIN
Input to Comparator. The comparator can be used to generate a square wave from the sinusoidal DAC output.
The DAC output should be filtered appropriately before it is applied to the comparator to reduce jitter. When
the OPBITEN and SIGN/PIB bits in the control register are set to 1, the comparator input is connected to VIN.
15 AGND Analog Ground.
16, 17
IOUT,
IOUTB
Current Output. This is a high impedance current source. A load resistor of nominally 200 Ω should be connected
between IOUT and AGND. IOUTB should be tied to AGND through an external load resistor of 200 Ω, but it can
be tied directly to AGND. A 20 pF capacitor to AGND is also recommended to prevent clock feedthrough.
Rev. A | Page 7 of 32
AD9838
Pin No. Mnemonic Description
18 FSADJUST
Full-Scale Adjust Control. A resistor (R
of the full-scale DAC current. The relationship between R
IOUT
= 18 × FSADJUST/R
FULL SCALE
FSADJUST = 1.14 V nominal, R
19 REFOUT Voltage Reference Output. The AD9838 has an internal 1.20 V reference that is available at this pin.
20 COMP DAC Bias Pin. This pin is used for decoupling the DAC bias voltage.
EP Exposed Pad. Connect the exposed pad to ground.
) is connected between this pin and AGND to determine the magnitude
SET
SET
= 6.8 kΩ typical
SET
and the full-scale current is as follows:
SET
Rev. A | Page 8 of 32
AD9838
–
–
–
TYPICAL PERFORMANCE CHARACTERISTICS
6.0
5.5
5.0
(mA)
4.5
AA
+ I
DD
I
4.0
3.5
VDD = 5V
VDD = 3V
40
AVDD = DVDD = 3V
T
–45
0Hz TO NYQUIST
–50
–55
–60
SFDR (dB)
–65
–70
–75
= 25°C
A
MCLK/7
MCLK/50
3.0
024681012141618
Figure 6. Typical Current Consumption (I
2.5
2.0
1.5
(mA)
DD
I
1.0
0.5
0
024681012141618
Figure 7. Typical Current Consumption (I
91
AVDD = DVDD = 3V
= 25°C
T
A
–92
±200kHz
–93
–94
–95
SFDR (dB)
–96
–97
–98
MCLK FREQUENCY (MHz)
+ IAA) vs. MCLK Frequency
DD
= MCLK/10
for f
OUT
VDD = 5V
VDD = 3V
MCLK FREQUENCY ( MHz)
for f
OUT
MCLK/50
= MCLK/10
DD
MCLK/7
) vs. MCLK Frequency
–80
1611
09077-020
MCLK FREQUENCY (MHz)
16
09077-023
Figure 9. Wideband SFDR vs. MCLK Frequency
40
–45
–50
–55
SNR (dB)
–60
–65
–70
024681012141618
09077-021
MCLK FREQUENCY (MHz)
09077-024
Figure 10. SNR vs. MCLK Frequency
1000
900
800
700
600
WAKE-UP TIME (µs)
500
VDD = 5.5V
VDD = 2.3V
–99
02 46810121416
MCLK FREQUENCY (MHz)
Figure 8. Narrow-Band SFDR vs. MCLK Frequency
09077-022
400
–40 –20 0 20 40 60 80 100 120 140
TEMPERATURE ( °C)
Figure 11. Wake-Up Time vs. Temperature
09077-037
Rev. A | Page 9 of 32
AD9838
1.180
1.178
1.176
1.174
(V)
1.172
REF
V
1.170
1.168
1.166
1.164
–40 –20 0 20 40 60 80 100 120 140
VDD = 2.7V
TEMPERATURE (°C)
Figure 12. V
VDD = 5.0V
vs. Temperature
REF
09077-038
0
–10
–20
–30
–40
–50
–60
POWER (dB)
–70
–80
–90
–100
0 102030405060708090100
Figure 15. Power vs. Frequency, f
FREQUENCY (kHz)
= 16 MHz, f
MCLK
= 3.8 kHz,
OUT
Frequency Word = 0x000FBA9
09077-047
0.20
0.18
0.16
DVDD = 2.3V
0.14
0.12
0.10
DVDD (V)
0.08
0.06
0.04
0.02
0
–40 –20 0 20 40 60 80 100
Figure 13. SIGN BIT OUT Pin, Low Level, I
5.5
5.0
4.5
4.0
3.5
DVDD (V)
3.0
2.5
2.0
1.5
–40 –20 0 20 40 60 80 100
Figure 14. SIGN BIT OUT Pin, High Level, I
DVDD = 3.3V
TEMPERATURE (° C)
DVDD = 5.5V
DVDD = 4.5V
DVDD = 3.3V
DVDD = 2.7V
DVDD = 2.3V
TEMPERATURE (° C)
DVDD = 5.5V
= 1 mA
SINK
= 1 mA
SINK
0
–10
–20
–30
–40
–50
–60
POWER (dB)
–70
–80
–90
–100
09077-045
0 10 2030405060708090100
Figure 16. Power vs. Frequency, f
FREQUENCY (kHz)
= 5 MHz, f
MCLK
= 1.2 kHz,
OUT
09077-048
Frequency Word = 0x000FBA9
0
–10
–20
–30
–40
–50
–60
POWER (dB)
–70
–80
–90
–100
09077-046
0 0.51.01.52.02.
Figure 17. Power vs. Frequency, f
FREQUENCY (MHz)
= 5 MHz, f
MCLK
= 0.714 MHz = f
OUT
5
09077-049
/7,
MCLK
Frequency Word = 0x2492492
Rev. A | Page 10 of 32
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