Analog Devices AD9834EB, AD9834BRU Datasheet
REV PrM 04/02
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=
Low Power, +2.3 V to +5.5 V, 50 MHz
Complete DDS
Preliminary Technical Data AD9834
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106,U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
FEATURES
+2.3 V to +5.5 V Power Supply
50 MHz Speed
Low Jitter Clock Output
Sine Output/Triangular Output
Serial Loading
Power-Down Option
Narrowband SFDR > 72 dB
20 mW Power Consumption at 3 V
20-Pin TSSOP
APPLICATIONS
Test Equipment
Slow Sweep Generator
DDS Tuning
Digital Modulation
GENERAL DESCRIPTION
The AD9834 is a numerically controlled oscillator
employing a phase accumulator, a SIN ROM and a
10-bit D/A converter integrated on a single CMOS
chip. Clock rates up to 50 MHz are supported with a
power supply from 2.3 V to 5.5 V.
FUNCTIONAL BLOCK DIAGRAM
10-Bit
DAC
IOUT
COMP
REFOUT
FullScale
Control
FS ADJUST
AD9834
IOUTB
SIGN BIT OUT
COMPARATOR
VIN
MUX
Serial Interface
&
Control Logic
SCLK
SDATAFSYNC
12 Bit PHASE1 REG
SLEEPPSELECT
16 Bit Control
Register
SIN
ROM
MUX
28 Bit
FREQ0 REG
MCLK
FSELECT
28 Bit
FREQ1 REG
12
On-Board
Reference
AGNDAVDD DGND DVDD
Phase
Accumulator
(28 Bit)
MUX
Regulator
CAP/2.5V
VCC
2.5V
RESET
12 Bit PHASE0 REG
MSB
MUX
DIV BY
2
MUX
Capability for phase modulation and frequency modulation is provided. Frequency accuracy can be controlled to
one part in 0.25 billion. Modulation is effected by loading
registers through the serial interface.
The AD9834 offers the user a variety of output
waveforms. The SIN ROM can be bypassed so that a
linear up/down ramp is output from the DAC. If the SIN
ROM is not by-passed, a sinusoidal output is available.
Also, if a clock output is required, the MSB of the DAC
data can be output, or the on-chip comparator can be
used.
The digital section is driven by an on-board regulator
which steps down the applied DVDD to +2.5 V when
DVDD exceeds +2.5 V. The analog and digital sections
are independent and can be run from different power
supplies e.g. AVDD can equals 5 V with DVDD equal to
3 V, etc.
The AD9834 has a power-down pin (SLEEP) which
allows external control of a power-down mode. Sections of
the device which are not being used can be powered down to
minimise the current consumption e.g. the DAC can be
powered down when a clock output is being generated.
The part is available in a 20-pin TSSOP package.
PRELIMINAR Y TECHNICAL DAT A
AD9834
–2–
REV PrM
PRELIMINAR Y TECHNICAL DAT A
Parameter Min Typ Max Units Test Conditions/Comments
SIGNAL DAC SPECIFICATIONS
Resolution 10 Bits
Update Rate (f
MAX
) 50 MSPS
I
OUT
Full Scale 2.8 mA
Output Compliance
2
0.8 V
DC Accuracy:
Integral Nonlinearity ±1 LSB
Differential Nonlinearity ±0.5 LSB
DDS SPECIFICATIONS
Dynamic Specifications:
Signal to Noise Ratio 50 dB f
MCLK
= 50 MHz, f
OUT
= f
MCLK
/4096
Total Harmonic Distortion -53 dBc f
MCLK
= 50 MHz, f
OUT
= f
MCLK
/4096
Spurious Free Dynamic Range (SFDR):
Wideband (0 to Nyquist) 50 dBc f
MCLK
= 50 MHz, f
OUT
= f
MCLK
/7
NarrowBand (± 200 kHz) 72 dBc f
MCLK
= 50 MHz, f
OUT
= f
MCLK
/7
Clock Feedthrough –55 dBc
Wake Up Time 1 ms
COMPARATOR
Input Voltage Range 1 V p-p ac-coupled internally
Input Capacitance 10 pF
Input HighPass Cutoff Frequency 4 MHz
Input DC Resistance 1 M Ω
Input DC Current 10 µA
OUTPUT BUFFER
Output Rise/Fall Time 20 ns Using a 15 pF Load
Output Jitter 100 ps rms When DAC data MSB is output
VOLTAGE REFERENCE
Internal Reference 1.116 1.2 1.284 V 1.2 V ± 7%
REFOUT Input Impedance
3
1KΩ
Reference TC 100 ppm/°C
LOGIC INPUTS
V
INH
, Input High Voltage D
VDD
–0.9 V +3.6 V to +5.5 V Power Supply
D
VDD
- 0.5 V +2.7 V to +3.6 V Power Supply
2 V +2.3 V to + 2.7 V Power Supply
V
INL
, Input Low Voltage 0.9 V +3.6 V to +5.5 V Power Supply
0.5 V +2.3 V to + 3.6 V Power Supply
I
INH
, Input Current 1 µA
CIN, Input Capacitance 10 pF
POWER SUPPLIES f
MCLK
= 50 MHz, f
OUT
= f
MCLK
/7
AVDD 2.3 5.5 V
DVDD 2.3 5.5 V
I
AA
4
5mA
I
DD
4
0.5 + 0.04/MHz mA
I
AA
+ I
DD
4
7 10 mA 3 V Power Supply
10 15 mA 5 V Power Supply
Low Power Sleep Mode
4
0.25 mA DAC and Internal Clock Powered Down
NOTES
1
Operating temperature range is as follows: B Version: –40°C to +85°C; typical specifications are at 25ⴗC
2
Guaranteed by Design.
3
Applies when REFOUT is sourcing current. The impedance is higher when REFOUT is sinking current.
4
Measured with the digital inputs static and equal to 0 V or DVDD.
Specifications subject to change without notice. There is 95% test coverage of the digital circuitry.
SPECIFICATIONS
1
(VDD = +2.3 V to +5.5 V; AGND = DGND = 0 V; TA = T
MIN
to T
MAX
; R
SET
= 6.8 k
Ω;Ω;
Ω;Ω;
Ω;
R
LOAD
= 200
ΩΩ
ΩΩ
Ω for IOUT and IOUTB unless otherwise noted)
AD9834
–3–
REV PrM
PRELIMINAR Y TECHNICAL DA TA
TIMING CHARACTERISTICS
1
(VDD = +2.3 V to +5.5 V; AGND = DGND = 0 V, unless otherwise noted)
Parameter Limit at T
MIN
to T
MAX
Units Test Conditions/Comments
t
1
20 ns min MCLK Period
t
2
8 ns min MCLK High Duration
t
3
8 ns min MCLK Low Duration
t
4
25 ns min SCLK Period
t
5
10 ns min SCLK High Duration
t
6
10 ns min SCLK Low Duration
t
7
5 ns min FSYNC to SCLK Falling Edge Setup Time
t
8
10 ns min FSYNC to SCLK Hold Time
t
4
- 5 ns max
t
9
5 ns min Data Setup Time
t
10
3 ns min Data Hold Time
t
11
8 ns min FSELECT, PSELECT Setup Time Before MCLK Rising Edge
t
11A
*
8 ns min FSELECT, PSELECT Setup Time After MCLK Rising Edge
1
Guaranteed by design, not production tested.
*See Pin Description Section.
Figure 3. Control Timing
Figure 2. Master Clock
Figure 4. Serial Timing
Figure 1. Test Circuit With which Specifications are tested.
IOUT
COMP
FS
ADJUST
REFOUT
12
AD9834
ON-BOARD
REFERENCE
10-BIT DAC
SIN
ROM
FULL-SCALE
CONTROL
200R 20pF
R
SET
6.8 K
10nF
10nF
AVDD
REGULATOR
100nF
CAP/2.5V
MCLK
t
2
t
1
t
3
t
11A
t
11
VALIDDATA VALIDDATA VALIDDATA
MCLK
FSELECT,
PSELECT
SCLK
FSYNC
SDATA
t
5
t
4
t
6
t
7
t
8
t
10
t
9
D15 D14 D2 D1 D0 D15 D14
AD9834
–4–
REV PrM
PRELIMINAR Y TECHNICAL DAT A
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
AGND to DGND. . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
CAP/2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.75 V
Digital I/O Voltage to DGND –0.3 V to DVDD + 0.3 V
Analog I/O Voltage to AGND –0.3 V to AVDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . –40°C to +85°C
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD9834BRU –40°C to +85°C 20-Pin TSSOP (
Thin Shrink Small Outline Package
) RU-20
EVAL-AD9834EB Evaluation Board
PIN CONFIGURATION
Storage Temperature Range . . . . . . . . .–65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . +150°C
TSSOP Package
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . .143°C/W
θ
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . 45°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . 300°C
IR Reflow, Peak Temperature . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9834 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
TOP VIEW
(Notto Scale)
O
FS ADJUST
REFOUT
AVDD
DVDD
CAP/+2.5V
DGND
MCLK
IOUTB
IOUT
AGND
VIN
SIGNBITOUT
FSYNC
SCLK
SDATA
AD9834
FSELECT
PSELECT
12
11
10
9
COMP
SLEEP
RESET
AD9834
–5–
REV PrM
PRELIMINAR Y TECHNICAL DA TA
PIN FUNCTIONS DESCRIPTIONS
Pin # Mnemonic Function
ANALOG SIGNAL AND REFERENCE
1 FS ADJUST Full-Scale Adjust Control. A resistor (R
SET
) is connected between this pin and AGND. This
determines the magnitude of the full-scale DAC current. The relationship between R
SET
and
the full-scale current is as follows:
IOUT
FULL-SCALE
= 18 x V
REFOUT/RSET
V
REFOUT
= 1.20 V nominal, R
SET
= 6.8 kΩ typical
2 REFOUT Voltage Reference Output. The AD9834 has an internal 1.20 V reference, which is made
available at this pin.
3 COMP A DAC Bias Pin. This pin is used for de-coupling the DAC bias voltage.
17 VIN Input to comparator. The comparator can be used to generate a square wave from the
sinusoidal DAC output. The DAC output should be filtered appropriately before being applied
to the comparator to improve jitter. When bits OPBITEN and SIGNPIB in the control
register are set to 1, the comparator input is connected to VIN.
19,20 IOUT, IOUTB Current Output. This is a high impedance current source. A load resistor of nominally 200 Ω
should be connected between IOUT and AGND. IOUTB should preferably be tied through an
external load resistor of 200 Ω to AGND but can be tied directly to AGND. A 20pF capacitor
to AGND is also recommended to prevent clock feedthrough.
POWER SUPPLY
4 AVDD Positive power supply for the analog section. AVDD can have a value from +2.3 V to +5.5 V.
A 0.1 µF decoupling capacitor should be connected between AVDD and AGND.
5 DVDD Positive power supply for the digital section. DVDD can have a value from +2.3 V to +5.5 V.
A 0.1 µF decoupling capacitor should be connected between DVDD and DGND.
6 CAP/2.5V The digital circuitry operates from a +2.5 V power supply. This +2.5 V is generated from
DVDD using an on board regulator (when DVDD exceeds +2.7 V). The regulator requires a
decoupling capacitor of typically 100 nF which is connected from CAP/2.5V to DGND. If
DVDD is equal to or less than +2.7 V, CAP/2.5 V should be shorted to DVDD.
7 DGND Digital Ground.
18 AGND Analog Ground.
DIGITAL INTERFACE AND CONTROL
8 MCLK Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the
frequency of MCLK. The output frequency accuracy and phase noise are determined by this
clock.
9 FSELECT Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is
used in the phase accumulator. The frequency register to be used can be selected using the pin
FSELECT or the bit FSEL. When the bit FSEL is being used to select the frequency register,
this pin, FSELECT, should be tied to CMOS high or low.
10 PSELECT Phase Select Input. PSELECT controls which phase register, PHASE0 or PHASE1, is added
to the phase accumulator output. The phase register to be used can be selected using the pin
PSELECT or the bit PSEL. When the phase registers are being controlled by the bit PSEL,
this pin, PSELECT, should be tied to CMOS high or low.
11 RESET Active high digital input. RESET resets appropriate internal registers to zero which
corresponds to an analog output of midscale. RESET does not affect any of the addressable
registers.
12 SLEEP Active high digital input. When this pin is high, the DAC is powered down. This pin has the
same function as control bit SLEEP12.
13 SDATA Serial Data Input. The 16-bit serial data word is applied to this input.
14 SC L K Serial Clock Input. Data is clocked into the AD9834 on each falling SCLK edge.
15 FSYNC Active Low Control Input. This is the frame synchronisation signal for the input data. When
FSYNC is taken low, the internal logic is informed that a new word is being loaded into
the device.
16 SIGN BIT OUT Logic Output. The comparator output is available on this pin or, alternatively, the MSB from
the NCO can be output on this pin. Setting bit OPBITEN in the control register to 1 enables
this output pin. Bit SIGNPIB determines whether the comparator output or the MSB from
the NCO is output on the pin.
AD9834
–6–
REV PrM
PRELIMINAR Y TECHNICAL DAT A
Typical Performance Characteristics
TPC 1. Typical Current Consumption
vs. MCLK Frequency
TPC 4. Wide Band SFDR vs. f
OUT/fMCLK
for Various MCLK Frequencies
TPC 7. Wake-Up Time vs.
Temperature
TPC 2. Narrow Band SFDR vs. MCLK
Frequency
TPC 5. SNR vs. MCLK Frequency
TPC 8. V
REFOUT
vs. Temperature
TPC 3. Wide Band SFDR vs. MCLK
Frequency
TPC 6. SNR vs. f
OUT/fMCLK
for
Various MCLK Frequencies
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