ANALOG DEVICES AD9832 Service Manual

25 MHz Direct Digital Synthesizer,

A

A

Data Sheet

FEATURES

25 MHz speed
On-chip COS lookup table
On-chip, 10-bit DAC
Serial loading
Power-down option
Temperature range: −40°C to +85°C
200 mW power consumption
16-Lead TSSOP

APPLICATIONS

Frequency stimulus/waveform generation
Frequency phase tuning and modulation
Low power RF/communications systems
Liquid and gas flow measurement
Sensory applications: proximity, motion, and defect

detection

Test and medical equipment

Waveform Generator

AD9832

GENERAL DESCRIPTION

The AD9832 is a numerically controlled oscillator employing
a phase accumulator, a sine look-up table, and a 10-bit digital­to-analog converter (DAC) integrated on a single CMOS chip.
Modulation capabilities are provided for phase modulation and
frequency modulation.

Clock rates up to 25 MHz are supported. Frequency accuracy can
be controlled to one part in 4 billion. Modulation is effected by
loading registers through the serial interface.

A power-down bit allows the user to power down the AD9832
when it is not in use, the power consumption being reduced to
5 mW (5 V) or 3 mW (3 V). The part is available in a 16-lead
TSSOP package.

Similar DDS products can be found at

http://www.analog.com/DDS.

FUNCTIONAL BLOCK DIAGRAM

GND

VDDDGNDDVDD

MCLK

FSELECT

FSELECT

BIT

FREQ0 REG

FREQ1 REG

16-BIT DATA REGISTER

FSYNC SCLK SDATA

SELSRC

MUX

MUX

SYNC

8 LSBs8 MSBs

DECODE LOG IC

SERIAL REGI STER

SYNC

ACCUMULATOR

PHASE0 REG

PHASE1 REG

PHASE2 REG

PHASE3 REG

DEFER REGIS TER

PHASE

(32 BIT)

MUX

CONTROL REG ISTER

FSELECT/PSEL REGISTER

ON-BOARD

REFERENCE

12

SELSRC

SIN

ROM

SYNC

AD9832

SYNC

MUX MUX

PSEL0

BIT

PSEL0 PSEL1

Figure 1.

REFINFS ADJUSTREFOUT

FULL-SCALE

CONTROL

10-BIT DAC

PSEL1

BIT

COMP

IOUT

09090-001

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©1999–2011 Analog Devices, Inc. All rights reserved.

AD9832 Data Sheet

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Terminology .................................................................................... 11

Theory of Operation ...................................................................... 12

Circuit Description......................................................................... 13

Numerical Controlled Oscillator and Phase Modulator....... 13

Sine Look-Up Table (LUT)........................................................ 13

Digital-to-Analog Converter .................................................... 13

Functional Description.................................................................. 14

Serial Interface ............................................................................ 14

Direct Data Transfer and Deferred Data Transfer ................. 14

Latency......................................................................................... 16

Flowcharts ................................................................................... 16

Applications Information.............................................................. 19

Grounding and Layout.............................................................. 19

Interfacing the AD9832 to Microprocessors.............................. 19

AD9832 to ADSP-21xx Interface ............................................. 19

AD9832 to 68HC11/68L11 Interface....................................... 20

AD9832 to 80C51/80L51 Interface.......................................... 20

AD9832 to DSP56002 Interface ............................................... 20

Evaluation Board............................................................................ 21

System Demonstration Platform.............................................. 21

AD9832 to SPORT Interface..................................................... 21

XO vs. External Clock................................................................ 21

Power Supply............................................................................... 21

Evaluation Board Schematics ................................................... 22

Evaluation Board Layout........................................................... 24

Ordering Information.................................................................... 25

Bill of Materials........................................................................... 25

Outline Dimensions....................................................................... 26

Ordering Guide .......................................................................... 26

REVISION HISTORY

9/11—Rev. B to Rev. C

Changes to Features and Applications........................................... 1

Changes to Specification Statement............................................... 3

Changes to Timing Characteristics Statement ............................. 5

Replaced Evaluation Board Section; Renumbered

Sequentially ..................................................................................... 21

Changes to Ordering Guide.......................................................... 26

6/10—Rev. A to Rev. B

Updated Format..................................................................Universal

Changed CMOS Complete DDS to 3 V to 5.0 V Programmable

Waveform Generator........................................................................ 1

Changes to Serial Interface Section.............................................. 14

Updated Outline Dimensions....................................................... 23

Changes to Ordering Guide.......................................................... 23

7/99—Rev 0 to Rev. A

Rev. C | Page 2 of 28

Data Sheet AD9832

SPECIFICATIONS

VDD = +5 V ± 5%; AGND = DGND = 0 V; TA = T
noted. Also, see Figure 2.

Table 1.

Parameter1 AD9832B Unit Test Conditions/Comments

SIGNAL DAC SPECIFICATIONS

Resolution 10 Bits
Update Rate (f

) 25 MSPS nom

MAX

IOUT Full Scale 4 mA nom

4.5 mA max
Output Compliance 1.35 V max 3 V power supply
DC Accuracy

Integral Nonlinearity ±1 LSB typ
Differential Nonlinearity ±0.5 LSB typ

DDS SPECIFICATIONS2

Dynamic Specifications

Signal-to-Noise Ratio 50 dB min f
Total Harmonic Distortion −53 dBc max f
Spurious-Free Dynamic Range (SFDR)3 f

Narrow Band (±50 kHz) −72 dBc min 5 V power supply

−70 dBc min 3 V power supply

Wideband (±2 MHz) −50 dBc min
Clock Feedthrough −60 dBc typ
Wake-Up Time4 1 ms typ
Power-Down Option Yes

VOLTAGE REFERENCE

Internal Reference @ 25°C 1.21 V typ

T

to T

MIN

1.21 ± 7% V min/V max

MAX

REFIN Input Impedance 10 MΩ typ
Reference Temperature Coefficient (TC) 100 ppm/°C typ
REFOUT Output Impedance 300 Ω typ

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

INH

V

INH

0.9 V max

INL

10 μA max

Input Capacitance, CIN 10 pF max

POWER SUPPLIES

AVDD 2.97/5.5 V min/V max
DVDD 2.97/5.5 V min/V max
IAA 5 mA max 5 V power supply
IDD 2.5 + 0.4/MHz mA typ 5 V power supply

5

IAA + I

15 mA max 3 V power supply

DD

24 mA max 5 V power supply
Low Power Sleep Mode 350 μA max

1

Operating temperature range is −40°C to +85°C.

2

100% production tested.

3

f

= 6.25 MHz, frequency word = 0x5671C71C, and f

MCLK

4

See . To reduce the wake-up time at low power supplies and low temperature, the use of an external reference is suggested. Figure 13

5

Measured with the digital inputs static and equal to 0 V or DVDD. The AD9832 is tested with a capacitive load of 50 pF. The part can operate with higher capacitive

loads, but the magnitude of the analog output will be attenuated. For example, a 5 MHz output signal is attenuated by 3 dB when the load capacitance equals 85 pF.

MIN

= 2.11 MHz.

OUT

to T

; REFIN = REFOUT; R

MAX

− 0.9 V min

DD

= 3.9 kΩ; R

SET

= 300 Ω for IOUT, unless otherwise

LOAD

= 25 MHz, f

MCLK

= 25 MHz, f

MCLK

= 6.25 MHz, f

MCLK

= 1 MHz

OUT

= 1 MHz

OUT

= 2.11 MHz

OUT

Rev. C | Page 3 of 28

AD9832 Data Sheet

10nF

REFOUT

ON-BOARD

REFERENCE

12

SIN

ROM

REFIN

FULL-SCALE

CONTROL

10-BIT DAC

R

SET

3.9kΩ

FS
ADJUST

AD9832

COMP

IOUT

AVDD

10nF

300Ω 50pF

9090-002

Figure 2. Test Circuit by Which Specifications Were Tested

Rev. C | Page 4 of 28

Data Sheet AD9832

TIMING CHARACTERISTICS

VDD = +5 V ± 5%; AGND = DGND = 0 V, unless otherwise noted.

Table 2.

Parameter Limit at T

t1 40 ns min MCLK period
t2 16 ns min MCLK high duration
t3 16 ns min MCLK low duration
t4 50 ns min SCLK period
t5 20 ns min SCLK high duration
t6 20 ns min SCLK low duration
t7 15 ns min FSYNC to SCLK falling edge setup time
t8 20 ns min FSYNC to SCLK hold time
SCLK − 5 ns max
t9 15 ns min Data setup time
t10 5 ns min Data hold time
t11 8 ns min FSELECT, PSEL0, PSEL1 setup time before MCLK rising edge

1

t

8 ns min FSELECT, PSEL0, PSEL1 setup time after MCLK rising edge

11A

1

See the section. Pin Configuration and Function Descriptions

Timing Diagrams

SCLK

FSYNC

SDATA

MIN

to T

(B Version) Unit Test Conditions/Comments

MAX

t

1

MCLK

t

2

t

3

09090-003

Figure 3. Master Clock

t

t

5

4

t

7

t

6

t

10

t

9

t

8

Figure 4. Serial Timing

D14D15D0D1D2D15 D14

09090-004

MCLK

t

11A

09090-005

FSELECT

PSEL0, PSEL1

t

11

VALID DATA VALID DATA VALID DATA

Figure 5. Control Timing

Rev. C | Page 5 of 28

AD9832 Data Sheet

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to AGND −0.3 V to +7 V
DVDD to DGND −0.3 V to +7 V
AVDD to DVDD −0.3 V to +0.3 V
AGND to DGND −0.3 V to +0.3 V
Digital I/O Voltage to DGND −0.3 V to DVDD + 0.3 V
Analog I/O Voltage to AGND −0.3 V to AVDD + 0.3 V
Operating Temperature Range

Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
TSSOP θJA Thermal Impedance 158°C/W
Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C
ESD Rating >4500 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. C | Page 6 of 28

Data Sheet AD9832

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

FS ADJUST

REFIN

REFOUT

DVDD

DGND

MCLK

SCLK

SDATA

1

2

3

AD9832

4

TOP VIEW

5

(Not to Scale)

6

7

8

16

15

14

13

12

11

10

9

COMP

AVDD

IOUT

AGND

PSEL0

PSEL1

FSELECT

FSYNC

09090-006

Figure 6. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 FS ADJUST

Full-Scale Adjust Control. A resistor (R
magnitude of the full-scale DAC current. The relationship between R

IOUT

2 REFIN

Voltage Reference Input. The AD9832 can be used with either the on-board reference, which is available from

FULL-SCALE

= 12.5 × V

REFIN/RSET

, where V

) is connected between this pin and AGND. This determines the

SET

= 1.21 V nominal and R

REFIN

and the full-scale current is

SET

= 3.9 kΩ typical.

SET

the REFOUT pin, or an external reference. The reference to be used is connected to the REFIN pin. The AD9832
accepts a reference of 1.21 V nominal.

3 REFOUT

Voltage Reference Output. The AD9832 has an on-board reference of value 1.21 V nominal. The reference is
available on the REFOUT pin. This reference is used as the reference to the DAC by connecting REFOUT to REFIN.
REFOUT should be decoupled with a 10 nF capacitor to AGND.

4 DVDD

Positive Power Supply for the Digital Section. A 0.1 μF decoupling capacitor should be connected between

DVDD and DGND. DVDD can have a value of 5 V ± 10% or 3.3 V ± 0%.
5 DGND Digital Ground.
6 MCLK

Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. This

clock determines the output frequency accuracy and phase noise.
7 SCLK Serial Clock, Logic Input. Data is clocked into the AD9832 on each falling SCLK edge.
8 SDATA Serial Data In, Logic Input. The 16-bit serial data-word is applied to this input.
9 FSYNC

Data Synchronization Signal, Logic Input. When this input goes low, the internal logic is informed that

a new word is being loaded into the device.
10 FSELECT

Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase

accumulator. The frequency register to be used can be selected using the FSELECT pin or the FSELECT bit. FSELECT

is sampled on the rising MCLK edge. FSELECT needs to be in steady state when an MCLK rising edge occurs. If

FSELECT changes value when a rising edge occurs, there is an uncertainty of one MCLK cycle as to when control is

transferred to the other frequency register. To avoid any uncertainty, a change on FSELECT should not coincide with an

MCLK rising edge. When the bit is being used to select the frequency register, the FSELECT pin should be tied to DGND.
11, 12

PSEL1,
PSEL0

Phase Select Input. The AD9832 has four phase registers. These registers can be used to alter the value being

input to the SIN ROM. The contents of the phase register are added to the phase accumulator output, the inputs

PSEL0 and PSEL1 selecting the phase register to be used. Alternatively, the phase register to be used can be

selected using the PSEL0 and PSEL1 bits. Like the FSELECT input, PSEL0 and PSEL1 are sampled on the rising

MCLK edge. Therefore, these inputs need to be in steady state when an MCLK rising edge occurs or there is an

uncertainty of one MCLK cycle as to when control is transferred to the selected phase register. When the phase

registers are being controlled by the PSEL0 and PSEL1 bits, the pins should be tied to DGND.
13 AGND Analog Ground.
14 IOUT Current Output. This is a high impedance current source. A load resistor should be connected between IOUT and AGND.
15 AVDD

Positive Power Supply for the Analog Section. A 0.1 μF decoupling capacitor should be connected between

AVDD and AGND. AVDD can have a value of 5 V ± 10% or 3.3 V ± 10%.
16 COMP

Compensation Pin. This is a compensation pin for the internal reference amplifier. A 10 nF decoupling ceramic

capacitor should be connected between COMP and AVDD.

Rev. C | Page 7 of 28

AD9832 Data Sheet

–

–

–

TYPICAL PERFORMANCE CHARACTERISTICS

25

T

= 25°C

A

20

15

5V

10

TOTAL CURRENT (mA)

3.3V

5

40

AVDD = DVDD = 3.3V

–45

–50

–55

–60

–65

SFDR (±2MHz) (d B)

–70

–75

25MHz

10MHz

0

MCLK FR EQUENC Y (MHz)

15 20

Figure 7. Typical Current Consumption vs. MCLK Frequency

50

f

AVDD = DVDD = 3.3V

–55

–60

–65

–70

SFDR (±50kHz) (dB)

–75

–80

OUT/fMCLK

= 1/3

MCLK FREQUENCY (MHz)

Figure 8. Narrow-Band SFDR vs. MCLK Frequency

40

f

AVDD = DVDD = 3.3V

–45

–50

–55

SFDR (±2MHz) (d B)

–60

OUT/fMCLK

= 1/3

25105

09090-007

2510 15 20

09090-008

–80

Figure 10. Wideband SFDR vs. f

60

AVDD = DVDD = 3.3V

f

= f

OUT

55

50

SNR (dB)

45

40

/3

MCLK

MCLK FREQUENCY (MHz)

0.2 0.3

f

OUT/fMCLK

for Various MCLK Frequencies

OUT/fMCLK

20

0.40.10

09090-010

251510

09090-011

Figure 11. SNR vs. MCLK Frequency

60

AVDD = DVDD = 3.3V

55

50

SNR (dB)

45

10MHz

25MHz

–65

MCLK FREQUENCY (MHz)

Figure 9. Wideband SFDR vs. MCLK Frequency

2510 15 20

09090-009

40

Figure 12. SNR vs. f

f

/

f

OUT

MCLK

for Various MCLK Frequencies

OUT/fMCLK

0.40.30. 20.10

09090-012

Rev. C | Page 8 of 28

Data Sheet AD9832

V

V

V

V

V

WAKE-UP TIME (ms)

Figure 14. f

Figure 15. f

10.0

AVDD = DVDD = 2.97V

7.5

5.0

2.5

0

0

–10

–20

–30

–40

–50

10dB/DI

–60

–70

–80

–90

–100

START 0Hz
RBW 300Hz

MCLK

0

–10

–20

–30

–40

–50

10dB/DI

–60

–70

–80

–90

–100

START 0Hz
RBW 300Hz

= 25 MHz, f

MCLK

–20 –10

TEMPERATURE (°C)

Figure 13. Wake-Up Time vs. Temperature

STOP 12. 5MHz

STOP 12.5MHz

= 25 MHz, f

VBW 1kHz

= 1.1 MHz, Frequency Word = 0xB439581

OUT

VBW 1kHz

= 2.1 MHz, Frequency Word = 0x15810625

OUT

ST 277 SEC

ST 277 SEC

0

–10

–20

–30

–40

–50

10dB/DI

–60

–70

–80

–90

–100

10dB/DI

–100

10dB/DI

–100

–10

–20

–30

–40

–50

–60

–70

–80

–90

–10

–20

–30

–40

–50

–60

–70

–80

–90

START 0Hz
RBW 300Hz

MCLK

0

START 0Hz
RBW 300Hz

MCLK

0

START 0Hz
RBW 300Hz

MCLK

= 25 MHz, f

= 25 MHz, f

= 25 MHz, f

VBW 1kHz

= 3.1 MHz, Frequency Word = 0x1FBE76C9

OUT

VBW 1kHz

= 4.1 MHz, Frequency Word = 0x29FBE76D

OUT

VBW 1kHz

= 5.1 MHz, Frequency Word = 0x34395810

OUT

0–30–40

09090-013

Figure 16. f

09090-014

Figure 17. f

09090-015

Figure 18. f

STOP 12.5MHz

ST 277 SEC

STOP 12.5MHz

ST 277 SEC

STOP 12.5MHz

ST 277 SEC

09090-016

09090-017

09090-018

Rev. C | Page 9 of 28