ANALOG DEVICES AD9789 Service Manual

14-Bit, 2400 MSPS RF DAC

FEATURES

DOCSIS 3.0 performance: 4 QAM carriers

ACLR over full band (47 MHz to 1 GHz)

−75 dBc @ f

−72 dBc @ f

−67 dBc @ f

Unequalized MER = 42 dB

On chip and bypassable

4 QAM encoders with SRRC filters, 16× to 512× interpolation,

rate converters, and modulators Flexible data interface: 4, 8, 16, or 32 bits wide with parity Power: 1.6 W (I Direct to RF synthesis support with f Built-in self-test (BIST) support

Input connectivity check Internal random number generator

APPLICATIONS

Broadband communications systems CMTS/DVB Cellular infrastructure Point-to-point wireless

GENERAL DESCRIPTION

The AD9789 is a flexible QAM encoder/interpolator/upconverter combined with a high performance, 2400 MSPS, 14-bit RF digitalto-analog converter (DAC). The flexible digital interface can accept up to four channels of complex data. The QAM encoder supports constellation sizes of 16, 32, 64, 128, and 256 with SRRC filter coefficients for all standards.

= 200 MHz

OUT

= 800 MHz (noise)

OUT

= 800 MHz (harmonics)

OUT

= 20 mA, f

FS

= 2.4 GHz, LVDS interface)

DAC

mix mode

S

with 4-Channel Signal Processing

AD9789

The on-chip rate converter supports a wide range of baud rates with a fixed DAC clock. The digital upconverter can place the channels from 0 to 0.5 × f channels to be synthesized and placed anywhere from dc to f

The AD9789 includes a serial peripheral interface (SPI) for device configuration and status register readback. The flexible digital interface can be configured for data bus widths of 4, 8, 16, and 32 bits. It can accept real or complex data.

The AD9789 operates from 1.5 V, 1.8 V, and 3.3 V supplies for a total power consumption of 1.6 W. It is supplied in a 164-ball chip scale package ball grid array for lower thermal impedance and reduced package parasitics. No special power sequencing is required. The clock receiver powers up muted to prevent start-up noise.

PRODUCT HIGHLIGHTS

1. Highly integrated and configurable QAM mappers, inter-

polators, and upconverters for direct synthesis of one to four DOCSIS- or DVB-C-compatible channels in a block.

2. Low noise and intermodulation distortion (IMD) perfor-

mance enable high quality synthesis of signals up to 1 GHz.

3. Flexible data interface supports LVDS for improved SFDR

or CMOS input data for less demanding applications.

4. Interface is configurable from 4-bit nibbles to 32-bit words

and can run at up to 150 MHz CMOS or 150 MHz LVDS double data rate (DDR).

5. Manufactured on a CMOS process, the AD9789 uses a

proprietary switching technique that enhances dynamic performance.

. This permits four contiguous

DAC

/2.

FUNCTIONAL BLOCK DIAGRAM

CMOS

0TO 15

32 INPUT

PINS AND

2PARITY

PINS

DCO

FS

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

150MHz

LVDS/CMOS

LVDS

RISE

CMOS

16 TO 31

LVDS FALL

RETIMER

DATA FORMATTER/

ASSEMBLER

DATA

Figure 1.

QAM/

FILTER/

NCO

QAM/

FILTER/

NCO

QAM/

FILTER/

NCO

QAM/

FILTER/

NCO

16×

INTERPOLATOR

AND BPF

+ SCALARS

SPI

IRQ RS

14-BIT

2.4GSPS DAC

07852-001

AD9789

REVISION HISTORY

7/11—Rev. 0 to Rev. A

Changes to Table 2, DAC Clock Input (CLKP, CLKN): Added

DAC Clock Rate Parameter............................................................. 5

Changes to Table 3, Dynamic Performance, DAC Update Rate

Parameter; Added Adjusted DAC Update Rate Parameter......... 6

Changes to Captions for Figure 42, Figure 44, Figure 46,

Figure 49 ..........................................................................................18

Changes to Digital 16x Tunable Band-Pass Filter Section, Third

Paragraph......................................................................................... 44

Changes to Retimer and Latency Look-Up Tables Section,

Second Paragraph........................................................................... 50

Changes to Captions for Figure 122, Figure 124, Figure 125.... 65

4/09—Revision 0: Initial Version

Rev. A | Page 2 of 76

AD9789

DETAILED FUNCTIONAL BLOCK DIAGRAMS

DATA-

PATH

0

DATA-

PATH

1

DATA-

PATH

2

DATA-

PATH

3

SUM

SCALE

16×

INTERPOLATOR

f

= 0 TO

C

f

DAC

BPF

/2

f

C

07852-002

32 INPUT

PINS

P0 P1

FS

DCO

LVD S/C MOS

CMOS

0TO 15

LVD S

RISE

CMOS

16 TO 31

LVD S FALL

RETIMER

CLK CTL

4TO

32 BITS

DATA FORMATTER/

ASSEMBLER

UP TO

32 BITS

UP TO

32 BITS

UP TO

32 BITS

UP TO

32 BITS

Figure 2. Digital Signal Processing Functional Block Diagram

24-BIT NCO

f

/16

0TO

QAM

MAPPER

INPUT

SCALE

BYPASS

QAM

SRRC

2

BYPASS

SRRC

RATE

N

2

(N = 0 TO 5) (P/Q = 0.5TO 1)

CONVERT ER

P/Q 24-BI T

Figure 3. Channel 0 Through Channel 3 Datapath Block Detail (I and Q Paths Are Identical So Only One Is Shown)

DAC

CH GAIN 0× TO 2×

07852-003

Rev. A | Page 3 of 76

AD9789

SPECIFICATIONS

DC SPECIFICATIONS

AVDD33 = DVDD33 = 3.3 V, CVDD18 = DVDD18 = 1.8 V, DVDD15 = 1.5 V, f

Table 1.

Parameter Min Typ Max Unit

DAC RESOLUTION 14 Bits ANALOG OUTPUTS

Offset Error 6.5 % FSR Gain Error (with Internal Reference) 3.5 % FSR Full-Scale Output Current (Monotonicity Guaranteed) 8.66 20.2 31.66 mA Output Compliance Range −1.0 +1.0 V Output Resistance 70 Ω Output Capacitance 1 pF

TEMPERATURE DRIFT

Gain 135 ppm/°C Reference Voltage 25 ppm/°C

REFERENCE

Internal Reference Voltage 1.2 V Output Resistance1 5 kΩ

ANALOG SUPPLY VOLTAGES

AVDD33 3.14 3.3 3.47 V CVDD18 1.71 1.8 1.89 V

DIGITAL SUPPLY VOLTAGES

DVDD33 3.14 3.3 3.47 V DVDD18 1.71 1.8 1.89 V DVDD15 1.43 1.5 1.58 V

SUPPLY CURRENTS AND POWER DISSIPATION

f

= 2.4 GSPS, f

DAC

I

45 mA

AVDD33

I

72 mA

DVDD18

I

180 mA

CVDD18

I

DVDD33

= 930 MHz, IFS = 25 mA, Four Channels Enabled

OUT

CMOS Interface 42 mA LVDS Interface 16 mA

I

640 mA

DVDD15

f

= 2.0 GSPS, f

DAC

I

37.4 38.5 mA

AVDD33

I

67.3 70.5 mA

DVDD18

I

155.4 180 mA

CVDD18

I

40.3 50.7 mA

DVDD33

I

(Four Channels Enabled, All Signal Processing Enabled) 517 556 mA

DVDD15

I

(One Channel Enabled, 16× Interpolation Only) 365 391 mA

DVDD15

= 70 MHz, IFS = 20 mA, CMOS Interface

OUT

Power Dissipation

f

= 2.4 GSPS, f

DAC

= 930 MHz, IFS = 25 mA, Four Channels Enabled

OUT

CMOS Interface 1.7 W LVDS Interface 1.63 W

1

Use an external amplifier to drive any external load.

= 2.4 GHz, IFS = 20 mA, unless otherwise noted.

DAC

Rev. A | Page 4 of 76

AD9789

DIGITAL SPECIFICATIONS

AVDD33 = DVDD33 = 3.3 V, CVDD18 = DVDD18 = 1.8 V, DVDD15 = 1.5 V, f are compliant with the IEEE Std 1596.3-1996 reduced range link, unless otherwise noted.

Table 2.

Parameter Min Typ Max Unit

CMOS DATA INPUTS (D[31:0], P0, P1)

Input Voltage High, VIH 2.0 3.3 V Input Voltage Low, VIL 0 0.8 V Input Current High, IIH −10 +10 µA Input Current Low, IIL −10 +10 µA Input Capacitance 2 pF Setup Time, CMOS Data Input to CMOS_DCO1 5.3 ns Hold Time, CMOS Data Input to CMOS_DCO1 −1.4 ns

CMOS OUTPUTS (CMOS_FS, CMOS_DCO)

Output Voltage High, VOH 2.4 3.3 V Output Voltage Low, VOL 0 0.4 V Output Current High, IOH 12 mA Output Current Low, IOL 12 mA Maximum Clock Rate (CMOS_DCO) 150 MHz CMOS_DCO to CMOS_FS Delay 0.28 0.85 ns

LVDS DATA INPUTS (D[15:0]P, D[15:0]N, PARP, PARN)

Input Voltage Range, VIA or VIB 825 1575 mV Input Differential Threshold, V Input Differential Hysteresis, V

−100 +100 mV

IDTH

, V

IDTHH

25 mV

IDTHL

Input Differential Input Impedance, RIN 80 120 Ω Maximum LVDS Input Rate 150 MSPS Setup Time, LVDS Differential Input Data to Differential DCOx2 1.41 ns Hold Time, LVDS Differential Input Data to Differential DCOx2 0.24 ns

LVDS OUTPUTS (DCOP, DCON, FSP, FSN)

DCOP, FSP = V

; DCON, FSN = VOB; 100 Ω Termination

OA

Output Voltage High, VOA or VOB 1375 mV Output Voltage Low, VOA or VOB 1025 mV Output Differential Voltage, |VOD| 150 200 250 mV Output Offset Voltage, VOS 1150 1250 mV Output Impedance, Single Ended, RO 40 140 Ω RO Mismatch Between A and B, RO 10 % Change in |VOD| Between 0 and 1, |VOD| 25 mV Change in VOS Between 0 and 1, VOS 25 mV Output Current—Driver Shorted to Ground, ISA, ISB 20 mA Output Current—Drivers Shorted Together, I

4 mA

SAB

Power-Off Output Leakage, |IXA|, |IXB| 10 mA Maximum Clock Rate (DCOP, DCON) 150 MHz DCOx to FSx Delay 0.12 0.37 ns

DAC CLOCK INPUT (CLKP, CLKN)3

Differential Peak Voltage 1.4 1.8 V Common-Mode Voltage 900 mV DAC Clock Rate 2400 MHz

SERIAL PERIPHERAL INTERFACE

Maximum Clock Rate (f Minimum Pulse Width High, t Minimum Pulse Width Low, t Minimum SDIO and CS to SCLK Setup, tDS

SCLK

, 1/t

) 25 MHz

SCLK

20 ns

PWH

20 ns

PWL

10 ns

= 2.4 GHz, IFS = 20 mA, LVDS drivers and receivers

DAC

Rev. A | Page 5 of 76

AD9789

Parameter Min Typ Max Unit

Minimum SCLK to SDIO Hold, tDH 5 ns Maximum SCLK to Valid SDIO and SDO, tDV 20 ns Minimum SCLK to Invalid SDIO and SDO, t

INPUTS (SDIO, SCLK, CS)

Input Voltage High, VIH 2.0 3.3 V Input Voltage Low, VIL 0 0.8 V Input Current High, IIH −10 +10 µA Input Current Low, IIL −10 +10 µA

OUTPUTS (SDO, SDIO)

Output Voltage High, VOH 2.4 3.6 V Output Voltage Low, VOL 0 0.4 V Output Current High, IOH 4 mA Output Current Low, IOL 4 mA

1

See the CMOS Interface Timing section for more information.

2

See the LVDS Interface Timing section for more information.

3

See the Clock Phase Noise Effects on AC Performance section for more information.

AC SPECIFICATIONS

AVDD33 = DVDD33 = 3.3 V, CVDD18 = DVDD18 = 1.8 V, DVDD15 = 1.5 V, f otherwise noted.

5 ns

DNV

= 2.4 GHz, IFS = 20 mA, digital scale = 0 dBFS, unless

DAC

Table 3.

Parameter Test Conditions/Comments Min Typ Max Unit

DYNAMIC PERFORMANCE

DAC Update Rate 2400 MSPS Adjusted DAC Update Rate1 150 MSPS Output Settling Time (tST) To 0.025% 13 ns

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

f

= 2000 MSPS

DAC

f

= 100 MHz 70 dBc

OUT

f

= 316 MHz 63 dBc

OUT

f

= 550 MHz 58 dBc

OUT

f

= 2400 MSPS

DAC

f

= 100 MHz 70 dBc

OUT

f

= 316 MHz 70 dBc

OUT

f

= 550 MHz 60 dBc

OUT

f

= 850 MHz 60 dBc

OUT

= f

TWO-TONE INTERMODULATION DISTORTION

f

OUT2

+ 1.25 MHz

OUT1

(IMD) f

= 2000 MSPS

DAC

f

= 100 MHz 86 dBc

OUT

f

= 316 MHz 73 dBc

OUT

f

= 550 MHz 62 dBc

OUT

f

= 2400 MSPS

DAC

f

= 100 MHz 86 dBc

OUT

f

= 316 MHz 74 dBc

OUT

f

= 550 MHz 66 dBc

OUT

f

= 850 MHz 66 dBc

OUT

NOISE SPECTRAL DENSITY (NSD)

1-Channel QAM f

f

= 100 MHz P

OUT

f

= 316 MHz P

OUT

f

= 550 MHz P

OUT

f

= 850 MHz P

OUT

= 2400 MSPS

DAC

= −14.5 dBm −167 dBm/Hz

OUT

= −15.5 dBm −166.5 dBm/Hz

OUT

= −18 dBm −166.5 dBm/Hz

OUT

= −18.5 dBm −166.5 dBm/Hz

OUT

Rev. A | Page 6 of 76

AD9789

Parameter Test Conditions/Comments Min Typ Max Unit

ADJACENT CHANNEL LEAKAGE RATIO (ACLR)

= 2293.76 MSPS measured in 6 MHz

f

DAC

channels

1-Channel QAM

f

= 200 MHz (Harmonics) −76 dBc

OUT

f

= 200 MHz (Noise Floor) −82 dBc

OUT

f

= 500 MHz (Harmonics) −74.5 dBc

OUT

f

= 500 MHz (Noise Floor) −78 dBc

OUT

f

= 800 MHz (Harmonics) −69 dBc

OUT

f

= 800 MHz (Noise Floor) −78 dBc

OUT

2-Channel QAM

f

= 200 MHz (Harmonics) −77.5 dBc

OUT

f

= 200 MHz (Noise Floor) −81 dBc

OUT

f

= 500 MHz (Harmonics) −68 dBc

OUT

f

= 500 MHz (Noise Floor) −76 dBc

OUT

f

= 800 MHz (Harmonics) −66 dBc

OUT

f

= 800 MHz (Noise Floor) −76 dBc

OUT

4-Channel QAM

f

= 200 MHz (Harmonics) −75 dBc

OUT

f

= 200 MHz (Noise Floor) −76 dBc

OUT

f

= 500 MHz (Harmonics) −69 dBc

OUT

f

= 500 MHz (Noise Floor) −72 dBc

OUT

f

= 800 MHz (Harmonics) −67 dBc

OUT

f

= 800 MHz (Noise Floor) −72 dBc

OUT

WCDMA ACLR

= 2304 MSPS, mix mode second

f

DAC

Nyquist zone

Single Carrier f

= 1850 MHz

OUT

First Adjacent Channel −70 dBc Second Alternate Channel −72.5 dBc Third Alternate Channel −74 dBc

Single Carrier f

= 2100 MHz

OUT

First Adjacent Channel −68 dBc Second Alternate Channel −70.4 dBc Third Alternate Channel −72.7 dBc

Four Carrier f

= 2100 MHz

OUT

First Adjacent Channel −63.5 dBc Second Alternate Channel −65.1 dBc Third Alternate Channel −66.9 dBc

1

Adjusted DAC update rate is calculated as f

with f

= 2400 MSPS, F

DAC

= 2400 MSPS/16 = 150 MSPS.

DACadj

divided by the minimum required interpolation factor. For the AD9789, the minimum interpolation factor is 16. Thus,

DAC

Rev. A | Page 7 of 76

AD9789

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

AVDD33 to AVSS −0.3 V to +3.6 V DVDD18 to DVSS −0.3 V to +1.98 V DVDD33 to DVSS −0.3 V to +3.6 V DVDD15 to DVSS −0.3 V to +1.98 V CVDD18 to AVSS −0.3 V to +1.98 V AVSS to DVSS −0.3 V to +0.3 V CLKP, CLKN to AVSS −0.3 V to CVDD18 + 0.3 V FS, DCO to DVSS −0.3 V to DVDD33 + 0.3 V CMOS and LVDS Data Inputs

to DVSS IOUTN, IOUTP to AVSS −1.0 V to AVDD33 + 0.3 V I120, VREF, IPTAT to AVSS −0.3 V to AVDD33 + 0.3 V IRQ, CS, SCLK, SDO, SDIO, RESET

to DVSS Junction Temperature 150°C Storage Temperature Range −65°C to +150°C

−0.3 V to DVDD33 + 0.3 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 5. Thermal Resistance

Package Typ e

164-Ball CSP_BGA

θJB θJC Unit Notes

θ

JA

25.5 14.4 6.8 °C/W 4-layer board, no vias

24.4 °C/W 4-layer board, 4 PCB vias

19.0 °C/W 8-layer board, 4 PCB vias

17.2 °C/W 8-layer board, 16 PCB vias

ESD CAUTION

Rev. A | Page 8 of 76

AD9789

A

V

S

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

111312111089765243 4

A

B

C

D

E

F

G

++++ ++

H

J

K

XXXX

SB

NC

CS L

NC

CK

NC

DO

R

IO

I

RESET IRQ

NC

NCNCNC

NC

DVSSNO CONNECT DVDD15DVDD33

X

++++

XXXX

+

07852-006

Figure 6. Digital Supply and SPI Pins (Top View)

CLKN C

CLKP D

CVDD18

111312111089765243 4

A

B

N

P

E

F

G

H

J

K

L

M

N

P

+

–

++

+

DVDD18

X

AVS S DV DD18CVDD18 AVDD33

DD33IOUTN IOUTP

XX

NC

I120

VREF

IPTAT

CLK M

SDO N

SDIO P

07852-004

Figure 4. Clock and Analog Pins (Top View)

111312111089765243 4

A

B

C

D

E

F

G

H

J

K

P1

L

M

N

P

31 27 23 19 15 11 7 3

P0

30 26 22 18 14 10 6 2

29 25 21 17 13 9 5 1

28 24 20 16 12 8 4 0

D[31:0] CMOS D ATA INPUTS

PARITY AND CONTROL INPUTS

BU

CT

FS

DC

CMOS_BUS

CMOS_CTRL

CMOS_FS

CMOS_DCO

07852-005

PAR P

PARN

Figure 5. CMOS Mode Data Input Pins (Top View)

111312111089765243 4

A

B

C

D

E

F

G

H

J

K

P+

L

M

N

P

13 11 9

15

P–

15 13 11 9

14 12 10 8 6 4 2 0

14 14

+LVDS

7

–LVDS

531

FS

DC

FSP

FSN

DCOP

DCON

07852-007

Figure 7. LVDS Mode Data Input Pins (Top View)

Rev. A | Page 9 of 76

AD9789

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

A1, A2, A3, A6, A9, A10, A11, B1, B2, B3, B6, B7, B8, B9, B10, B11, C2, C3, C6, C7, C8, C9, C10, C11, D2, D3, D6, D7, D8, D9, D10, D11, E1, E2, E3, E4, E13, E14, F1, F2, F3, F4, F11, F12, F13, F14

A4, A5, B4, B5, C4, C5, D4, D5 CVDD18 1.8 V Clock Supply. A7 IOUTN DAC Negative Output Current. A8 IOUTP DAC Positive Output Current. A12, A13, B12, B13, C12, C13,

D12, D13 A14 NC No Connect. Leave floating. B14 I120 Tie this pin to analog ground with a 10 kΩ resistor to generate a 120 µA reference current. C1 CLKN Negative DAC Clock Input (DACCLK). C14 VREF

D1 CLKP Positive DAC Clock Input (DACCLK). D14 IPTAT

E11, E12 DVDD18 1.8 V Digital Supply. G1, G2, G3, G4, G7, G8, G11,

G12, G13, G14 H1, H2, H3, H4, H7, H8, H11,

H12, H13, H14, J1, J2, J3, J4, J11, J12, J13, J14

K1, K2, K3, K4, K11, K12, K13, K14

L1 L2, L3, M2, M3, N3, N4, P3, P4 NC Not Used. Leave unconnected.

L4 P1/PARP CMOS/LVDS Parity Bit. L5 D31/D15P CMOS/LVDS Data Input. L6 D27/D13P CMOS/LVDS Data Input. L7 D23/D11P CMOS/LVDS Data Input. L8 D19/D9P CMOS/LVDS Data Input. L9 D15/D7P CMOS/LVDS Data Input. L10 D11/D5P CMOS/LVDS Data Input. L11 D7/D3P CMOS/LVDS Data Input. L12 D3/D1P CMOS/LVDS Data Input. L13 FSP Positive LVDS Frame Sync (FSP) for Data Bus. L14 CMOS_BUS

M1 SCLK Qualifying Clock for SPI. M4 P0/PARN CMOS/LVDS Parity Bit. M5 D30/D15N CMOS/LVDS Data Input. M6 D26/D13N CMOS/LVDS Data Input. M7 D22/D11N CMOS/LVDS Data Input. M8 D18/D9N CMOS/LVDS Data Input. M9 D14/D7N CMOS/LVDS Data Input. M10 D10/D5N CMOS/LVDS Data Input. M11 D6/D3N CMOS/LVDS Data Input. M12 D2/D1N CMOS/LVDS Data Input. M13 FSN Negative LVDS Frame Sync (FSN) for Data Bus.

AVSS Analog Supply Ground.

AVDD33 3.3 V Analog Supply.

Band Gap Voltage Reference I/O. Decouple to analog ground with a 1 nF capacitor. Output impedance is approximately 5 kΩ.

Factory Test Pin. Output current, proportional to absolute temperature, is approximately 10 µA at 25°C with a slope of approximately 20 nA/°C.

DVDD15 1.5 V Digital Supply.

DVSS Digital Supply Ground.

DVDD33 3.3 V Digital Supply.

CS

Active Low Chip Select for SPI.

Active High Input. Configures data bus for CMOS inputs. Low input configures data bus to accept LVDS inputs.

Rev. A | Page 10 of 76

AD9789

Pin No. Mnemonic Description

M14 CMOS_CTRL

N1 SDO Serial Data Output for SPI. N2 RESET Active High Input. Resets the AD9789. N5 D29/D14P CMOS/LVDS Data Input. N6 D25/D12P CMOS/LVDS Data Input. N7 D21/D10P CMOS/LVDS Data Input. N8 D17/D8P CMOS/LVDS Data Input. N9 D13/D6P CMOS/LVDS Data Input. N10 D9/D4P CMOS/LVDS Data Input. N11 D5/D2P CMOS/LVDS Data Input. N12 D1/D0P CMOS/LVDS Data Input. N13 DCOP Positive LVDS Data Clock Output (DCOP) for Data Bus. N14 CMOS_FS CMOS Frame Sync for Data Bus. P1 SDIO Serial Data Input/Output for SPI. P2 IRQ

P5 D28/D14N CMOS/LVDS Data Input. P6 D24/D12N CMOS/LVDS Data Input. P7 D20/D10N CMOS/LVDS Data Input. P8 D16/D8N CMOS/LVDS Data Input. P9 D12/D6N CMOS/LVDS Data Input. P10 D8/D4N CMOS/LVDS Data Input. P11 D4/D2N CMOS/LVDS Data Input. P12 D0/D0N CMOS/LVDS Data Input. P13 DCON Negative LVDS Data Clock Output (DCON) for Data Bus. P14 CMOS_DCO CMOS Data Clock Output for Data Bus.

Active High Input. Enables CMOS_DCO and CMOS_FS signals and disables DCOP/DCON and FSP/FSN signals. Low input disables CMOS_DCO and CMOS_FS signals and enables DCOP/DCON and FSP/FSN signals.

Active Low, Open-Drain Interrupt Request Output. Pull up to DVDD33 with a 10 kΩ resistor.

Rev. A | Page 11 of 76

AD9789

–

TYPICAL PERFORMANCE CHARACTERISTICS

40

–45

–50

–55

–60

–65

–70

SFDR (dBc)

–75

–80

–85

–90

0 200 400 600 800 1000 1200

Figure 8. SFDR vs. f

OUT

f

(MHz)

OUT

over f

, Full-Scale Current = 20 mA,

DAC

2.4GHz

2.2GHz 2GHz

1.6GHz 1GHz

Digital Scale = 0 dBFS, Temperature = 25°C

07852-013

40

–45

–50

–55

–60

–65

–70

SFDR (dBc)

–75

–80

–85

–90

0 200 400 600 800 1000 1200

Figure 11. SFDR vs. f

f

(MHz)

OUT

over Digital Full Scale, f

OUT

0dBFS –3dBFS –6dBFS –12dBFS

= 2.4 GHz,

DAC

Full-Scale Current = 20 mA, Temperature = 25°C

07852-010

40

–45

–50

–55

–60

–65

–70

–75

HARMONIC LEVEL (dBc)

–80

–85

–90

0 200 400 600 800 1000 1200

Figure 9. Second-Order Harmonic vs. f

= 2.4 GHz, Full-Scale Current = 20 mA, Temperature = 25°C

f

DAC

40

–45

–50

–55

–60

–65

–70

SFDR (dBc)

–75

–80

–85

–90

0 200 400 600 800 1000 1200

Figure 10. SFDR vs. f

f

(MHz)

OUT

over Digital Full Scale,

OUT

f

(MHz)

OUT

over Full-Scale Current, f

OUT

0dBFS –3dBFS –6dBFS –12dBFS

32mA 20mA 8mA

DAC

Digital Scale = 0 dBFS, Temperature = 25°C

= 2.4 GHz,

40

–45

–50

–55

–60

–65

–70

–75

HARMONIC LEVEL (dBc)

–80

–85

–90

07852-009

0 200 400 600 800 1000 1200

Figure 12. Third-Order Harmonic vs. f

= 2.4 GHz, Full-Scale Current = 20 mA, Temperature = 25°C

f

DAC

50

–55

–60

–65

–70

–75

–80

SFDR (dBc)

–85

–90

–95

–100

07852-011

0 200 400 600 800 1000 1200

Figure 13. SFDR vs. f

f

(MHz)

OUT

f

(MHz)

OUT

over Temperature, f

OUT

over Digital Full Scale,

0dBFS –3dBFS –6dBFS –12dBFS

+85°C +25°C –40°C

= 2.4 GHz,

DAC

07852-012

07852-008

Full-Scale Current = 20 mA, Digital Scale = 0 dBFS

Rev. A | Page 12 of 76

AD9789

–

90

100

80

70

60

IMD (dBc)

50

40

30

0 100 200 300 400 500 600 700 800 900 1000 1100

Figure 14. Third-Order IMD vs. f

f

OUT

(MHz)

over f

, Full-Scale Current = 20 mA,

DAC

Digital Scale = 0 dBFS, Temperature = 25°C

100

90

80

70

60

IMD (dBc)

50

40

30

0 100 200 300 400 500 600 700 800 900 1000 1100

Figure 15. Third-Order IMD vs. f

f

(MHz)

OUT

over Full-Scale Current, f

OUT

Digital Scale = 0 dBFS, Temperature = 25°C

2.4GHz

2.0GHz

1.6GHz

1.0GHz

32mA 20mA 8mA

DAC

07852-034

07852-038

= 2.4 GHz,

90

80

70

60

IMD (dBc)

50

40

30

0 100 200 300 400 500 600 700 800 900 1000 1100

Figure 17. Third-Order IMD vs. f

f

(MHz)

OUT

over Digital Full Scale, f

OUT

Full-Scale Current = 20 mA, Temperature = 25°C

90

80

70

60

IMD (dBc)

50

40

30

0 100 200 300 400 500 600 700 800 900 1000 1100

Figure 18. Third-Order IMD vs. f

f

(MHz)

OUT

over Temperature, f

OUT

Full-Scale Current = 20 mA, Digital Scale = 0 dBFS

0dBFS –3dBFS –6dBFS –12dBFS

DAC

+85°C +25°C –40°C

= 2.4 GHz,

DAC

07852-037

= 2.4 GHz,

07852-041

155

–157

–159

–161

–163

–165

–167

NSD (dBm/Hz)

–169

–171

–173

–175

0 200 400 600 800 1000 1200

Figure 16. NSD vs. f

OUT

f

(MHz)

OUT

over f

, 1-Channel QAM, Full-Scale Current = 20 mA

DAC

2.4GHz

2.0GHz

1.6GHz

07852-016

155

–157

–159

–161

–163

–165

–167

NSD (dBm/Hz)

–169

–171

–173

–175

0 200 400 600 800 1000 1200

Figure 19. NSD vs. f

over Temperature, 1-Channel QAM, f

OUT

f

OUT

(MHz)

+85°C +25°C –40°C

= 2.4 GHz,

DAC

07852-019

Full-Scale Current = 20 mA

Rev. A | Page 13 of 76

AD9789

–

–15

–25

–35

–5

DOCSIS3 –40°C 0°C +25°C +85°C

–15

–25

–35

–5

DOCSIS3 –40°C 0°C +25°C +85°C

–45

ACLR (dB c)

–55

–65

–75

–85

50 250 450 650 850

FREQUENCY (MHz)

Figure 20. ACLR Performance over Temperature, 1-Channel QAM,

= 2.3 GHz, Full-Scale Current = 20 mA, f

f

DAC

= 200 MHz, Sum Scale = 48

OUT

(DOCSIS SPEC Is −73 dBc; Harmonic Exception Is −63 dBc)

55

–60

–65

–70

–75

HARMONIC LEVEL (dBc)

–80

–85

0 100 200 300 400 500 600 700 800 900 1000

f

(MHz)

OUT

Figure 21. Second-Order Harmonic Performance vs. f 1-Channel QAM, f

= 2.3 GHz, Full-Scale Current = 20 mA, Sum Scale = 48

DAC

DOCSIS3 25°C 65°C 85°C

over Temperature,

OUT

(DOCSIS SPEC Is −73 dBc; Harmonic Exception Is −63 dBc)

55

–60

–65

–70

ACLR (d Bc)

–75

–80

–85

0 100 200 300 400 500 600 700 800 900 1000

Figure 22. Noise Floor vs. f

1-Channel QAM, f

= 2.3 GHz, Full-Scale Current = 20 mA, Sum Scale = 48

DAC

OUT

f

(MHz)

OUT

over Temperature (ACLR Measured Beyond 30 MHz),

(DOCSIS SPEC Is −73 dBc)

DOCSIS3 25°C 65°C 85°C

–45

ACLR (dB c)

–55

–65

–75

–85

50 150 250 350 450 550 650 750 850 950

07852-015

FREQUENCY (MHz)

07852-018

Figure 23. ACLR Performance over Temperature, 1-Channel QAM,

= 2.3 GHz, Full-Scale Current = 20 mA, f

f

DAC

= 800 MHz, Sum Scale = 48

OUT

(DOCSIS SPEC Is −73 dBc)

55

–60

–65

–70

–75

HARMONIC LEVEL (dBc)

–80

–85

0 100 200 300 400 500 600 700 800 900 1000

07852-014

f

(MHz)

OUT

Figure 24. Third-Order Harmonic Performance vs. f

1-Channel QAM, f

= 2.3 GHz, Full-Scale Current = 20 mA, Sum Scale = 48

DAC

DOCSIS3 25°C 65°C 85°C

over Temperature,

OUT

07852-017

(DOCSIS SPEC Is −73 dBc; Harmonic Exception Is −63 dBc)

–5

DOCSIS 3

–15

–25

–35

–45

ACLR (dB c)

–55

–65

–75

–85

07852-031

Figure 25. ACLR Performance over f

2.3GHz

2.2GHz

2.4GHz

50 250 450 650 850 1050

FREQUENCY (MHz)

, 1-Channel QAM, f

DAC

= 850 MHz,

OUT

07852-039

Full-Scale Current = 20 mA, Temperature = 25°C, Sum Scale = 48

(DOCSIS SPEC Is −73 dBc)

Rev. A | Page 14 of 76

AD9789

–

0

DOCSIS3 CMOS LVD S

0 100 200 300 400 500 600 700 800 900 1000

FREQUENCY ( MHz)

07852-040

ACLR (dBc)

–10

–20

–30

–40

–50

–60

–70

–80

–90

Figure 26. ACLR Performance for CMOS and LVDS Interfaces, 1-Channel QAM,

= 840 MHz, f

f

OUT

= 2.4 GHz, Full-Scale Current = 20 mA, Sum Scale = 48

DAC

(DOCSIS SPEC Is −73 dBc)

–5

–15

–25

–35

–45

ACLR (dB c)

–55

–65

–75

–85

DOCSIS3 25°C 65°C 85°C

50 250 450 650 850 1050

FREQUENCY (MHz)

07852-042

Figure 27. ACLR Performance over Temperature, 2-Channel QAM,

f

= 800 MHz, f

OUT

= 2.3 GHz, Full-Scale Current = 25 mA, Sum Scale = 32

DAC

(DOCSIS SPEC Is −70 dBc)

55

–60

–65

–5

–15

–25

–35

–45

ACLR (dB c)

–55

–65

–75

–85

50 250 450 650 850 1050

FREQUENCY (MHz)

DOCSIS3 25°C 65°C 85°C

07852-044

Figure 29. ACLR Performance over Temperature, 2-Channel QAM,

= 200 MHz, f

f

OUT

= 2.3 GHz, Full-Scale Current = 25 mA, Sum Scale = 32

DAC

(DOCSIS SPEC Is −70 dBc; Harmonic Exception Is −63 dBc)

55

–60

–65

–70

–75

HARMONIC LEVEL (dBc)

–80

–85

0 100 200 300 400 500 600 700 800 900 1000

f

OUT

(MHz)

Figure 30. Second Harmonic Performance vs. f

2-Channel QAM, f

= 2.3 GHz, Full-Scale Current = 25 mA, Sum Scale = 32

DAC

DOCSIS3 25°C 65°C 85°C

over Temperature,

OUT

07852-045

(DOCSIS SPEC Is −70 dBc; Harmonic Exception Is −63 dBc)

55

DOCSIS3

–60

–65

25°C 65°C 85°C

–70

–75

HARMONIC LEVEL (dBc)

–80

–85

0 100 200 300 400 500 600 700 800 900 1000

f

OUT

(MHz)

Figure 28. Third-Order Harmonic Performance vs. f

2-Channel QAM, f

= 2.3 GHz, Full-Scale Current = 25 mA, Sum Scale = 32

DAC

(DOCSIS SPEC Is −70 dBc; Harmonic Exception Is −63 dBc)

DOCSIS3 25°C 65°C 85°C

over Temperature,

OUT

07852-043

–70

ACLR (d Bc)

–75

–80

–85

0 100 200 300 400 500 600 700 800 900 1000

Figure 31. Noise Floor vs. f

2-Channel QAM, f

= 2.3 GHz, Full-Scale Current = 25 mA, Sum Scale = 32

DAC

f

(MHz)

OUT

over Temperature (ACLR Measured Beyond 30 MHz),

OUT

(DOCSIS SPEC Is −70 dBc)

07852-046

Rev. A | Page 15 of 76

AD9789

–

0

–10

–20

–30

–40

ACLR (dBc)

–50

–60

–70

–80

50 250 450 650 850 1050

FREQUENCY ( MHz)

DOCSIS3 –40°C 0°C +25°C +85°C

Figure 32. ACLR Performance over Temperature, 4-Channel QAM,

= 200 MHz, f

f

OUT

= 2.3 GHz, Full-Scale Current = 25 mA, Sum Scale = 20

DAC

(DOCSIS SPEC Is −67 dBc; Harmonic Exception Is −63 dBc)

55

–60

–65

–70

0

–10

–20

–30

–40

ACLR (dBc)

–50

–60

–70

–80

50 250 450 650 850 1050

07852-027

DOCSIS3 –40°C 0°C +25°C +85°C

FREQUENCY (MHz )

07852-030

Figure 35. ACLR Performance over Temperature, 4-Channel QAM,

= 800 MHz, f

f

OUT

= 2.3 GHz, Full-Scale Current = 25 mA, Sum Scale = 20

DAC

(DOCSIS SPEC Is −67 dBc)

55

–60

–65

–70

–75

HARMONIC LEVEL (dBc)

–80

–85

0 100 200 300 400 500 600 700 800 900 1000

f

(MHz)

OUT

Figure 33. Second-Order Harmonic Performance vs. f 4-Channel QAM, f

= 2.3 GHz, Full-Scale Current = 25 mA, Sum Scale = 20

DAC

(DOCSIS SPEC Is −67 dBc; Harmonic Exception Is −63 dBc)

55

–60

–65

–70

ACLR (d Bc)

–75

–80

–85

0 100 200 300 400 500 600 700 800 900 1000

Figure 34. Noise Floor vs. f

4-Channel QAM, f

= 2.3 GHz, Full-Scale Current = 25 mA, Sum Scale = 20

DAC

OUT

f

(MHz)

OUT

over Temperature (ACLR Measured Beyond 30 MHz),

(DOCSIS SPEC Is −67 dBc)

DOCSIS3 25°C 65°C 85°C

over Temperature,

OUT

DOCSIS3 25°C 65°C 85°C

–75

HARMONIC LEVEL (dBc)

–80

–85

0 100 200 300 400 500 600 700 800 900 1000

07852-026

f

(MHz)

OUT

Figure 36. Third-Order Harmonic Performance vs. f

4-Channel QAM, f

= 2.3 GHz, Full-Scale Current = 25 mA, Sum Scale = 20

DAC

DOCSIS 3 25°C 65°C 85°C

over Temperature,

OUT

07852-029

(DOCSIS SPEC Is −67 dBc; Harmonic Exception Is −63 dBc)

0

DOCSIS3

–10

–20

–30

–40

ACLR (dBc)

–50

–60

–70

–80

07852-028

Figure 37. ACLR Performance over f

2.3GHz

2.2GHz

2.4GHz

50 250 450 650 850 1050

FREQUENCY (MHz )

, 4-Channel QAM, f

DAC

= 850 MHz,

OUT

07852-047

Full-Scale Current = 25 mA, Temperature = 25°C, Sum Scale = 20

(DOCSIS SPEC Is −67 dBc)

Rev. A | Page 16 of 76

AD9789

A

m

A

m

A

m

A

m

TTEN 2dBRE F –32.76dB

CENTER 840.00MHz RES BW 56kHz VBW 560kHz

FREQ. LOWER UPPER RMS RESULTS CARRIER POWER –18.10dBm/

6.00000MHz

OFFSET REF BW dBc dBm dBc dBm

3.375MHz 750.0kHz –65.57 –83.66 –68. 98 –87.07

6.375MHz 5.250M Hz –75.01 –93. 11 –74.62 –92.71

12.00MHz 6.000M Hz –76.83 –94.92 –76.46 –94.55

18.00MHz 6.000M Hz –77.17 –95.26 –76.56 –94.66

Figure 38. 1-Channel QAM ACLR, f

SWEEP 39. 12ms (601 PTS)

= 840 MHz, Temperature = 25°C,

OUT

SPAN 42MHz

Sum Scale = 48, Full-Scale Current = 20 mA, Span = 42 MHz

TTEN 2dBRE F –35.91dB

CENTER 840.00MHz RES BW 30kHz VBW 300kHz

FREQ. LOWER UPPER RMS RESULTS CARRIER POWER –21.75dBm/

6.00000MHz

OFFSET REF BW dBc dBm dBc dBm

3.375MHz 750.0kHz –71.64 –93.39 –72. 50 –94.25

6.375MHz 5.250M Hz –73.71 –95.47 –66.72 –88.47

12.00MHz 6.000M Hz –73.58 –95.33 0.50 –21.10

18.00MHz 6.000M Hz –73.70 –95.45 –66.72 –88.48

Figure 39. 2-Channel QAM ACLR, f

SWEEP 136. 2ms (601 PTS)

= 840 MHz, Sum Scale = 32,

OUT

SPAN 42MHz

Full-Scale Current = 25 mA, Span = 42 MHz, Channel 1

CENTER 840.00MHz RES BW 30kHz VBW 300kHz

FREQ. LOWER UPPER

RMS RESULTS CARRIER POWER

–17.98dBm/

07852-020

6.00000MHz

OFFSET REF BW dBc dBm dBc dBm

3.375MHz 750.0kHz –73.99 –91.97 –74. 93 –92.91

6.375MHz 5.250M Hz –74.94 –92.92 –75.35 –93.33

Figure 40. 1-Channel QAM ACLR, f

SWEEP 58.4ms (601 PTS)

= 840 MHz, Temperature = 25°C,

OUT

SPAN 18MHz

7852-023

Sum Scale = 48, Full-Scale Current = 20 mA, Span = 18 MHz

TTEN 2dBRE F –35.91dB

START 831.00M Hz RES BW 30kHz VBW 300kHz

FREQ. LOWER UPPER RMS RESULTS CARRIER POWER –21.29dBm/

07852-061

6.00000MHz

OFFSET REF BW dBc dBm dBc dBm

3.375MHz 750.0kHz –70.07 –92.16 –73. 20 –94.49

6.375MHz 5.250M Hz –69.05 –90.34 –73.87 –95.16

12.00MHz 6.000M Hz –0.49 –21.78 –73.29 –94.58

18.00MHz 6.000M Hz –66.61 –87.90 –73.98 –95.27

Figure 41. 2-Channel QAM ACLR, f

SWEEP 136. 2ms (601 PTS)

= 840 MHz, Sum Scale = 32,

OUT

STOP 873MHz

07852-066

Full-Scale Current = 25 mA, Span = 42 MHz, Channel 2

Rev. A | Page 17 of 76

AD9789

A

m

A

m

A

m

A

TTEN 2dBRE F –35.91dB

CENTER 840.00MHz RES BW 30kHz VBW 300kHz

FREQ. LOWER UPPER RMS RESULTS CARRIER POWER –21.56dBm/

6.00000MHz

OFFSET REF BW dBc dBm dBc dBm

3.375MHz 750.0kHz –75.37 –96.93 –75. 56 –97. 11

6.375MHz 5.250M Hz –73.85 –95.41 –72.54 –94.10

Figure 42. Zoomed 2-Channel QAM ACLR, f

SWEEP 58.4ms (601 PTS)

OUT

SPAN 18MHz

= 840 MHz, Sum Scale = 32,

Full-Scale Current = 25 mA, Span = 18 MHz, Channel 1

TTEN 2dBRE F –35.96dB

CENTER 834.00MHz RES BW 30kHz

RMS RESULTS CARRIER POWER –23.63dBm/

6.00000MHz

VBW 300kHz

FREQ. LOWER UPPER

OFFSET REF BW dBc dBm dBc dBm

3.375MHz 750.0kHz –70.33 –93.96 – 11.07 –34.70

6.375MHz 5.250MHz –69.04 –92.67 –0.49 –24.12

12.00MHz 6.000MHz –70.38 –94.01 0.00 –23.63

18.00MHz 6.000MHz –71.02 –94.65 0.43 –23.20

Figure 43. 4-Channel QAM ACLR, f

SWEEP 136.2ms (601 PTS)

= 840 MHz, Temperature = 25°C,

OUT

SPAN 42MHz

Sum Scale = 20, Full-Scale Current = 25 mA, Span = 42 MHz, Channel 1

CENTER 852.00MHz RES BW 30kHz VBW 300kHz

FREQ. LOWER UPPER RMS RESULTS CARRIER POWER –21.03dBm/

07852-065

6.00000MHz

OFFSET REF BW dBc dBm dBc dBm

3.375MHz 750.0kHz –75.51 –96.54 –75. 17 –96.20

6.375MHz 5.250M Hz –72.55 –93.58 –73.90 –94.93

Figure 44. Zoomed 2-Channel QAM ACLR, f

SWEEP 58.4ms (601 PTS)

OUT

SPAN 18MHz

07852-067

= 840 MHz, Sum Scale = 32,

Full-Scale Current = 25 mA, Span = 18 MHz, Channel 2

TTEN 2dBREF –35.96dBm

CENTER 852.00MHz RES BW 30kHz

RMS RESULTS CARRIER POWER –23.23dBm/

07852-021

6.00000MHz

Figure 45. 4-Channel QAM ACLR, f

VBW 300kHz

FREQ. LOWER UPPER

OFFSET REF BW dBc dBm dBc dBm

3.375MHz 750.0kHz –11.10 –34.32 –72.19 –95.42

6.375MHz 5.250M Hz –0.75 –23.98 –68.97 –92.20

12.00MHz 6.000M Hz –0.59 –23.81 –70.32 –93.55

18.00MHz 6.000M Hz –0.35 –23.58 –70.70 –93.93

SWEEP 136. 2ms (601 PTS)

= 840 MHz, Temperature = 25°C,

OUT

SPAN 42MHz

07852-022

Sum Scale = 20, Full-Scale Current = 25 mA, Span = 42 MHz, Channel 4

Rev. A | Page 18 of 76

AD9789

A

TTEN 2dBREF –35.96dBm

CENTER 834.00MHz RES BW 30kHz

RMS RESULTS CARRIER POWER

–23.62dBm/

6.00000MHz

VBW 300kHz

FREQ. LOWER UPPER OFFSET REF BW dBc dBm dBc dBm

3.375MHz 750.0kHz –72.95 –96.56 –10. 86 –34.48

6.375MHz 5.250M Hz –69.38 –92.99 –0.51 –24.13

Figure 46. Zoomed 4-Channel QAM ACLR, f

SWEEP 58.4ms (601 PTS)

OUT

SPAN 18MHz

= 840 MHz, Temperature =

07852-024

25°C, Sum Scale = 20, Full-Scale Current = 25 mA, Span = 18 MHz, Channel 1

50

48

46

44

42

40

MER (dB)

38

36

34

32

30

50 150 250 350 450 550 650 750 850 950

f

OUT

(MHz)

+25°C

+85°C

–40°C

07852-032

Figure 47. Modulation Error Ratio, Equalized, 1-Channel 256-QAM,

f

= 2.29376 GHz, Full-Scale Current = 20 mA, Sum Scale = 48

DAC

(Equalization Filter from Demodulation Toolbox on Spectrum Analyzer Used)

50

48

46

44

42

40

MER (dB)

38

36

34

32

30

50 150 250 350 450 550 650 750 850 950

f

OUT

(MHz)

+25°C

+85°C

–40°C

07852-033

Figure 48. Modulation Error Ratio, Unequalized, 1-Channel 256-QAM,

= 2.29376 GHz, Full-Scale Current = 20 mA, Sum Scale = 48

f

DAC

CENTER 852.00MHz RES BW 30kHz

RMS RESULTS CARRIER POWER

–23.20dBm/

6.00000MHz

VBW 300kHz

FREQ. LOWER UPPER OFFSET REF BW dBc dBm dBc dBm

3.375MHz 750.0kHz –11.20 –34.40 –74.44 –97.64

6.375MHz 5.250M Hz –0.77 –23.96 –69.07 –92.26

Figure 49. Zoomed 4-Channel QAM ACLR, f

SWEEP 58.4ms (601 PTS)

OUT

SPAN 18MHz

= 840 MHz, Temperature =

07852-025

25°C, Sum Scale = 20, Full-Scale Current = 25 mA, Span = 18 MHz, Channel 4

50

48

46

44

42

40

MER (dB)

38

36

34

32

30

50 150 250 350 450 550 650 750 850 950

f

OUT

(MHz)

+25°C

+85°C

–40°C

07852-035

Figure 50. Modulation Error Ratio, Equalized, 4-Channel 256-QAM,

f

= 2.29376 GHz, Full-Scale Current = 25 mA, Sum Scale = 20

DAC

(Equalization Filter from Demodulation Toolbox on Spectrum Analyzer Used)

50

48

46

44

42

40

MER (dB)

38

36

34

32

30

50 150 250 350 450 550 650 750 850 950

f

OUT

(MHz)

+25°C

+85°C

–40°C

07852-036

Figure 51. Modulation Error Ratio, Unequalized, 4-Channel 256-QAM,

= 2.29376 GHz, Full-Scale Current = 25 mA, Sum Scale = 20

f

DAC

Rev. A | Page 19 of 76

AD9789

–

A

m

A

m

80

75

70

65

60

55

50

45

40

SFDR (dBc)

35

30

25

20

15

10

1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400

Figure 52. SFDR vs. f

in Mix Mode, f

OUT

f

(MHz)

OUT

= 2.4 GHz, Full-Scale Current = 20 mA

DAC

(Second Nyquist Zone Performance)

90

85

80

75

70

65

60

55

IMD (dBc)

50

45

40

35

30

1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400

Figure 53. IMD vs. f

in Mix Mode, f

OUT

f

(MHz)

OUT

= 2.4 GHz, Full-Scale Current = 20 mA

DAC

(Second Nyquist Zone Performance)

07852-068

CENTER 2.100G Hz RES BW 30kHz VBW 300kHz

RMS RESULTS CARRIER POWER –19.95dBm/

3.84000MHz

Figure 55. One-Carrier WCDMA ACLR in Mix Mode, f

f

07852-076

TTEN 0dBRE F –32.62dB

SWEEP 174. 6ms (601 PTS)

FREQ. LOWER UPPER

OFFSET REF BW dBc dBm dBc dBm

5.000MHz 3.840M Hz –68.93 –88.88 –67.99 –87.94

10.00MHz 3.840M Hz –71.31 –91.26 –70.42 –90.37

15.00MHz 3.840M Hz –73.43 –93.37 –72.68 –92.63

20.00MHz 3.840M Hz –75.12 –95.07 –74.89 –94.84

25.00MHz 3.840M Hz –75.60 –95.55 –76.51 –96.46

= 2304 MHz, Full-Scale Current = 20 mA

DAC

TTEN 2dBRE F –38.62dB

SPAN 53.84MHz

OUT

= 2.1 GHz,

07852-092

40

–45

–50

–55

–60

–65

ACLR (dBc)

–70

–75

–80

–85

Figure 54. ACLR vs. f

FIRST ADJACENT CHANNE L SECOND ADJACENT CHANNE L THIRD ADJACENT CHANNE L FIFTH ADJACENT CHANNE L

1150 1250 1350 1450 1550 1650 1750 1850 1950 2050 2150 2250

in Mix Mode with One-Carrier WCDMA, f

OUT

f

OUT

(MHz)

Full-Scale Current = 20 mA (Second Nyquist Zone Performance)

= 2304 MHz,

DAC

07852-075

Rev. A | Page 20 of 76

CENTER 2.102 50G Hz RES BW 30kHz VBW 300kHz

FREQ. LOWER UPPER RMS RESULTS CARRIER POWER –26.06dBm/

3.84000MHz

OFFSET REF BW dBc dBm dBc dBm

5.000MHz 3.840M Hz –0.25 –26.31 –0.42 –26.47

10.00MHz 3.840M Hz –0.42 –26.48 –63.50 –89.56

15.00MHz 3.840M Hz –64.07 –90.13 –65.13 –91.18

20.00MHz 3.840M Hz –65.36 –91.42 –66.97 –93.03

25.00MHz 3.840M Hz –66.86 –92.92 –68.70 –94.76

30.00MHz 3.840M Hz –67.83 –93.89 –68.64 –94.70

SWEEP 207ms (601 PTS)

Figure 56. Four-Carrier WCDMA ACLR in Mix Mode, f

= 2304 MHz, Full-Scale Current = 20 mA

f

DAC

SPAN 63.84MHz

= 2.1 GHz,

OUT

07852-093

AD9789

1100

1000

900

800

700

600

500

400

300

POWER DISSIPATIO N (mW)

200

100

Figure 57. Power Dissipation by Supply vs. f

AVDD33 DVDD33 (LVDS) DVDD33 (CMOS) DVDD18 DVDD15 CVDD18

0

1.0 1. 2 1.4 1.6 1.8 2.0 2.2 2.4

f

(GHz)

DAC

, 4-Channel DOCSIS, f

DAC

= 915 MHz,

OUT

Full-Scale Current = 25 mA (Datapath Configuration: QAM Encoder On,

SRRC Filter On, Four 2× Interpolation Filters On)

07852-094

2000

1800

1600

1400

1200

1000

800

600

POWER DISSIPATIO N (mW)

400

200

Figure 60. Total Power Dissipation vs. f

TOTAL (CMOS) TOTAL (LVDS)

0

1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4

f

(GHz)

DAC

, 4-Channel DOCSIS, f

DAC

= 915 MHz,

OUT

Full-Scale Current = 25 mA (Datapath Configuration: QAM Encoder On,

SRRC Filter On, Four 2× Interpolation Filters On)

07852-096

700

600

500

400

300

200

POWER DISSIPATION (mW)

100

AVDD33 DVDD33 (LVDS) DVDD33 (CMOS) DVDD18 DVDD15 CVDD18

0

1.0 1. 2 1.4 1.6 1.8 2.0 2.2 2.4

f

DAC

(GHz)

Figure 58. Power Dissipation by Supply vs. f

One Channel Enabled, f

200

180

160

140

120

100

80

60

POWER DISSIPATION (mW)

40

20

0

8 101214161820222426283032

= 70 MHz, Full-Scale Current = 20 mA

OUT

AVDD33

FULL-SCAL E CURRENT (mA)

Figure 59. AVDD33 Power Dissipation vs. Full-Scale Current

, 16× Interpolation,

DAC

1400

1200

1000

800

600

400

POWER DISSIPATION (mW)

200

07852-095

Figure 61. Total Power Dissipation vs. f

One Channel Enabled, f

07852-098

TOTAL (CMOS) TOTAL (LVDS)

0

1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4

f

(GHz)

DAC

, 16× Interpolation,

= 70 MHz, Full-Scale Current = 20 mA

OUT

DAC

07852-097

Rev. A | Page 21 of 76

AD9789

TERMINOLOGY

Monotonicity

A DAC is monotonic if the output either increases or remains constant as the digital input increases.

Offset Error

Offset error is the deviation of the output current from the ideal of 0. For IOUTP, 0 mA output is expected when all inputs are set to 0. For IOUTN, 0 mA output is expected when all inputs are set to 1.

Gain Error

Gain error is the difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s.

Temp er at u re D ri ft

Temperature drift is specified as the maximum change from the ambient (25°C) value to the value at either T

MIN

or T

. For offset,

MAX

gain, and reference drift, the drift is reported in ppm per °C.

Power Supply Rejection (PSR)

PSR is the maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages.

Output Compliance Range

The output compliance range is the range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance.

Spurious-Free Dynamic Range (SFDR)

SFDR is the difference, in dB, between the peak amplitude of the output signal and the peak spurious signal over the specified bandwidth.

Noise Spectral Density (NSD)

NSD is the converter noise power per unit of bandwidth. NSD is usually specified in dBm/Hz in the presence of a 0 dBm fullscale signal.

Adjacent Channel Leakage Ratio (ACLR)

The adjacent channel leakage (power) ratio is the ratio, in dBc, between the measured power within a channel relative to its adjacent channels.

Modulation Error Ratio (MER)

Modulated signals create a discrete set of output values referred to as a constellation. Each symbol creates an output signal corresponding to one point on the constellation. MER is a measure of the discrepancy between the average output symbol magnitude and the rms error magnitude of the individual symbol.

Intermodulation Distortion (IMD)

IMD is the result of two or more signals at different frequencies mixing together. Many products are created according to the formula af

± bf2, where a and b are integer values.

1

Rev. A | Page 22 of 76

AD9789

SERIAL CONTROL PORT

The AD9789 serial control port is a flexible, synchronous serial communications port that allows an easy interface to many industry-standard microcontrollers and microprocessors. The AD9789 serial control port is compatible with most synchronous transfer formats, including both the Motorola SPI® and Intel® SSR protocols. The serial control port allows read/write access to all registers that configure the AD9789. Single- or multiple-byte transfers are supported, as well as MSB first or LSB first transfer formats. The AD9789 serial control port can be configured for a single bidirectional I/O pin (SDIO only) or for two unidirectional I/O pins (SDIO/SDO). By default, the AD9789 is in unidirectional long instruction mode (long instruction mode is the only instruction mode supported).

SERIAL CONTROL PORT PIN DESCRIPTIONS

The SCLK (serial clock) pin is the serial shift clock. This pin is an input. SCLK is used to synchronize serial control port reads and writes. Write data bits are registered on the rising edge of this clock, and read data bits are registered on the falling edge. This pin is internally pulled down by a 30 kΩ resistor to ground.

SDIO (serial data input/output) is a dual-purpose pin that acts as an input only (unidirectional mode) or as both an input and an output (bidirectional mode). The AD9789 defaults to the unidirectional I/O mode (Register 0x00[7] = 0).

The SDO (serial data output) pin is used only in the unidirectional I/O mode as a separate output pin for reading back data.

CS

(chip select bar) is an active low control that gates the read

and write cycles. When

CS

is high, SDO and SDIO are in a high impedance state. This pin is internally pulled up by a 30 kΩ resistor to DVDD33.

SCLK

M1

AD9789

L1

CS

SDO

SDIO

Figure 62. Serial Control Port

N1

P1

SERIAL

CONTROL

PORT

07852-048

GENERAL OPERATION OF SERIAL CONTROL PORT

A write or read operation to the AD9789 is initiated by pulling CS

low. CS stall high is supported in modes where three or

fewer bytes of data (plus the instruction data) are transferred

CS

(see ). In these modes, Tabl e 7 on any byte boundary, allowing time for the system controller to process the next byte.

CS

only and can go high during either part (instruction or data) of the transfer.

During

CS

stall high mode, the serial control port state machine enters a wait state until all data is sent. If the system controller decides to abort the transfer before all of the data is sent, the state machine must be reset by either completing the remaining

can temporarily return high

can go high on byte boundaries

transfers or by returning cycle (but less than eight SCLK cycles). Raising boundary terminates the serial transfer and flushes the buffer.

In streaming mode (see Ta b le 7 ), any number of data bytes can be transferred in a continuous stream. The register address is automatically incremented or decremented (see the MSB/LSB First Transfers section). byte to be transferred, thereby ending streaming mode.

Communication Cycle—Instruction Plus Data

There are two parts to a communication cycle with the AD9789. In the first part, a 16-bit instruction word is written to the AD9789, coincident with the first 16 SCLK rising edges. The instruction word provides the AD9789 serial control port with information regarding the data transfer, which is the second part of the communication cycle. The instruction word defines whether the upcoming data transfer is a read or a write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer.

Write

If the instruction word is for a write operation, the second part of the communication cycle is the transfer of data into the serial control port buffer of the AD9789. Data bits are registered on the rising edge of SCLK.

The length of the transfer (one, two, or three bytes or streaming mode) is indicated by two bits (N1 and N0) in the instruction byte. When the transfer is one, two, or three bytes (but not streaming

CS

mode),

can be raised after each sequence of eight bits to stall the bus, except after the last byte, where it ends the cycle. When the bus is stalled, the serial transfer resumes when Raising

CS

on a nonbyte boundary resets the serial control port. During a write, streaming mode does not skip reserved or blank registers; therefore, the user must know what bit pattern to write to the reserved registers to preserve proper operation of the part. It does not matter what data is written to blank registers.

Most writes to the control registers immediately reconfigure the device. However, Register 0x16 through Register 0x1D do not directly control device operation. They provide data to internal logic that must perform additional operations on the data before it is downloaded and the device configuration is changed. For any updates to Register 0x16 through Register 0x1D to take effect, the FREQNEW bit (Register 0x1E[7]) must be set to 1 (this bit is self-clearing). Any number of bytes of data can be changed before updating registers. Setting the FREQNEW bit simultaneously updates Register 0x16 through Register 0x1D.

In a similar fashion, any changes to Register 0x22 and Register 0x23 require PARMNEW (Register 0x24[7]) to be toggled from a low state to a high state before the new values take effect. Unlike the FREQNEW bit, PARMNEW is not self-clearing.

CS

low for at least one complete SCLK

CS

on a nonbyte

CS

must be raised at the end of the last

CS

is lowered.

Rev. A | Page 23 of 76

ANALOG DEVICES AD9789 Service Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

DETAILED FUNCTIONAL BLOCK DIAGRAMS

SPECIFICATIONS

DC SPECIFICATIONS

DIGITAL SPECIFICATIONS

AC SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TERMINOLOGY

SERIAL CONTROL PORT

SERIAL CONTROL PORT PIN DESCRIPTIONS

GENERAL OPERATION OF SERIAL CONTROL PORT

Communication Cycle—Instruction Plus Data

Write