Analog Devices AD9767 b Datasheet

a

“1”

LATCH

“1”

DAC

REFIO
FSADJ1
FSADJ2
GAINCTRL

REFERENCE

BIAS

GENERATOR

I

OUTA1

I

OUTB1

SLEEP

I

OUTA2

I

OUTB2

DIGITAL

INTERFACE

AD9767

PORT1

PORT2

WRT1

WRT2

DVDD DCOM AVDD ACOM CLK1

CLK2

MODE

“2”

DAC

“2”

LATCH

14-Bit, 125 MSPS

Dual TxDAC+

®

D/A Converter

AD9767*

FEATURES
14-Bit Dual Transmit DAC
125 MSPS Update Rate
Excellent SFDR and IMD: 82 dBc
Excellent Gain and Offset Matching: 0.1%
Fully Independent or Single Resistor Gain Control
Dual Port or Interleaved Data
On-Chip 1.2 V Reference
Single 5 V or 3 V Supply Operation
Power Dissipation: 380 mW @ 5 V
Power-Down Mode: 50 mW @ 5 V
48-Lead LQFP

APPLICATIONS
Communications
Base Stations
Digital Synthesis
Quadrature Modulation

PRODUCT DESCRIPTION

The AD9767 is a dual port, high speed, two channel, 14-bit
CMOS DAC. It integrates two high quality 14-bit TxDAC+
cores, a voltage reference and digital interface circuitry into a small
48-lead LQFP package. The AD9767 offers exceptional ac and
dc performance while supporting update rates up to 125 MSPS.

The AD9767 has been optimized for processing I and Q data in
communications applications. The digital interface consists of
two double-buffered latches as well as control logic. Separate
write inputs allow data to be written to the two DAC ports
independent of one another. Separate clocks control the update
rate of the DACs.

A mode control pin allows the AD9767 to interface to two sep­arate data ports, or to a single interleaved high speed data port.
In interleaving mode the input data stream is demuxed into its
original I and Q data and then latched. The I and Q data is then
converted by the two DACs and updated at half the input data
rate.

The GAINCTRL pin allows two modes for setting the full-scale
current (I
set independently using two external resistors, or I

) of the two DACs. I

OUTFS

for each DAC can be

OUTFS

OUTFS

for both

DACs can be set by using a single external resistor.**

The DACs utilize a segmented current source architecture com­bined with a proprietary switching technique to reduce glitch
energy and to maximize dynamic accuracy. Each DAC provides

FUNCTIONAL BLOCK DIAGRAM

differential current output thus supporting single-ended or
differential applications. Both DACs can be simultaneously
updated and provide a nominal full-scale current of 20 mA. The
full-scale currents between each DAC are matched to within

0.1%.

The AD9767 is manufactured on an advanced low cost CMOS
process. It operates from a single supply of 3.0 V to 5.0 V and
consumes 380 mW of power.

PRODUCT HIGHLIGHTS

1. The AD9767 is a member of a pin-compatible family of dual
TxDACs providing 8-, 10-, 12- and 14-bit resolution.

2. Dual 14-Bit, 125 MSPS DACs: A pair of high performance
DACs optimized for low distortion performance provide for
flexible transmission of I and Q information.

3. Matching: Gain matching is typically 0.1% of full scale, and
offset error is better than 0.02%.

4. Low Power: Complete CMOS Dual DAC function operates
on 380 mW from a 3.0 V to 5.0 V single supply. The DAC
full-scale current can be reduced for lower power operation,
and a sleep mode is provided for low power idle periods.

5. On-Chip Voltage Reference: The AD9767 includes a 1.20 V
temperature-compensated bandgap voltage reference.

6. Dual 14-Bit Inputs: The AD9767 features a flexible dual­port interface allowing dual or interleaved input data.

TxDAC+ is a registered trademark of Analog Devices, Inc.

**Patent pending.

**Please see GAINCTRL Mode section, for important date code information on

this feature.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

AD9767–SPECIFICATIONS

(T

to T

DC SPECIFICATIONS

MIN

, AVDD = +5 V, DVDD = +5 V, I

MAX

Parameter Min Typ Max Units

RESOLUTION 14 Bits

DC ACCURACY

1

Integral Linearity Error (INL)

T

= +25°C –3.5 ± 1.5 +3.5 LSB

A

T

MIN

to T

MAX

–4.0 +4.0 LSB

Differential Nonlinearity (DNL)

= +25°C –2.5 ± 1.0 +2.5 LSB

T

A

T

MIN

to T

MAX

–3.0 +3.0 LSB

ANALOG OUTPUT

Offset Error –0.02 +0.02 % of FSR
Gain Error (Without Internal Reference) –2 ±0.25 +2 % of FSR
Gain Error (With Internal Reference) –5 ±1 +5 % of FSR
Gain Match –1.6 0.1 +1.6 % of FSR

–0.14 +0.14 dB

2.0 20.0 mA

Full-Scale Output Current

2

Output Compliance Range –1.0 +1.25 V
Output Resistance 100 kΩ
Output Capacitance 5 pF

REFERENCE OUTPUT

Reference Voltage 1.14 1.20 1.26 V
Reference Output Current

3

REFERENCE INPUT

Input Compliance Range 0.1 1.25 V
Reference Input Resistance 1 MΩ
Small Signal Bandwidth 0.5 MHz

TEMPERATURE COEFFICIENTS

Offset Drift 0 ppm of FSR/°C
Gain Drift (Without Internal Reference) ±50 ppm of FSR/°C
Gain Drift (With Internal Reference) ±100 ppm of FSR/°C
Reference Voltage Drift ±50 ppm/°C

POWER SUPPLY

Supply Voltages

AVDD 3 5 5.5 V

DVDD 2.7 5 5.5 V
Analog Supply Current (I
Digital Supply Current (I
Digital Supply Current (I
Supply Current Sleep Mode (I
Power Dissipation
Power Dissipation
Power Dissipation

4

(5 V, I

5

(5 V, I

6

(5 V, I

Power Supply Rejection Ratio

)7175mA

AVDD

4

)

DVDD

5

)

DVDD

OUTFS

OUTFS

OUTFS

)812mA

AVDD

= 20 mA) 380 410 mW
= 20 mA) 420 450 mW
= 20 mA) 450 mW

7

—AVDD –0.4 +0.4 % of FSR/V

Power Supply Rejection Ratio7—DVDD –0.025 +0.025 % of FSR/V

OPERATING RANGE –40 +85 °C

NOTES

1

Measured at I

2

Nominal full-scale current, I

3

An external buffer amplifier with input bias current <100 nA should be used to drive any external load.

4

Measured at f

5

Measured at f

6

Measured as unbuffered voltage output with I

7

±10% Power supply variation.

Specifications subject to change without notice.

, driving a virtual ground.

OUTA

= 25 MSPS and f

CLOCK

= 100 MSPS and f

CLOCK

, is 32 times the I

OUTFS

= 1.0 MHz.

OUT

= 1 MHz.

OUT

current.

REF

= 20 mA and 50 Ω R

OUTFS

LOAD

at I

OUTA

= 20 mA, unless otherwise noted.)

OUTFS

100 nA

57 mA

15 mA

and I

OUTB

, f

= 100 MSPS and f

CLOCK

= 40 MHz.

OUT

–2–

REV. B

AD9767

(T

to T

DYNAMIC SPECIFICATIONS

MIN

, AVDD = +5 V, DVDD = +5 V, I

MAX

Output, 50 ⍀ Doubly Terminated, unless otherwise noted)

Parameter Min Typ Max Units

DYNAMIC PERFORMANCE

Maximum Output Update Rate (f
Output Settling Time (t
Output Propagation Delay (t

) (to 0.1%)

ST

)1ns

PD

Glitch Impulse 5 pV-s
Output Rise Time (10% to 90%)
Output Fall Time (90% to 10%)
Output Noise (I
Output Noise (I

= 20 mA) 50 pA/√Hz

OUTFS

= 2 mA) 30 pA/√Hz

OUTFS

) 125 MSPS

CLOCK

1

1

1

AC LINEARITY

Spurious-Free Dynamic Range to Nyquist

= 100 MSPS; f

f

CLOCK

= 1.00 MHz

OUT

0 dBFS Output 71 82 dBc
–6 dBFS Output 77 dBc
–12 dBFS Output 73 dBc
–18 dBFS Output 70 dBc

= 65 MSPS; f

f

CLOCK

= 65 MSPS; f

f

CLOCK

f

= 65 MSPS; f

CLOCK

f

= 65 MSPS; f

CLOCK

= 65 MSPS; f

f

CLOCK

f

= 125 MSPS; f

CLOCK

f

= 125 MSPS; f

CLOCK

= 1.00 MHz 82 dBc

OUT

= 2.51 MHz 80 dBc

OUT

= 5.02 MHz 79 dBc

OUT

= 14.02 MHz 70 dBc

OUT

= 25 MHz 55 dBc

OUT

= 25 MHz 67 dBc

OUT

= 40 MHz 70 dBc

OUT

Spurious-Free Dynamic Range Within a Window

= 100 MSPS; f

f

CLOCK

f

= 50 MSPS; f

CLOCK

= 65 MSPS; f

f

CLOCK

f

= 125 MSPS; f

CLOCK

= 1.00 MHz; 2 MHz Span 82 91 dBc

OUT

= 5.02 MHz; 10 MHz Span 88 dBc

OUT

= 5.03 MHz; 10 MHz Span 88 dBc

OUT

= 5.04 MHz; 10 MHz Span 88 dBc

OUT

Total Harmonic Distortion

= 100 MSPS; f

f

CLOCK

f

= 50 MSPS; f

CLOCK

f

= 125 MSPS; f

CLOCK

= 125 MSPS; f

f

CLOCK

= 1.00 MHz –81 –71 dBc

OUT

= 2.00 MHz –79 dBc

OUT

= 4.00 MHz –83 dBc

OUT

= 10.00 MHz –80 dBc

OUT

Multitone Power Ratio (Eight Tones at 110 kHz Spacing)

f

= 65 MSPS; f

CLOCK

= 2.00 MHz to 2.99 MHz

OUT

0 dBFS Output 80 dBc
–6 dBFS Output 79 dBc
–12 dBFS Output 78 dBc
–18 dBFS Output 76 dBc

Channel Isolation

= 125 MSPS; f

f

CLOCK

f

= 125 MSPS; f

CLOCK

NOTES

1

Measured single-ended into 50 Ω load.

Specifications subject to change without notice.

= 10 MHz 85 dBc

OUT

= 40 MHz 77 dBc

OUT

= 20 mA, Differential Transformer Coupled

OUTFS

35 ns

2.5 ns

2.5 ns

REV. B –3–

AD9767–SPECIFICATIONS

WARNING!

ESD SENSITIVE DEVICE

(T

to T

DIGITAL SPECIFICATIONS

MIN

, AVDD = +5 V, DVDD = +5 V, I

MAX

Parameter Min Typ Max Units

DIGITAL INPUTS

Logic “1” Voltage @ DVDD = +5 V 3.5 5 V
Logic “1” @ DVDD = 3 2.1 3 V
Logic “0” Voltage @ DVDD = +5 V 0 1.3 V
Logic “0” @ DVDD = 3 0 0.9 V
Logic “1” Current –10 +10 µA
Logic “0” Current –10 +10 µA
Input Capacitance 5 pF
Input Setup Time (t
Input Hold Time (t
Latch Pulsewidth (t

Specifications subject to change without notice.

) 2.0 ns

S

) 1.5 ns

H

, t

LPW

) 3.5 ns

CPW

ABSOLUTE MAXIMUM RATINGS*

With

Parameter Respect to Min Max Units

AVDD ACOM –0.3 +6.5 V
DVDD DCOM –0.3 +6.5 V
ACOM DCOM –0.3 +0.3 V
AVDD DVDD –6.5 +6.5 V
MODE, CLK1, CLK2, WRT1, WRT2 DCOM –0.3 DVDD + 0.3 V
Digital Inputs DCOM –0.3 DVDD + 0.3 V
I

OUTA1/IOUTA2

, I

OUTB1/IOUTB2

ACOM –1.0 AVDD + 0.3 V
REFIO, FSADJ1, FSADJ2 ACOM –0.3 AVDD + 0.3 V
GAINCTRL, SLEEP ACOM –0.3 AVDD + 0.3 V
Junction Temperature +150 °C
Storage Temperature –65 +150 °C
Lead Temperature (10 sec) +300 °C

*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for
extended periods may affect device reliability.

= 20 mA, unless otherwise noted.)

OUTFS

ORDERING GUIDE

Temperature Package Package

Model Range Description Option*

(WRT2) (WRT1 / IQWRT)

DATA IN

AD9767AST –40°C to +85°C 48-Lead LQFP ST-48
AD9767-EB Evaluation Board

*ST = Thin Plastic Quad Flatpack.

(CLK2) (CLK1/ IQCLK)

THERMAL CHARACTERISTICS
Thermal Resistance

48-Lead LQFP

θ

= 91°C/W

JA

Figure 1. Timing Diagram for Dual and Interleaved Modes

See Dynamic and Digital sections for timing specifications.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9767 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–4–

IOUTA

OR

IOUTB

t

S

t

H

t

LPW

t

CPW

t

PD

REV. B

PIN FUNCTION DESCRIPTIONS

Pin No. Name Description

1–14 PORT1 Data Bits DB13–P1 to DB0–P1.
15, 21 DCOM1, DCOM2 Digital Common.
16, 22 DVDD1, DVDD2 Digital Supply Voltage.
17 WRT1/IQWRT Input write signal for PORT 1 (IQWRT in interleaving mode).
18 CLK1/IQCLK Clock input for DAC1 (IQCLK in interleaving mode).
19 CLK2/IQRESET Clock input for DAC2 (IQRESET in interleaving mode).
20 WRT2/IQSEL Input write signal for PORT 2 (IQSEL in interleaving mode).
23–36 PORT2 Data Bits DB13–P2 to DB0–P2.
37 SLEEP Power-Down Control Input.
38 ACOM Analog Common.
39, 40 I

OUTA2

, I

OUTB2

“PORT 2” differential DAC current outputs.
41 FSADJ2 Full-scale current output adjust for DAC2.
42 GAINCTRL GAINCTRL Mode (0 = 2 resistor, 1 = 1 resistor.)
43 REFIO Reference Input/Output.
44 FSADJ1 Full-scale current output adjust for DAC1.
45, 46 I

OUTB1

, I

OUTA1

“PORT 1” differential DAC current outputs.
47 AVDD Analog Supply Voltage.
48 MODE Mode Select (1 = Dual Port, 0 = Interleaved).

AD9767

DB13-P1 (MSB)

DB12-P1

DB11-P1

DB10-P1

DB9-P1

DB8-P1

DB7-P1

DB6-P1

DB5-P1

DB4-P1

DB3-P1

DB2-P1

PIN CONFIGURATION

OUTA1IOUTB1

MODE

AVDD

I

FSADJ1

REFIO

GAINCTRL

AD9767

CLK1/IQCLK

WRT1/IQWRT

FSADJ2

WRT2/IQSEL

CLK2/IQRESET

48 47 46 45 44 39 38 3743 42 41 40

1

PIN 1

2

IDENTIFIER

3

4

5

6

7

8

9

10

11

12

13 14 15 16 17 18 19 20 21 22 23 24

DB1-P1

DB0-P1

DCOM1

TOP VIEW

(Not to Scale)

DVDD1

OUTB2IOUTA2

I

DVDD2

DCOM2

ACOM

SLEEP

DB13-P2

DB12-P2

36

35

34

33

32

31

30

29

28

27

26

25

DB0-P2

DB1-P2

DB2-P2

DB3-P2

DB4-P2

DB5-P2

DB6-P2

DB7-P2

DB8-P2

DB9-P2

DB10-P2

DB11-P2

REV. B

–5–

AD9767

DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)

Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.

Differential Nonlinearity (or DNL)

DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input
code.

Monotonicity

A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.

Offset Error

The deviation of the output current from the ideal of zero is
called offset error. For I
inputs are all 0s. For I

, 0 mA output is expected when the

OUTA

, 0 mA output is expected when all

OUTB

inputs are set to 1s.

Gain Error

The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.

Output Compliance Range

The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown resulting in
nonlinear performance.

Temperature Drift

Temperature drift is specified as the maximum change from the
ambient (+25°C) value to the value at either T

MIN

or T

MAX

. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree C. For reference drift, the drift is
reported in ppm per degree C (ppm/°C).

Power Supply Rejection

The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.

Settling Time

The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.

Glitch Impulse

Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.

Spurious-Free Dynamic Range

The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.

Total Harmonic Distortion

THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal. It is
expressed as a percentage or in decibels (dB).

R

1

SET

2k⍀

0.1␮F

R

SET

2k⍀

DVDD

DCOM

*RETIMED CLOCK OUTPUT

FSADJ1

REFIO

FSADJ2

2

LECROY 9210

PULSE

GENERATOR

1.2V REF

GAINCTRL

WRT1/
IQWRT

50⍀

AVDD

PMOS

CURRENT

SOURCE

ARRAY

PMOS

CURRENT

SOURCE

ARRAY

AD9767

5V

DB0 – DB13 DB0 – DB13

DIGITAL

DATA

TEKTRONIX

AWG-2021

w/OPTION 4

CLK1/IQCLK

CLK

DIVIDER

DAC 1

LATCH

DAC 2

LATCH

MULTIPLEXING LOGIC

CHANNEL 2 LATCHCHANNEL 1 LATCH

*AWG2021 CLOCK RETIMED SUCH THAT
DIGITAL DATA TRANSITIONS ON FALLING
EDGE OF 50% DUTY CYCLE CLOCK

CLK2/IQRESET

SEGMENTED

SWITCHES FOR

DAC1

SEGMENTED

SWITCHES FOR

DAC2

SWITCH

SWITCH

WRT2/
IQSEL

SLEEP

LSB

LSB

ACOM

I

OUTA1

I

OUTB1

I

OUTA2

I

OUTB2

MODE

DVDD

DCOM

50⍀ 50⍀

5V

MINI

CIRCUITS

T1-1T

TO HP3589A
SPECTRUM/
NETWORK
ANALYZER

Figure 2. Basic AC Characterization Test Setup for AD9767, Testing Port 1 in Dual Port Mode, Using Independent
GAINCTRL Resistors on FSADJ1 and FSADJ2

–6–

REV. B

Typical Characterization Curves

(AVDD = +5 V, DVDD = +3.3 V, I
otherwise noted.)

90

5MSPS

80

70

SFDR – dBc

60

25MSPS

65MSPS

= 20 mA, 50 ⍀ Doubly Terminated Load, Differential Output, TA = +25ⴗC, SFDR up to Nyquist, unless

OUTFS

125MSPS

90

85

SFDR – dBc

80

–12dBFS

0dBFS

–6dBFS

90

85

80

75

SFDR – dBc

70

65

AD9767

0dBFS

–12dBFS

–6dBFS

50

110

Figure 3. SFDR vs. f

85

80

75

70

65

SFDR – dBc

60

55

50

05 25

Figure 6. SFDR vs. f

90

85

80

75

SFDR – dBc

70

65

60

–20 –15

f

– MHz

OUT

0dBFS

–6dBFS

10 15 20

f

OUT

910kHz/10MSPS

2.27MHz/25MSPS

5.91MHz/65MSPS

–10 –5

A

OUT

@ 0 dBFS

OUT

–12dBFS

– MHz

OUT

11.37MHz/125MSPS

– dBFS

30 35

@ 65 MSPS

Figure 9. Single-Tone SFDR vs. A
@ f

OUT

= f

CLOCK

/11

100

0

OUT

75

0.00 2.500.50 1.00 1.50 2.00

Figure 4. SFDR vs. f

85

80

75

70

–12dBFS

65

SFDR – dBc

60

55

50

010 50

Figure 7. SFDR vs. f

90

85

2MHz/10MSPS

80

75

70

SFDR – dBc

65

60

55

50

–20 –15 –5

0dBFS

20 30 40

5MHz/25MSPS

f

– MHz

OUT

OUT

–6dBFS

f

– MHz

OUT

@ 125 MSPS

OUT

1MHz/5MSPS

13MHz/65MSPS

25MHz/125MSPS

–10

A

– dBFS

OUT

@ 5 MSPS

60 70

Figure 10. Single-Tone SFDR vs.

@ f

A

OUT

OUT

= f

CLOCK

/5

60

0

Figure 5. SFDR vs. f

90

85

80

75

70

SFDR – dBc

65

60

55

50

0

Figure 8. SFDR vs. f

4

212

f

OUT

I

= 5mA

OUTFS

I

OUTFS

5152535

10

f

OUT

6

– MHz

OUT

I

= 20mA

– MHz

8

@ 25 MSPS

= 10mA

OUTFS

20 30

and I

OUT

10

OUTFS

@ 65 MSPS and 0 dBFS

85

80

75

70

65

SFDR – dBc

60

55

50

0

–25 –15 –10 –5

Figure 11. Dual-Tone SFDR vs. A
@ f

OUT

0.965/1.035MHz@7MSPS

3.38/3.63MHz@25MSPS

16.9/18.1MHz@125MSPS

6.75/7.25MHz@65MSPS

–20

A

– dBFS

OUT

= f

CLOCK

/7

0

OUT

REV. B

–7–

AD9767

75

I

= 20mA

OUTFS

70

I

= 10mA

65

SINAD – dBc

60

55

20 14040 60 80 100 120

Figure 12. SINAD vs. f
@ f

= 5 MHz and 0 dBFS

OUT

85

80

75

70

65

SFDR – dBc

60

55

50

45

–40 –20 80

–60

OUTFS

I

= 5mA

OUTFS

f

– MSPS

CLOCK

CLOCK

f

= 1MHz

OUT

f

= 10MHz

OUT

f

= 25MHz

OUT

f

= 40MHz

OUT

f

= 60MHz

OUT

TEMPERATURE – ⴗC

40200

and I

60

OUTFS

100

Figure 15. SFDR vs. Temperature @
125 MSPS, 0 dBFS

2.5

2.0

1.5

1.0

0.5

INL – LSBs

0

–0.5

–1.0

–1.5

4000 8000 12000 16000

0

CODE

Figure 13. Typical INL

0.05

GAIN ERROR

0.03
OFFSET ERROR

0.00

–0.03

OFFSET ERROR – % FS

–0.05

–40 –200 20406080

TEMPERATURE – ⴗC

1.0

0.5

0.00

–0.5

–1.0

Figure 16. Reference Voltage Drift
vs. Temperature

GAIN ERROR – % FS

0.4

0.2

0

–0.2

–0.4

–0.6

DNL – LSBs

–0.8

–1.0

–1.2

–1.4

0 200

400 600 800 1000

CODE

Figure 14. Typical DNL

10

0

–10

–20

–30

–40

dBm

–50

–60

–70

–80

–90

0

10 30

20

FREQUENCY – MHz

Figure 17. Single-Tone SFDR
@ f

= 125 MSPS

CLK

40

0

–10

–20

–30

–40

dBm

–50

–60

–70

–80

–90

0

20

10 30

FREQUENCY – MHz

Figure 18. Dual-Tone SFDR
@ f

= 125 MSPS

CLK

0

–10

–20

–30

–40

dBm

–50

–60

–70

–80

–90

0

40

10 30

20

FREQUENCY – MHz

40

Figure 19. Four-Tone SFDR

= 125 MSPS

@ f

CLK

–8–

REV. B

AD9767

+1.2V

REF

AVDD

GAINCTRL

CURRENT

SOURCE

ARRAY

REFIO

FSADJ

2k⍀

AD9767

REFERENCE

SECTION

I

REF

ACOM

AVDD

EXTERNAL

REFERENCE

I

REF

5V

CURRENT

CURRENT

AD9767

WRT1/
IQWRT

AVDD

PMOS

SOURCE

ARRAY

PMOS

SOURCE

ARRAY

MULTIPLEXING LOGIC

DB0 – DB13 DB0 – DB13

R

1

SET

2k⍀

1

I

2

REF

0.1␮F

R

SET

2k⍀

FSADJ1

REFIO

2

FSADJ2

1.2V REF

GAINCTRL

CLK1/IQCLK

CLK

DIVIDER

DAC 1

LATCH

DAC 2

LATCH

DIGITAL DATA INPUTS

Figure 20. Simplified Block Diagram

FUNCTIONAL DESCRIPTION

Figure 20 shows a simplified block diagram of the AD9767.
The AD9767 consists of two DACs, each with its own indepen­dent digital control logic and full-scale output current control.
Each DAC contains a PMOS current source array capable of
providing up to 20 mA of full-scale current (I

OUTFS

). The array
is divided into 31 equal currents that make up the five most
significant bits (MSBs). The next four bits, or middle bits,
consist of 15 equal current sources whose value is 1/16th of an
MSB current source. The remaining LSB is a binary weighted
fraction of the middle bit current sources. Implementing the
middle and lower bits with current sources, instead of an R-2R
ladder, enhances the dynamic performance for multitone or low
amplitude signals and helps maintain the DAC’s high output
impedance (i.e., >100 kΩ).

All of these current sources are switched to one or the other of
the two output nodes (i.e., I

OUTA

or I

) via PMOS differen-

OUTB

tial current switches. The switches are based on a new architec­ture that drastically improves distortion performance. This new
switch architecture reduces various timing errors and provides
matching complementary drive signals to the inputs of the dif­ferential current switches.

The analog and digital sections of the AD9767 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 3 V to 5.5 V range. The digital section,
which is capable of operating up to a 125 MSPS clock rate,
consists of edge-triggered latches and segment decoding logic
circuitry. The analog section includes the PMOS current sources,
the associated differential switches, a 1.20 V bandgap voltage
reference and two reference control amplifiers.

The full-scale output current of each DAC is regulated by sepa­rate reference control amplifiers and can be set from 2 mA to
20 mA via an external resistor, R

, connected to the Full

SET

Scale Adjust (FSADJ) pin. The external resistor, in combination
with both the reference control amplifier and voltage reference

, sets the reference current I

V

REFIO

, which is replicated to the

REF

segmented current sources with the proper scaling factor. The
full-scale current, I

REV. B

, is 32 × I

OUTFS

REF

.

–9–

CLK2/IQRESET

SWITCHES FOR

SEGMENTED

SWITCHES FOR

CHANNEL 2 LATCHCHANNEL 1 LATCH

SEGMENTED

DAC1

DAC2

SLEEP

LSB

SWITCH

LSB

SWITCH

WRT2/
IQSEL

ACOM

I

OUTA1

I

OUTB1

I

OUTA2

I

OUTB2

MODE

DVDD

DCOM

= V

A – V

V

DIFF

OUT

2A

V

OUT

V

2B

RL2B
50⍀

RL2A
50⍀

OUT

5V

B

OUT

1A

V

OUT

V

1B

RL1B
50⍀

RL1A
50⍀

OUT

REFERENCE OPERATION

The AD9767 contains an internal 1.20 V bandgap reference.
This can easily be overridden by an external reference with no
effect on performance. REFIO serves as either an input or out-
put, depending on whether the internal or an external reference
is used. To use the internal reference, simply decouple the
REFIO pin to ACOM with a 0.1 µF capacitor. The internal
reference voltage will be present at REFIO. If the voltage at
REFIO is to be used elsewhere in the circuit, an external buffer
amplifier with an input bias current of less than 100 nA should
be used. An example of the use of the internal reference is
shown in Figure 21.

OPTIONAL
EXTERNAL

REFERENCE

BUFFER

ADDITIONAL

EXTERNAL

LOAD

0.1␮F

I

REF

2k⍀

GAINCTRL

+1.2V

REF

REFIO

FSADJ

AD9767

REFERENCE

SECTION

AVDD

CURRENT

SOURCE

ARRAY

ACOM

Figure 21. Internal Reference Configuration

An external reference can be applied to REFIO as shown in
Figure 22. The external reference may provide either a fixed
reference voltage to enhance accuracy and drift performance or
a varying reference voltage for gain control. Note that the 0.1 µF
compensation capacitor is not required since the internal refer­ence is overridden, and the relatively high input impedance of
REFIO minimizes any loading of the external reference.

Figure 22. External Reference Configuration

AD9767

GAINCTRL MODE

The AD9767 allows the gain of each channel to be indepen­dently set by connecting one R
other R
system cost, a single R

resistor to FSADJ2. To add flexibility and reduce

SET

resistor can be used to set the gain of

SET

resistor to FSADJ1 and an-

SET

both channels simultaneously.

When GAINCTRL is low (i.e., connected to AGND), the inde­pendent channel gain control mode using two resistors is enabled.
In this mode, individual R

resistors should be connected to

SET

FSADJ1 and FSADJ2. When GAINCTRL is high (i.e., con­nected to AVDD), the master/slave channel gain control mode
using one resistor is enabled. In this mode, a single R

resistor

SET

is connected to FSADJ1 and the resistor on FSADJ2 must be
removed.

NOTE: Only parts with date code of 9930 or later have the
Master/Slave GAINCTRL function. For parts with a date code
before 9930, Pin 42 must be connected to AGND, and the part
will operate in the two resistor, independent gain control mode.

REFERENCE CONTROL AMPLIFIER

Both of the DACs in the AD9767 contain a control amplifier
that is used to regulate the full-scale output current, I

OUTFS

.
The control amplifier is configured as a V-I converter as shown
in Figure 21, so that its current output, I
by the ratio of the V
stated in Equation 4. I

and an external resistor, R

REFIO

is copied to the segmented current

REF

sources with the proper scale factor to set I

, is determined

REF

as stated in

OUTFS

SET

, as

Equation 3.

The control amplifier allows a wide (10:1) adjustment span of
I

from 2 mA to 20 mA by setting I

OUTFS

and 625 µA. The wide adjustment range of I

between 62.5 µA

REF

OUTFS

provides
several benefits. The first relates directly to the power dissipa­tion of the AD9767, which is proportional to I

OUTFS

(refer to
the Power Dissipation section). The second relates to the 20 dB
adjustment, which is useful for system gain control purposes.

The small signal bandwidth of the reference control amplifier is
approximately 500 kHz and can be used for low frequency,
small signal multiplying applications.

DAC TRANSFER FUNCTION

Both DACs in the AD9767 provide complementary current
outputs, I
current output, I
= 16383) while I
current. The current output appearing at I
a function of both the input code and I

OUTA

and I

OUTFS

OUTB

. I

OUTB

will provide a near full-scale

OUTA

, when all bits are high (i.e., DAC CODE

, the complementary output, provides no

and I

OUTA

and can be

OUTFS

OUTB

is

expressed as:

I

= (DAC CODE /16384) × I

OUTA

I

= (16383 – DAC CODE)/16384) × I

OUTB

OUTFS

OUTFS

(1)

(2)

where DAC CODE = 0 to 16383 (i.e., Decimal Representation).

As previously mentioned, I
current I
V

REFIO

, which is nominally set by a reference voltage,

REF

and external resistor R

I

= 32 × I

OUTFS

REF

is a function of the reference

OUTFS

. It can be expressed as:

SET

(3)

where

I

REF

= V

REFIO /RSET

(4)

The two current outputs will typically drive a resistive load di­rectly or via a transformer. If dc coupling is required, I
I

should be directly connected to matching resistive loads,

OUTB

, that are tied to analog common, ACOM. Note, R

R

LOAD

may represent the equivalent load resistance seen by I
I

as would be the case in a doubly terminated 50 Ω or

OUTB

OUTA

OUTA

LOAD

or

and

75 Ω cable. The single-ended voltage output appearing at the

and I

I

OUTA

V

OUTA

V

OUTB

Note the full-scale value of V

nodes is simply:

OUTB

= I

= I

OUTA

OUTB

× R
× R

LOAD

LOAD

OUTA

and V

should not exceed

OUTB

(5)

(6)

the specified output compliance range to maintain specified
distortion and linearity performance.

V

= (I

DIFF

Substituting the values of I

OUTA

– I

OUTB

) × R

OUTA

LOAD

, I

OUTB

and I

REF

; V

DIFF

(7)

can be

expressed as:

V

= {(2 × DAC CODE – 16383)/16384} ×

DIFF

(32 × R

LOAD/RSET

) × V

REFIO

(8)

These last two equations highlight some of the advantages of
operating the AD9767 differentially. First, the differential opera­tion will help cancel common-mode error sources associated
with I

OUTA

and I

such as noise, distortion and dc offsets.

OUTB

Second, the differential code dependent current and subsequent
voltage, V
output (i.e., V

, is twice the value of the single-ended voltage

DIFF

OUTA

or V

), thus providing twice the signal

OUTB

power to the load.

Note, the gain drift temperature performance for a single-ended
(V

OUTA

and V

) or differential output (V

OUTB

) of the AD9767

DIFF

can be enhanced by selecting temperature tracking resistors for
R

LOAD

and R

due to their ratiometric relationship as shown in

SET

Equation 8.

ANALOG OUTPUTS

The complementary current outputs in each DAC, I
I

, may be configured for single-ended or differential opera-

OUTB

tion. I
single-ended voltage outputs, V
tor, R

and I

OUTA

, as described in the DAC Transfer Function section

LOAD

can be converted into complementary

OUTB

OUTA

and V

, via a load resis-

OUTB

by Equations 5 through 8. The differential voltage, V
existing between V

OUTA

and V

can also be converted to a

OUTB

OUTA

and

DIFF

,

single-ended voltage via a transformer or differential amplifier
configuration. The ac performance of the AD9767 is optimum
and specified using a differential transformer coupled output in
which the voltage swing at I

OUTA

and I

If a single-ended unipolar output is desirable, I

is limited to ±0.5 V.

OUTB

OUTA

should be

selected.

The distortion and noise performance of the AD9767 can be
enhanced when it is configured for differential operation. The
common-mode error sources of both I

OUTA

and I

OUTB

can be
significantly reduced by the common-mode rejection of a trans­former or differential amplifier. These common-mode error
sources include even-order distortion products and noise. The
enhancement in distortion performance becomes more signifi­cant as the frequency content of the reconstructed waveform
increases. This is due to the first order cancellation of various
dynamic common-mode distortion mechanisms, digital feed­through and noise.

–10–

REV. B

AD9767

Performing a differential-to-single-ended conversion via a trans­former also provides the ability to deliver twice the reconstructed
signal power to the load (i.e., assuming no source termination).
Since the output currents of I

OUTA

and I

are complemen-

OUTB

tary, they become additive when processed differentially. A
properly selected transformer will allow the AD9767 to provide
the required power and voltage levels to different loads.

The output impedance of I

OUTA

and I

is determined by the

OUTB

equivalent parallel combination of the PMOS switches associ­ated with the current sources and is typically 100 kΩ in parallel
with 5 pF. It is also slightly dependent on the output voltage

OUTA

and V

(i.e., V
As a result, maintaining I

) due to the nature of a PMOS device.

OUTB

OUTA

and/or I

at a virtual ground

OUTB

via an I-V op amp configuration will result in the optimum dc
linearity. Note the INL/DNL specifications for the AD9767
are measured with I

maintained at a virtual ground via an

OUTA

op amp.

I

OUTA

and I

also have a negative and positive voltage com-

OUTB

pliance range that must be adhered to in order to achieve opti­mum performance. The negative output compliance range of
–1.0 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a break­down of the output stage and affect the reliability of the AD9767.

The positive output compliance range is slightly dependent on
the full-scale output current, I
its nominal 1.25 V for an I
I

= 2 mA. The optimum distortion performance for a

OUTFS

OUTFS

. It degrades slightly from

OUTFS

= 20 mA to 1.00 V for an

single-ended or differential output is achieved when the maxi­mum full-scale signal at I

OUTA

and I
Applications requiring the AD9767’s output (i.e., V
V

) to extend its output compliance range should size R

OUTB

does not exceed 0.5 V.

OUTB

OUTA

and/or

LOAD

accordingly. Operation beyond this compliance range will ad­versely affect the AD9767’s linearity performance and subse­quently degrade its distortion performance.

DIGITAL INPUTS

The AD9767’s digital inputs consist of two channels. For the
dual port mode, each DAC has its own dedicated 14-bit data
port, WRT line and CLK line. In the interleaved timing mode,
the function of the digital control pins changes as described in
the Interleaved Mode Timing section. The 14-bit parallel data
inputs follow straight binary coding where DB13 is the Most
Significant Bit (MSB) and DB0 is the Least Significant Bit
(LSB). I
bits are at Logic 1. I

produces a full-scale output current when all data

OUTA

produces a complementary output

OUTB

with the full-scale current split between the two outputs as a
function of the input code.

The digital interface is implemented using an edge-triggered
master slave latch. The DAC outputs are updated following
either the rising edge, or every other rising edge of the clock,
depending on whether dual or interleaved mode is being used.
The DAC outputs are designed to support a clock rate as high
as 125 MSPS. The clock can be operated at any duty cycle that
meets the specified latch pulsewidth. The setup and hold times
can also be varied within the clock cycle as long as the specified
minimum times are met, although the location of these transi­tion edges may affect digital feedthrough and distortion perfor­mance. Best performance is typically achieved when the input
data transitions on the falling edge of a 50% duty cycle clock.

DAC TIMING

The AD9767 can operate in two timing modes, dual and inter­leaved, which are described below. The block diagram in Figure
25 represents the latch architecture in the interleaved timing mode.

DUAL PORT MODE TIMING

For the following section, refer to Figure 2.

When the mode pin is at Logic 1, the AD9767 operates in dual
port mode. The AD9767 functions as two distinct DACs. Each
DAC has its own completely independent digital input and
control lines.

The AD9767 features a double buffered data path. Data enters
the device through the channel input latches. This data is then
transferred to the DAC latch in each signal path. Once the data
is loaded into the DAC latch, the analog output will settle to its
new value.

For general consideration, the WRT lines control the channel
input latches and the CLK lines control the DAC latches. Both
sets of latches are updated on the rising edge of their respective
control signals.

The rising edge of CLK should occur before or simultaneously
with the rising edge of WRT. Should the rising edge of CLK
occur after the rising edge of WRT, a 2 ns minimum delay should
be maintained from the rising edge of WRT to the rising edge of
CLK.

Timing specifications for dual port mode are given in Figures 23
and 24.

DATA IN

WRT1/WRT2

CLK1/CLK2

IOUTA

OR

IOUTB

t

S

t

H

t

LPW

t

CPW

t

PD

Figure 23. Dual Mode Timing

D1 D2 D3 D4 D5DATA IN

WRT1/WRT2

CLK1/CLK2

IOUTA

OR

IOUTB

xx

D1

D2

D3

D4

Figure 24. Dual Mode Timing

REV. B

–11–

AD9767

DVDD

DIGITAL

INPUT

INTERLEAVED MODE TIMING

For the following section, refer to Figure 25.

When the mode pin is at Logic 0, the AD9767 operates in inter­leaved mode. WRT1 now functions as IQWRT and CLK1
functions as IQCLK. WRT2 functions as IQSEL and CLK2
functions as IQRESET.

Data enters the device on the rising edge of IQWRT. The logic
level of IQSEL will steer the data to either Channel Latch 1
(IQSEL = 1) or to Channel Latch 2 (IQSEL = 0).

When IQRESET is high, IQCLK is disabled. When IQRESET
goes low, the following rising edge on IQCLK will update both
DAC latches with the data present at their inputs. In the inter­leaved mode IQCLK is divided by 2 internally. Following this
first rising edge, the DAC latches will only be updated on every
other rising edge of IQCLK. In this way, IQRESET can be used
to synchronize the routing of the data to the DACs.

As with the dual port mode, IQCLK should occur before or
simultaneously with IQWRT.

INTERLEAVED

DATA IN, PORT 1

IQWRT

IQSEL

IQCLK

IQRESET

PORT 1

INPUT

LATCH

PORT 2

INPUT

LATCH

ⴜ2

DAC1
LATCH

DAC2
LATCH

DAC1

DAC2

DEINTERLEAVED
DATA OUT

Figure 25. Latch Structure Interleaved Mode

Timing specifications for interleaved mode are given in Figures
26 and 27.

t

DATA IN

IQSEL

t

*

IQWRT

IQCLK

IOUTA

OR

IOUTB

* Applies to falling edge of IQCLK/IQWRT and IQSEL only

H

S

t

H

t

LPW

t

PD

Figure 26. Interleaved Mode Timing

INTERLEAVED

DATA

IQSEL

xx

D1 D2 D3 D4 D5

The digital inputs are CMOS-compatible with logic thresholds,
V

THRESHOLD

, set to approximately half the digital positive supply

(DVDD) or

V

THRESHOLD

= DVDD/2 (± 20%)

The internal digital circuitry of the AD9767 is capable of oper­ating over a digital supply range of 3 V to 5.5 V. As a result, the
digital inputs can also accommodate TTL levels when DVDD is
set to accommodate the maximum high level voltage of the TTL
drivers V

(MAX). A DVDD of 3 V to 3.3 V will typically

OH

ensure proper compatibility with most TTL logic families. Fig­ure 28 shows the equivalent digital input circuit for the data and
clock inputs. The sleep mode input is similar with the exception
that it contains an active pull-down circuit, thus ensuring that
the AD9767 remains enabled if this input is left disconnected.

Since the AD9767 is capable of being updated up to 125 MSPS,
the quality of the clock and data input signals are important in
achieving the optimum performance. Operating the AD9767
with reduced logic swings and a corresponding digital supply
(DVDD) will result in the lowest data feedthrough and on-chip
digital noise. The drivers of the digital data interface circuitry
should be specified to meet the minimum setup and hold times
of the AD9767 as well as its required min/max input logic level
thresholds.

Digital signal paths should be kept short and run lengths matched
to avoid propagation delay mismatch. The insertion of a low
value resistor network (i.e., 20 Ω to 100 Ω) between the AD9767
digital inputs and driver outputs may be helpful in reducing any
overshooting and ringing at the digital inputs that contribute to
digital feedthrough. For longer board traces and high data up­date rates, stripline techniques with proper impedance and
termination resistors should be considered to maintain “clean”
digital inputs.

The external clock driver circuitry should provide the AD9767
with a low jitter clock input meeting the min/max logic levels
while providing fast edges. Fast clock edges will help minimize
any jitter that will manifest itself as phase noise on a recon­structed waveform. Thus, the clock input should be driven by
the fastest logic family suitable for the application.

Note that the clock input could also be driven via a sine wave,
which is centered around the digital threshold (i.e., DVDD/2)
and meets the min/max logic threshold. This will typically result
in a slight degradation in the phase noise, which becomes more
noticeable at higher sampling rates and output frequencies.
Also, at higher sampling rates, the 20% tolerance of the digital
logic threshold should be considered since it will affect the effec­tive clock duty cycle and, subsequently, cut into the required
data setup and hold times.

IQWRT

IQCLK

IQRESET

DAC OUTPUT

PORT 1

DAC OUTPUT

PORT 2

xx

xx

D1

D2

Figure 27. Interleaved Mode Timing

D3

D4

–12–

Figure 28. Equivalent Digital Input

REV. B

AD9767

RATIO – f

OUT/fCLK

0

0.1

0

I

DVDD

– mA

5

10

15

20

25

30

35

0.2 0.3 0.4 0.5

125MSPS

100MSPS

65MSPS

25MSPS

5MSPS

RATIO – f

OUT/fCLK

0

0.1

0

I

DVDD

– mA

2

4

6

8

10

12

14

0.2 0.3 0.4 0.5

16

18

125MSPS

100MSPS

65MSPS

25MSPS

5MSPS

INPUT CLOCK AND DATA TIMING RELATIONSHIP

SNR in a DAC is dependent on the relationship between the
position of the clock edges and the point in time at which the
input data changes. The AD9767 is rising edge triggered, and so
exhibits SNR sensitivity when the data transition is close to this
edge. In general, the goal when applying the AD9767 is to make
the data transition close to the falling clock edge. This becomes
more important as the sample rate increases. Figure 29 shows
the relationship of SNR to clock placement with different
sample rates. Note that at the lower sample rates, much more
tolerance is allowed in clock placement, while much more care
must be taken at higher rates.

80

70

60

50

40

SNR – dBc

30

20

10

0

–3 –1

–4 –2

TIME OF DATA CHANGE RELATIVE TO

RISING CLOCK EDGE – ns

Figure 29. SNR vs. Clock Placement @ f

= 125 MSPS

f

CLK

0

1

23

= 20 MHz and

OUT

4

80

70

60

50

AVDD

I

40

30

20

10

0510

Figure 30. I

Conversely, I
form, f

CLOCK

show I

DVDD

(f

OUT/fCLOCK

is dependent on both the digital input wave-

DVDD

, and digital supply DVDD. Figures 31 and 32

as a function of full-scale sine wave output ratios

) for various update rates with DVDD = 5 V and

DVDD = 3 V, respectively. Note how I

15 20 25

I

OUTFS

vs. I

AVDD

OUTFS

DVDD

is reduced by more

than a factor of 2 when DVDD is reduced from 5 V to 3 V.

SLEEP MODE OPERATION

The AD9767 has a power-down function that turns off the
output current and reduces the supply current to less than 8.5 mA
over the specified supply range of 3.0 V to 5.5 V and tempera­ture range. This mode can be activated by applying a Logic
Level “1” to the SLEEP pin. The SLEEP pin logic threshold is
equal to 0.5 × AVDD. This digital input also contains an active
pull-down circuit that ensures the AD9767 remains enabled if

Figure 31. I

vs. Ratio @ DVDD = 5 V

DVDD

this input is left disconnected. The AD9767 takes less than
50 ns to power down and approximately 5 µs to power back up.

POWER DISSIPATION

The power dissipation, PD, of the AD9767 is dependent on
several factors that include: (1) The power supply voltages
(AVDD and DVDD), (2) the full-scale current output I
(3) the update rate f

, (4) and the reconstructed digital

CLOCK

OUTFS

,

input waveform. The power dissipation is directly proportional
to the analog supply current, I
rent, I

DVDD

. I

is directly proportional to I

AVDD

in Figure 30 and is insensitive to f

REV. B

, and the digital supply cur-

AVDD

OUTFS

CLOCK

.

as shown

–13–

Figure 32. I

vs. Ratio @ DVDD = 3 V

DVDD

AD9767

APPLYING THE AD9767
Output Configurations

The following sections illustrate some typical output configura­tions for the AD9767. Unless otherwise noted, it is assumed
that I

is set to a nominal 20 mA. For applications requir-

OUTFS

ing the optimum dynamic performance, a differential output
configuration is suggested. A differential output configuration
may consist of either an RF transformer or a differential op amp
configuration. The transformer configuration provides the opti­mum high frequency performance and is recommended for any
application allowing for ac coupling. The differential op amp
configuration is suitable for applications requiring dc coupling,
a bipolar output, signal gain and/or level-shifting, within the
bandwidth of the chosen op amp.

A single-ended output is suitable for applications requiring a
unipolar voltage output. A positive unipolar output voltage will
result if I

OUTA

and/or I

sized load resistor, R

is connected to an appropriately-

OUTB

, referred to ACOM. This configuration

LOAD

may be more suitable for a single-supply system requiring a
dc coupled, ground referred output voltage. Alternatively, an
amplifier could be configured as an I-V converter, thus convert-

OUTA

or I

ing I
figuration provides the best dc linearity since I
is maintained at a virtual ground. Note that I
slightly better performance than I

into a negative unipolar voltage. This con-

OUTB

OUTA

provides

OUTA

.

OUTB

or I

OUTB

DIFFERENTIAL COUPLING USING A TRANSFORMER

An RF transformer can be used to perform a differential-to­single-ended signal conversion as shown in Figure 33. A dif­ferentially coupled transformer output provides the optimum
distortion performance for output signals whose spectral con­tent lies within the transformer’s passband. An RF transformer
such as the Mini-Circuits T1-1T provides excellent rejection
of common-mode distortion (i.e., even-order harmonics) and
noise over a wide frequency range. It also provides electrical
isolation and the ability to deliver twice the power to the load.
Transformers with different impedance ratios may also be used
for impedance matching purposes. Note that the transformer
provides ac coupling only.

The center tap on the primary side of the transformer must be
connected to ACOM to provide the necessary dc current path
for both I
ing at I

OUTA

OUTA

and I

and I

. The complementary voltages appear-

OUTB

OUTB

(i.e., V

OUTA

and V

) swing symmetri-

OUTB

cally around ACOM and should be maintained with the specified
output compliance range of the AD9767. A differential resistor,

, may be inserted in applications where the output of the

R

DIFF

transformer is connected to the load, R
reconstruction filter or cable. R

is determined by the trans-

DIFF

, via a passive

LOAD

former’s impedance ratio and provides the proper source termi­nation that results in a low VSWR. Note that approximately half
the signal power will be dissipated across R

DIFF

.

DIFFERENTIAL COUPLING USING AN OP AMP

An op amp can also be used to perform a differential-to-single­ended conversion as shown in Figure 34. The AD9767 is con­figured with two equal load resistors, R
differential voltage developed across I

OUTA

, of 25 Ω. The

LOAD

and I

OUTB

is con­verted to a single-ended signal via the differential op amp con­figuration. An optional capacitor can be installed across I
and I

, forming a real pole in a low-pass filter. The addition

OUTB

OUTA

of this capacitor also enhances the op amps distortion perfor­mance by preventing the DACs high slewing output from over­loading the op amp’s input.

The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the differ­ential op amp circuit using the AD8047 is configured to provide
some additional signal gain. The op amp must operate from a
dual supply since its output is approximately ±1.0 V. A high
speed amplifier capable of preserving the differential perfor­mance of the AD9767, while meeting other system level
objectives (i.e., cost, power), should be selected. The op
amp’s differential gain, its gain setting resistor values, and
full-scale output swing capabilities should all be considered
when optimizing this circuit.

500⍀

AD9767

I

OUTA

I

OUTB

C

OPT

225⍀

225⍀

25⍀25⍀

AD8047

500⍀

Figure 34. DC Differential Coupling Using an Op Amp

The differential circuit shown in Figure 35 provides the neces­sary level-shifting required in a single supply system. In this case
AVDD, which is the positive analog supply for both the AD9767
and the op amp, is also used to level-shift the differential output
of the AD9767 to midsupply (i.e., AVDD/2). The AD8055 is a
suitable op amp for this application.

500⍀

AD9767

I

OUTA

I

OUTB

25⍀

C

OPT

225⍀

225⍀

500⍀25⍀

AD8055

1k⍀

AVDD

Figure 35. Single Supply DC Differential Coupled Circuit

AD9767

I

OUTA

I

OUTB

MINI-CIRCUITS

T1-1T

OPTIONAL
R

DIFF

R

LOAD

Figure 33. Differential Output Using a Transformer

SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT

Figure 36 shows the AD9767 configured to provide a unipolar
output range of approximately 0 V to +0.5 V for a doubly termi­nated 50 Ω cable since the nominal full-scale current, I
20 mA flows through the equivalent R
R

represents the equivalent load resistance seen by I

LOAD

. The unused output (I

I

OUTB

OUTA

or I

ACOM directly or via a matching R

of 25 Ω. In this case,

LOAD

) can be connected to

OUTB

. Different values of

LOAD

OUTFS

–14–

, of

or

OUTA

REV. B

I

OUTFS

and R

can be selected as long as the positive compli-

LOAD

ance range is adhered to. One additional consideration in this
mode is the integral nonlinearity (INL) as discussed in the
Analog Output section of this data sheet. For optimum INL
performance, the single-ended, buffered voltage output configu­ration is suggested.

AD9767

I

OUTA

I

OUTB

I

OUTFS

= 20mA

25⍀

50⍀

V

OUTA

= 0 TO +0.5V

50⍀

Figure 36. 0 V to 0.5 V Unbuffered Voltage Output

AD9767

One factor that can measurably affect system performance is the
ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution.
This is referred to as the Power Supply Rejection Ratio. For dc
variations of the power supply, the resulting performance of the
DAC directly corresponds to a gain error associated with the
DAC’s full-scale current, I
common in applications where the power distribution is gener­ated by a switching power supply. Typically, switching power
supply noise will occur over the spectrum from tens of kHz to
several MHz. The PSRR vs. frequency of the AD9767 AVDD
supply over this frequency range is shown in Figure 38.

90

. AC noise on the dc supplies is

OUTFS

SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
CONFIGURATION

Figure 37 shows a buffered single-ended output configuration
in which the op amp U1 performs an I-V conversion on the
AD9767 output current. U1 maintains I

OUTA

(or I

OUTB

) at a
virtual ground, thus minimizing the nonlinear output impedance
effect on the DAC’s INL performance as discussed in the
Analog Output section. Although this single-ended configura­tion typically provides the best dc linearity performance, its ac
distortion performance at higher DAC update rates may be
limited by U1’s slewing capabilities. U1 provides a negative
unipolar output voltage and its full-scale output voltage is sim­ply the product of R

and I

FB

. The full-scale output should

OUTFS

be set within U1’s voltage output swing capabilities by scaling

and/or RFB. An improvement in ac distortion perfor-

I

OUTFS

mance may result with a reduced I

since the signal current

OUTFS

U1 will be required to sink will be subsequently reduced.

C

OPT

R

FB

200⍀

I

= 10mA

AD9767

I

OUTA

I

OUTB

OUTFS

200⍀

U1

V

= I

OUTFS

ⴛ R

FB

OUT

Figure 37. Unipolar Buffered Voltage Output

POWER AND GROUNDING CONSIDERATIONS, POWER
SUPPLY REJECTION

Many applications seek high speed and high performance under
less than ideal operating conditions. In these application cir­cuits, the implementation and construction of the printed circuit
board is as important as the circuit design. Proper RF tech­niques must be used for device selection, placement and rout­ing, as well as power supply bypassing and grounding to ensure
optimum performance. Figures 43 to 50 illustrate the recom­mended printed circuit board ground, power and signal plane
layouts which are implemented on the AD9767 evaluation board.

85

80

PSRR – dB

75

70

0.2

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
FREQUENCY – MHz

Figure 38. Power Supply Rejection Ratio of AD9767

Note that the units in Figure 38 are given in units of (amps out/
volts in). Noise on the analog power supply has the effect of
modulating the internal current sources, and therefore the out­put current. The voltage noise on AVDD, therefore, will be
added in a nonlinear manner to the desired I

. PSRR is very

OUT

code-dependent thus producing mixing effects which can modu­late low frequency power supply noise to higher frequencies.
Worst case PSRR for either one of the differential DAC outputs
will occur when the full-scale current is directed towards that
output. As a result, the PSRR measurement in Figure 38 repre­sents a worst case condition in which the digital inputs remain
static and the full-scale output current of 20 mA is directed to
the DAC output being measured.

An example serves to illustrate the effect of supply noise on the
analog supply. Suppose a switching regulator with a switching
frequency of 250 kHz produces 10 mV of noise and, for simplic­ity sake (i.e., ignore harmonics), all of this noise is concentrated
at 250 kHz. To calculate how much of this undesired noise will
appear as current noise superimposed on the DAC’s full-scale
current, I
Figure 38 at 250 kHz. To calculate the PSRR for a given R

, one must determine the PSRR in dB using

OUTFS

LOAD

,

such that the units of PSRR are converted from A/V to V/V,
adjust the curve in Figure 38 by the scaling factor 20 × Log

). For instance, if R

(R

LOAD

is 50 Ω, the PSRR is reduced

LOAD

by 34 dB (i.e., PSRR of the DAC at 250 kHz, which is 85 dB in
Figure 38, becomes 51 dB V

OUT/VIN

).

REV. B

–15–

AD9767

Proper grounding and decoupling should be a primary objective
in any high speed, high resolution system. The AD9767 features
separate analog and digital supply and ground pins to optimize
the management of analog and digital ground currents in a
system. In general, AVDD, the analog supply, should be de­coupled to ACOM, the analog common, as close to the chip as
physically possible. Similarly, DVDD, the digital supply, should
be decoupled to DCOM as close to the chip as physically possible.

For those applications that require a single +5 V or +3 V supply
for both the analog and digital supplies, a clean analog supply
may be generated using the circuit shown in Figure 39. The
circuit consists of a differential LC filter with separate power
supply and return lines. Lower noise can be attained by using
low ESR type electrolytic and tantalum capacitors.

TTL/CMOS

LOGIC

CIRCUITS

+5V

POWER SUPPLY

FERRITE

BEADS

ELECTROLYTIC

100␮F

CERAMIC

AVDD

10–22␮F 0.1␮F

ACOM

TANTALUM

Figure 39. Differential LC Filter for Single +5 V and +3 V
Applications

–20

–30

–40

–50

–60

–70

dBm

–80

–90

–100

–110

–120

0.685 0.705 0.725 0.745 0.765 0.785 0.805 0.825

0.665
FREQUENCY – MHz

Figure 40a. Notch in Missing Bin at 750 kHz Is Down
>60 dB (Peak Amplitude = 0 dBm)

–20

–40

–60

dBm

–80

APPLICATION
VDSL Applications Using the AD9767

Very High Frequency Digital Subscriber Line (VDSL) technol­ogy is growing rapidly in applications requiring data transfer
over relatively short distances. By using QAM modulation and
transmitting the data in Discrete Multiple Tones (DMT), high
data rates can be achieved.

As with other multitone applications, each VDSL tone is ca­pable of transmitting a given number of bits, depending on the
signal-to-noise ratio (SNR) in a narrow band around that tone.
For a typical VDSL application, the tones are evenly spaced
over the range of several kHz to 10 MHz. At the high frequency
end of this range, performance is generally limited by cable
characteristics and environmental factors, such as external inter­ferers. Performance at the lower frequencies is much more de­pendent on the performance of the components in the signal
chain. In addition to in-band noise, intermodulation from other
tones can also potentially interfere with the data recovery for a
given tone. The two graphs in Figure 40 represent a 500 tone
missing bin test vector, with frequencies evenly spaced from
400 Hz to 10 MHz. This test is very commonly done to deter­mine if distortion will limit the number of bits which can be
transmitted in a tone. The test vector has a series of missing
tones around 750 kHz, which is represented in Figure 40a, and
a series of missing tones around 5 MHz, which is represented in
Figure 40b. In both cases, the spurious free dynamic range
(SFDR) between the transmitted tones and the empty bins is
greater than 60 dB.

–100

–120

4.85 4.90 4.95 5.00 5.05 5.10 5.15
FREQUENCY – MHz

Figure 40b. Notch in Missing Bin at 5 MHz Is Down
>60 dB (Peak Amplitude = 0 dBm)

CDMA

Carrier Division Multiple Access, or CDMA, is an air transmit/
receive scheme where the signal in the transmit path is modu­lated with a pseudorandom digital code (sometimes referred to
as the spreading code). The effect of this is to spread the trans­mitted signal across a wide spectrum. Similar to a DMT wave­form, a CDMA waveform containing multiple subscribers can
be characterized as having a high peak to average ratio (i.e.,
crest factor), thus demanding highly linear components in the
transmit signal path. The bandwidth of the spectrum is defined
by the CDMA standard being used, and in operation is imple­mented by using a spreading code with particular characteristics.

Distortion in the transmit path can lead to power being trans­mitted out of the defined band. The ratio of power transmitted
in-band to out-of-band is often referred to as Adjacent Channel
Power (ACP). This is a regulatory issue due to the possibility of
interference with other signals being transmitted by air. Regula­tory bodies define a spectral mask outside of the transmit band,
and the ACP must fall under this mask. If distortion in the
transmit path causes the ACP to be above the spectral mask,
then filtering, or different component selection, is needed to
meet the mask requirements.

–16–

REV. B

AD9767

Figure 41 shows the AD9767, when used with the AD8346,
reconstructing a wideband CDMA signal at 2.4 GHz. The
baseband signal is being sampled at 65 MSPS and has a chip
rate of 8M chips.

–30

–40

–50

–60

==

–70

–80

dB

–90

–100

–110

c11 cu1

–120

–130

CENTER 2.4GHz 3MHz SPAN 30MHz

c11

C0

FREQUENCY

cu1

C0

Figure 41. CDMA Signal, 8 M Chips Sampled at 65 MSPS,
Recreated at 2.4 GHz Adjacent Channel Power > 60 dBm

DVDD AVDD

CLK1

FSADJ1

(“Q DAC”)

FSADJ2

AD9767

(“I DAC”)

INPUT

LATCHES

INPUT

LATCHES

REFIO SLEEP

0.1␮F

DAC

LATCHES

DAC

LATCHES

CLK2

U1

DAC

U2

DAC

ACOM

IOUTA

IOUTB

QOUTA

QOUTB

DCOM

50⍀

50⍀

500⍀

500⍀

50⍀

500⍀

50⍀

R

CAL

220⍀

R

SET1

2k⍀

I DATA

INPUT

WRT1

WRT2

Q DATA

INPUT

R

SET2

1.9k⍀

Figure 42 shows an example of the AD9767 used in a W-CDMA
transmitter application using the AD6122 CDMA 3 V IF sub­system. The AD6122 has functions, such as external gain con­trol and low distortion characteristics, needed for the superior
Adjacent Channel Power (ACP) requirements of W-CDMA.

3V

500⍀

500⍀

500⍀ 500⍀

LOIPP
LOIPN

500⍀

GAIN

CONTROL

IIPP

IIPN

ⴜ

IIQP

IIQN

REFIN

VGAIN

2

CONTROL

FACTOR

PHASE

SPLITTER

GAIN

SCALE

AD6122

TEMPERATURE

COMPENSATION

MODOPP

MODOPN

V

CC

V

CC

REV. B

TXOPP

TXOPN

Figure 42. CDMA Transmit Application Using AD9767 and AD6122

–17–

AD9767

EVALUATION BOARD
General Description

The AD9767-EB is an evaluation board for the AD9767 14-bit
dual D/A converter. Careful attention to layout and circuit
design, combined with a prototyping area, allow the user to
easily and effectively evaluate the AD9767 in any application
where high resolution, high speed conversion is required.

This board allows the user the flexibility to operate the AD9767
in various configurations. Possible output configurations include

POWER DECOUPLING AND INPUT CLOCKS

RED

DVDDIN

BAN-JACK

TP10

B1

B2

L1

BEAD

2

1

C9
10␮F
25V

BLK

TP37

DVDD

BLK

TP38

BLK

TP39

B3

AVDDIN

BAN-JACK

B4

transformer coupled, resistor terminated, and single and differ­ential outputs. The digital inputs can be used in dual port or
interleaved mode, and are designed to be driven from various
word generators, with the on-board option to add a resistor
network for proper load termination. When operating the
AD9767, best performance is obtained by running the Digital
Supply (DVDD) at +3 V and the Analog Supply (AVDD) at +5 V.

RED
TP11

L2

BEAD

1

2

C10
10␮F
25V

BLK
TP40

AVDD

BLK

TP41

BLK

TP42

DVDD

2

1

C7

0.1␮F

1

C8

0.01␮F

2

WRT1IN

IQWRT

CLK1IN

IQCLK

CLK2IN

RESET

WRT2IN

IQSEL

RCOM

RCOM

BAN-JACK

S1

S2

S3

S4

SLEEP

R1
22⍀

21

INP1

R1
22⍀

21

INP23

WHT
TP29

DGND;3,4,5

WHT
TP30

DGND;3,4,5

WHT
TP31

DGND;3,4,5

WHT
TP32

DGND;3,4,5

WHT
TP33

R2
22⍀

3

INP2

R2
22⍀

3

INP24

INP3

INP25

1

2

R3
22⍀

4

R3
22⍀

4

R13
50⍀

1

R1
50⍀

2

INP4

INP26

R4
22⍀

5

R4
22⍀

5

1

2

INP5

INP27

R2
50⍀

R5
22⍀

6

R5
22⍀

6

TP43

DGND

BLK

DCLKIN1 DCLKIN2

1

JP16

JP5

AB

2

1

3

IC

JP4

A

B

2

1

3

IC

JP3

A

B

2

1

3

INP7

INP29

1

2

8

8

R4
50⍀

R7
22⍀

R7
22⍀

IC

INP8

INP30

R8
22⍀

9

R8
22⍀

9

1

2

INP6

INP28

7

7

R3
50⍀

R6
22⍀

R6
22⍀

BAN-JACK

JP9

2

A

B

RP16

R9
22⍀

10

RP10

R9
22⍀

10

TP44

AGND

BLK

3

DVDD

JP6

2

1

3

A

B

JP2

10

PRE

CLR

14

U2

Q

Q

DGND;8
DVDD;16

9

7

TSSOP112

11

J

13

CLK

12

K

JP1

DVDD

4

PRE

15

A

U1

CLR

2

JP7

Q

Q

DGND;8
DVDD;16

B

3

5

6

TSSOP112

3

J

1

CLK

2

KDVDD

1

/2 CLOCK DIVIDER

WRT1

CLK1

CLK2

WRT2

SLEEP

RP9

R2

RCOM

RCOM

INP9

INP31

21

21

R1
22⍀

R1
22⍀

INP10

INP32

22⍀

3

R2
22⍀

3

INP11

INP33

4

4

R3
22⍀

R3
22⍀

INP12

INP34

R4
22⍀

5

R4
22⍀

5

INP13

INP35

R5
22⍀

6

R5
22⍀

6

INP14

INP36

7

7

R6
22⍀

R6
22⍀

R7
22⍀

8

R7
22⍀

8

9

INCK1

9

INCK2

R8
22⍀

R8
22⍀

R9
22⍀

10

RP15

R9
22⍀

10

Figure 43. Power Decoupling and Clocks on AD9767 Evaluation Board

–18–

REV. B

2 P1

4 P1

6 P1

8 P1

10 P1

12 P1

14 P1

16 P1

18 P1

20 P1

22 P1

24 P1

26 P1

28 P1

30 P1

32 P1

34 P1

36 P1

38 P1

40 P1

2 P2

4 P2

6 P2

8 P2

10 P2

12 P2

14 P2

16 P2

18 P2

20 P2

22 P2

24 P2

26 P2

28 P2

30 P2

32 P2

34 P2

36 P2

38 P2

40 P2

P1 1

P1 3

P1 5

P1 7

P1 9

P1 11

P1 13

P1 15

P1 17

P1 19

P1 21

P1 23

P1 25

P1 27

P1 29

P1 31

P1 33

P1 35

P1 37

P1 39

P2 1

P2 3

P2 5

P2 7

P2 9

P2 11

P2 13

P2 15

P2 17

P2 19

P2 21

P2 23

P2 25

P2 27

P2 29

P2 31

P2 33

P2 35

P2 37

P2 39

INP1

INP2

INP3

INP4

INP5

INP6

INP7

INP8

INP9

INP10

INP11

INP12

INP13

INP14

INCK1

INP23

INP24

INP25

INP26

INP27

INP28

INP29

INP30

INP31

INP32

INP33

INP34

INP35

INP36

INCK2

RP5, 10⍀

116

RP5, 10⍀

314

RP5, 10⍀

512

RP5, 10⍀

710

RP6, 10⍀

116

RP6, 10⍀

314

RP6, 10⍀

512

RP7, 10⍀

116

RP7, 10⍀

314

RP7, 10⍀

512

RP7, 10⍀

710

RP8, 10⍀

116

RP8, 10⍀

314

RP8, 10⍀

512

RP3

RCOM

DVDD

RP5, 10⍀

215

RP5, 10⍀

4

RP5, 10⍀

6

RP5, 10⍀

8

RP6, 10⍀

2

RP6, 10⍀

4

RP6, 10⍀

6

RP6, 10⍀

89

RP4

RCOM

DVDD

RP7, 10⍀

215

RP7, 10⍀

4

RP7, 10⍀

6

RP7, 10⍀

8

RP8, 10⍀

2

RP8, 10⍀

4

RP8, 10⍀

6

RP8, 10⍀

89

R1 R9

22⍀

1

13

11

9

15

13

11

R1 R9

22⍀

1

13

11

9

15

13

11

DIGITAL INPUT SIGNAL CONDITIONING

RP1

R1 R9

RCOM

22⍀

RP5, 10⍀

710

1098765432

1098765432

SPARES

1

DVDD

RP2

RCOM

22⍀

1

DVDD

RP8, 10⍀

710

R1 R9

1098765432

1098765432

RP13

R1 R9

RCOM

33⍀

1

RP14

R1 R9

RCOM

33⍀

1

AD9767

RP11

R1 R9

RCOM

33⍀

1098765432

1

RP12

R1 R9

RCOM

33⍀

1098765432

1

1098765432

DUTP1

DUTP2

DUTP3

DUTP4

DUTP5

DUTP6

DUTP7

DUTP8

DUTP9

DUTP10

DUTP11

DUTP12

DUTP13

DUTP14

DCLKIN1

1098765432

DUTP23

DUTP24

DUTP25

DUTP26

DUTP27

DUTP28

DUTP29

DUTP30

DUTP31

DUTP32

DUTP33

DUTP34

DUTP35

DUTP36

DCLKIN2

REV. B

Figure 44. Digital Input Signal Conditioning

–19–

AD9767

DUTP1

DUTP2

DUTP3

DUTP4

DUTP5

DUTP6

DUTP7

DUTP8

DUTP9

DUTP10

DUTP11

DUTP12

DUTP13

DUTP14

WRT1

CLK1

CLK2

WRT2

DUTP23

DUTP24

1

C1
VAL

2

1

DB13P1MSB

2

DB12P1

3

DB11P1

4

DB10P1

5

DB9P1

6

DB8P1

7

DB7P1

8

DB6P1

9

DB5P1

10

DB4P1

11

DB3P1

12

DB2P1

13

DB1P1

14

DB0P1

15

DCOM1

16

DVDD1

17

WRT1

18

CLK1

19

CLK2

20

WRT2

21

DCOM2

22

DVDD2

23

DB13P2MSB

24

DB12P2

1

C2

0.01␮F

2

U2

1

C3

0.1␮F

2

DVDD

MODE

AVDD

IA1

IB1

FSADJ1

REFIO

GAINCTRL

FSADJ2

IB2

IA2

ACOM

SLEEP

DB0P2

DB1P2

DB2P2

DB3P2

DB4P2

DB5P2

DB6P2

DB7P2

DB8P2

DB9P2

DB10P2

DB11P2

DUT AND ANALOG OUTPUT SIGNAL CONDITIONING

DVDD

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

AVDD

MODE

JP8

A

ACOM

JP15

2

1

3

A

B

2

3

B

10pF

SLEEP

10pF

DUTP36

C15

1

R5
50⍀

2

2

C4

10pF

1

2

10pF

1

1

R7
50⍀

2

1

R6
50⍀

2

2

C5

1

2

C6

1

1

R8
50⍀

2

DUTP35

DUTP34

DUTP33

DUTP32

DUTP31

DUTP30

DUTP29

DUTP28

DUTP27

DUTP26

DUTP25

1

1

C11

C12

1␮F

2

0.01␮F

2

1

2

C13

0.1␮F

AVDD

NC = 5

3

2

R11
VAL

16

TP45
WHT

WHT
TP46

R12
VAL

R9

1.92k⍀

12

C16

22nF

2

1

C17

22nF

2

1

R10

1.92k⍀

12

NC = 5

3

2

16

BL1

1:1

T1

BL2

R15

256⍀

12

R14

256⍀

12

JP10

BL3

1:1

T2

BL4

4

4

TP35
WHT

TP34
WHT

REFIO

2

AGND;3,4,5

TP36
WHT

1

C14

0.1␮F

AGND;3,4,5

S6
OUT1

S11
OUT2

Figure 45. AD9767 and Output Signal Conditioning

–20–

REV. B

AD9767

Figure 46. Assembly, Top Side

REV. B

–21–

AD9767

Figure 47. Assembly, Bottom Side

–22–

REV. B

AD9767

REV. B

Figure 48. Layer 1, Top Side

–23–

AD9767

Figure 49. Layer 2, Ground Plane

–24–

REV. B

AD9767

REV. B

Figure 50. Layer 3, Power Plane

–25–

AD9767

Figure 51. Layer 4, Bottom Side

–26–

REV. B

(

)

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

48-Lead Thin Plastic Quad Flatpack

(ST-48)

0.063 (1.60)

0.030 (0.75)

0.018 (0.45)

MAX

0.354 (9.00) BSC SQ

48

1

AD9767

37

36

COPLANARITY

0.003 (0.08)

0.004 (0.09)

0.008 (0.2)

0ⴗ
MIN

7ⴗ
0ⴗ

(PINS DOWN)

12

13

0.019 (0.5)
BSC

0.006 (0.15)

0.002

0.05

TOP VIEW

0.011 (0.27)

0.006 (0.17)

SEATING
PLANE

24

25

0.276
(7.00)

BSC

SQ

0.057 (1.45)

0.053 (1.35)

C3583a–0–2/00 (rev. B) 00620

REV. B

PRINTED IN U.S.A.

–27–