Analog Devices AD9764ARU, AD9764AR, AD9764-EB Datasheet

a

(

)

14-Bit, 125 MSPS

TxDAC

®

D/A Converter

AD9764*

FEATURES
Member of Pin-Compatible TxDAC Product Family
125 MSPS Update Rate
14-Bit Resolution
Excellent SFDR and IMD
Differential Current Outputs: 2 mA to 20 mA
Power Dissipation: 190 mW @ 5 V to 45 mW @ 3 V
Power-Down Mode: 25 mW @ 5 V
On-Chip 1.20 V Reference
Single +5 V or +3 V Supply Operation
Packages: 28-Lead SOIC and TSSOP
Edge-Triggered Latches

APPLICATIONS
Communication Transmit Channel:

Basestations
ADSL/HFC Modems

Instrumentation

PRODUCT DESCRIPTION

The AD9764 is the 14-bit resolution member of the TxDAC
series of high performance, low power CMOS digital-to-analog
converters (DACs). The TxDAC

family, which consists of pin
compatible 8-, 10-, 12-, and 14-bit DACs, is specifically opti­mized for the transmit signal path of communication systems.
All of the devices share the same interface options, small outline
package and pinout, providing an upward or downward compo­nent selection path based on performance, resolution and cost.
The AD9764 offers exceptional ac and dc performance while
supporting update rates up to 125 MSPS.

The AD9764’s flexible single-supply operating range of 2.7 V to

5.5 V and low power dissipation are well suited for portable and
low power applications. Its power dissipation can be further
reduced to a mere 45 mW with a slight degradation in performance
by lowering the full-scale current output. Also, a power-down
mode reduces the standby power dissipation to approximately
25 mW.

The AD9764 is manufactured on an advanced CMOS process.
A segmented current source architecture is combined with a
proprietary switching technique to reduce spurious components
and enhance dynamic performance. Edge-triggered input
latches and a 1.2 V temperature compensated bandgap refer­ence have been integrated to provide a complete monolithic
DAC solution. Flexible supply options support +3 V and +5 V
CMOS logic families.

The AD9764 is a current-output DAC with a nominal full-scale

output current of 20 mA and > 100 kΩ output impedance.

TxDAC is a registered trademark of Analog Devices, Inc.
*Patent pending.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

FUNCTIONAL BLOCK DIAGRAM

+5V

0.1mF

50pF

LATCHES

COMP1

CURRENT

SOURCE

ARRAY

SWITCHES

AVDD ACOM

AD9764

LSB

DB13–DB0

COMP2

I

OUTA

I

OUTB

0.1mF

R

SET

CLOCK

0.1mF

+5V

REFLO

+1.20V REF

REFIO
FS ADJ

DVDD
DCOM

CLOCK

SLEEP

DIGITAL DATA INPUTS

SEGMENTED

SWITCHES

Differential current outputs are provided to support single­ended or differential applications. Matching between the two
current outputs ensures enhanced dynamic performance in a
differential output configuration. The current outputs may be
tied directly to an output resistor to provide two complemen­tary, single-ended voltage outputs or fed directly into a trans­former. The output voltage compliance range is 1.25 V.

The on-chip reference and control amplifier are configured for
maximum accuracy and flexibility. The AD9764 can be driven
by the on-chip reference or by a variety of external reference
voltages. The internal control amplifier, which provides a wide
(>10:1) adjustment span, allows the AD9764 full-scale current
to be adjusted over a 2 mA to 20 mA range while maintaining
excellent dynamic performance. Thus, the AD9764 may operate
at reduced power levels or be adjusted over a 20 dB range to
provide additional gain ranging capabilities.

The AD9764 is available in 28-lead SOIC and TSSOP packages.
It is specified for operation over the industrial temperature range.

PRODUCT HIGHLIGHTS

1. The AD9764 is a member of the TxDAC product family that
provides an upward or downward component selection path
based on resolution (8 to 14 bits), performance and cost.

2. Manufactured on a CMOS process, the AD9764 uses a pro­prietary switching technique that enhances dynamic perfor­mance beyond that previously attainable by higher power/cost
bipolar or BiCMOS devices.

3. On-chip, edge-triggered input CMOS latches readily interface
to +3 V and +5 V CMOS logic families. The AD9764 can
support update rates up to 125 MSPS.

4. A flexible single-supply operating range of 2.7 V to 5.5 V, and
a wide full-scale current adjustment span of 2 mA to 20 mA,
allows the AD9764 to operate at reduced power levels.

5. The current output(s) of the AD9764 can be easily config­ured for various single-ended or differential circuit topologies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

AD9764–SPECIFICATIONS

DC SPECIFICATIONS

(T

to T

MIN

, AVDD = +5 V, DVDD = +5 V, I

MAX

= 20 mA, unless otherwise noted)

OUTFS

Parameter Min Typ Max Units

RESOLUTION 14 Bits

DC ACCURACY

1

Integral Linearity Error (INL)

= +25°C –4.5 ±2.5 +4.5 LSB

T

A

to T

T

MIN

MAX

–6.5 +6.5 LSB

Differential Nonlinearity (DNL)

= +25°C –2.5 ±1.5 +2.5 LSB

T

A

T

MIN

to T

MAX

–4.5 +4.5 LSB

ANALOG OUTPUT

Offset Error –0.025 +0.025 % of FSR
Gain Error
Gain Error
Full-Scale Output Current

(Without Internal Reference) –2 ±1 +2 % of FSR
(With Internal Reference) –7 ±1 +7 % of FSR

2

2.0 20.0 mA

Output Compliance Range –1.0 1.25 V

Output Resistance 100 kΩ

Output Capacitance 5 pF

REFERENCE OUTPUT

Reference Voltage 1.08 1.20 1.32 V
Reference Output Current

3

100 nA

REFERENCE INPUT

Input Compliance Range 0.1 1.25 V

Reference Input Resistance 1 MΩ

Small Signal Bandwidth (w/o C

COMP1

4

)

1.4 MHz

TEMPERATURE COEFFICIENTS

Offset Drift 0 ppm of FSR/°C

Gain Drift
Gain Drift

(Without Internal Reference) ±50 ppm of FSR/°C
(With Internal Reference) ±100 ppm of FSR/°C

Reference Voltage Drift ±50 ppm/°C

POWER SUPPLY

Supply Voltages

AVDD

5

2.7 5.0 5.5 V

DVDD 2.7 5.0 5.5 V
Analog Supply Current (I
Digital Supply Current (I
Supply Current Sleep Mode (I
Power Dissipation
Power Dissipation
Power Dissipation

6

(5 V, I

7

(5 V, I

7

(3 V, I

Power Supply Rejection Ratio

)2530mA

AVDD

6

)

DVDD

OUTFS

OUTFS

OUTFS

) 5.0 8.5 mA

AVDD

= 20 mA) 133 170 mW
= 20 mA) 190 mW
= 2 mA) 45 mW

8

—AVDD –0.4 +0.4 % of FSR/V

1.5 4 mA

Power Supply Rejection Ratio8—DVDD –0.025 +0.025 % of FSR/V

OPERATING RANGE –40 +85 °C

NOTES

1

Measured at I

2

Nominal full-scale current, I

3

Use an external buffer amplifier to drive any external load.

4

Reference bandwidth is a function of external cap at COMP1 pin and signal level.

5

For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance.

6

Measured at f

7

Measured as unbuffered voltage output with I

8

±5% Power supply variation.

Specifications subject to change without notice.

, driving a virtual ground.

OUTA

= 25 MSPS and f

CLOCK

, is 32 × the I

OUTFS

= 1.0 MHz.

OUT

current.

REF

= 20 mA and 50 Ω R

OUTFS

LOAD

at I

OUTA

and I

OUTB

, f

= 100 MSPS and f

CLOCK

= 40 MHz.

OUT

REV. B–2–

AD9764

(T

to T

, AVDD = +5 V, DVDD = +5 V, I

MAX

DYNAMIC SPECIFICATIONS

MIN

50 ⍀ Doubly Terminated, unless otherwise noted)

Parameter Min Typ Max Units

DYNAMIC PERFORMANCE

Maximum Output Update Rate (f
Output Settling Time (t
Output Propagation Delay (t

) (to 0.1%)

ST

)1ns

PD

Glitch Impulse 5 pV-s
Output Rise Time (10% to 90%)
Output Fall Time (10% to 90%)
Output Noise (I
Output Noise (I

= 20 mA) 50 pA/√Hz

OUTFS

= 2 mA) 30 pA/√Hz

OUTFS

) 125 MSPS

CLOCK

1

1

1

AC LINEARITY

Spurious-Free Dynamic Range to Nyquist

f

= 25 MSPS; f

CLOCK

= 1.00 MHz

OUT

0 dBFS Output

= +25°C 75 82 dBc

T

A

to T

T

MIN

MAX

73 dBc
–6 dBFS Output 85 dBc
–12 dBFS Output 77 dBc
–18 dBFS Output 70 dBc

= 50 MSPS; f

f

CLOCK

= 50 MSPS; f

f

CLOCK

= 50 MSPS; f

f

CLOCK

= 50 MSPS; f

f

CLOCK

= 1.00 MHz 80 dBc

OUT

= 2.51 MHz 77 dBc

OUT

= 5.02 MHz 70 dBc

OUT

= 20.2 MHz 58 dBc

OUT

Spurious-Free Dynamic Range within a Window

= 25 MSPS; f

f

CLOCK

= +25°C 78 89 dBc

T

A

to T

T

f

CLOCK

f

CLOCK

MIN

MAX

= 50 MSPS; f
= 100 MSPS; f

= 1.00 MHz; 2 MHz Span

OUT

76 dBc

= 5.02 MHz; 2 MHz Span 84 dBc

OUT

= 5.04 MHz; 4 MHz Span 84 dBc

OUT

Total Harmonic Distortion

= 25 MSPS; f

f

CLOCK

= +25°C –78 –74 dBc

T

A

to T

T

f

CLOCK

f

CLOCK

MIN

MAX

= 50 MHz; f
= 100 MHz; f

= 1.00 MHz

OUT

= 2.00 MHz –75 dBc

OUT

= 2.00 MHz –75 dBc

OUT

Multitone Power Ratio (Eight Tones at 110 kHz Spacing)

= 20 MSPS; f

f

CLOCK

= 2.00 MHz to 2.99 MHz

OUT

0 dBFS Output 73 dBc
–6 dBFS Output 76 dBc
–12 dBFS Output 73 dBc
–18 dBFS Output 64 dBc

NOTES

1

Measured single-ended into 50 Ω load.

Specifications subject to change without notice.

= 20 mA, Differential Transformer Coupled Output,

OUTFS

35 ns

2.5 ns

2.5 ns

–72 dBc

REV. B –3–

AD9764

WARNING!

ESD SENSITIVE DEVICE

DIGITAL SPECIFICATIONS

Parameter Min Typ Max Units

DIGITAL INPUTS

Logic “1” Voltage @ DVDD = +5 V 3.5 5 V
Logic “1” Voltage @ DVDD = +3 V 2.1 3 V
Logic “0” Voltage @ DVDD = +5 V 0 1.3 V
Logic “0” Voltage @ DVDD = +3 V 0 0.9 V

Logic “1” Current –10 +10 µA
Logic “0” Current –10 +10 µA

Input Capacitance 5 pF
Input Setup Time (tS) 2.0 ns
Input Hold Time (t
Latch Pulsewidth (t

Specifications subject to change without notice.

) 1.5 ns

H

) 3.5 ns

LPW

DB0–DB13

t

S

CLOCK

t

PD

IOUTA

OR

IOUTB

Figure 1. Timing Diagram

ABSOLUTE MAXIMUM RATINGS*

With

Parameter Respect to Min Max Units

AVDD ACOM –0.3 +6.5 V
DVDD DCOM –0.3 +6.5 V
ACOM DCOM –0.3 +0.3 V
AVDD DVDD –6.5 +6.5 V
CLOCK, SLEEP DCOM –0.3 DVDD + 0.3 V
Digital Inputs DCOM –0.3 DVDD + 0.3 V
I

OUTA

, I

OUTB

ACOM –1.0 AVDD + 0.3 V
COMP1, COMP2 ACOM –0.3 AVDD + 0.3 V
REFIO, FSADJ ACOM –0.3 AVDD + 0.3 V
REFLO ACOM –0.3 +0.3 V

Junction Temperature +150 °C
Storage Temperature –65 +150 °C

Lead Temperature

(10 sec) +300 °C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.

t

H

t

LPW

t

ST

0.1%

0.1%

ORDERING GUIDE

Temperature Package Package

Model Range Description Options*

AD9764AR –40°C to +85°C 28-Lead 300 mil SOIC R-28
AD9764ARU –40°C to +85°C 28-Lead TSSOP RU-28

AD9764-EB Evaluation Board

*R = Small Outline IC, RU = TSSOP.

THERMAL CHARACTERISTICS
Thermal Resistance

28-Lead 300 mil SOIC

= 71.4°C/W

θ

JA

= 23°C/W

θ

JC

28-Lead TSSOP

= 97.9°C/W

θ

JA

= 14.0°C/W

θ

JC

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9764 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–4–

REV. B

PIN CONFIGURATION

AD9764

(MSB) DB13

1
2

DB12
DB11

3

DB10

4

DB9

5
6

DB8
DB7

7
8

DB6

9

DB5

10

DB4

11

DB3
DB2

12

DB1

13

DB0

14

NC = NO CONNECT

AD9764

TOP VIEW

(Not to Scale)

28
27

26
25

24
23

22
21

20
19
18

17
16

15

CLOCK
DVDD

DCOM
NC

AVDD
COMP2

I

OUTA

I

OUTB

ACOM
COMP1
FS ADJ

REFIO
REFLO

SLEEP

PIN FUNCTION DESCRIPTIONS

Pin No. Name Description

1 DB13 Most Significant Data Bit (MSB).
2–13 DB12–DB1 Data Bits 1–12.
14 DB0 Least Significant Data Bit (LSB).
15 SLEEP Power-Down Control Input. Active High. Contains active pull-down circuit; it may be left unterminated if

not used.
16 REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference.
17 REFIO Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to

AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM).

Requires 0.1 µF capacitor to ACOM when internal reference activated.

18 FS ADJ Full-Scale Current Output Adjust.

19 COMP1 Bandwidth/Noise Reduction Node. Add 0.1 µF to AVDD for optimum performance.

20 ACOM Analog Common.
21 I
22 I

OUTB

OUTA

Complementary DAC Current Output. Full-scale current when all data bits are 0s.

DAC Current Output. Full-scale current when all data bits are 1s.

23 COMP2 Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 µF capacitor.

24 AVDD Analog Supply Voltage (+2.7 V to +5.5 V).
25 NC No Internal Connection.
26 DCOM Digital Common.
27 DVDD Digital Supply Voltage (+2.7 V to +5.5 V).
28 CLOCK Clock Input. Data latched on positive edge of clock.

REV. B

–5–

AD9764

DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)

Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.

Differential Nonlinearity (or DNL)

DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input
code.

Offset Error

The deviation of the output current from the ideal of zero is
called offset error. For I
inputs are all 0s. For I

, 0 mA output is expected when the

OUTA

, 0 mA output is expected when all

OUTB

inputs are set to 1s.

Gain Error

The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.

Output Compliance Range

The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.

Temperature Drift

Temperature drift is specified as the maximum change from the

ambient (+25°C) value to the value at either T

MIN

or T

MAX

. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree C. For reference drift, the drift is
reported in ppm per degree C.

Power Supply Rejection

The maximum change in the full-scale output as the supplies
are varied over a specified range.

Settling Time

The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.

Glitch Impulse

Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.

Spurious-Free Dynamic Range

The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.

Total Harmonic Distortion

THD is the ratio of the sum of the rms value of the first six
harmonic components to the rms value of the measured output
signal. It is expressed as a percentage or in decibels (dB).

Multitone Power Ratio

The spurious-free dynamic range for an output containing mul­tiple carrier tones of equal amplitude. It is measured as the
difference between the rms amplitude of a carrier tone to the
peak spurious signal in the region of a removed tone.

DVDD

DCOM

R

SET

2kV

RETIMED

CLOCK

OUTPUT*

50V

LECROY 9210

PULSE GENERATOR

0.1mF

+5V

+5V

0.1mF

+1.20V REF

REFIO
FS ADJ

DVDD
DCOM

CLOCK

SLEEP

REFLO

SEGMENTED SWITCHES

FOR DB13–DB5

CLOCK

OUTPUT

50pF

COMP1

LATCHES

TEKTRONIX

AWG-2021

AVDD ACOM

PMOS

CURRENT SOURCE

ARRAY

SWITCHES

DIGITAL

DATA

AD9764

LSB

Figure 2. Basic AC Characterization Test Setup

COMP2

I

OUTA

I

OUTB

50V

0.1mF
MINI-CIRCUITS

100V

50V

20pF

20pF

* AWG2021 CLOCK RETIMED
SUCH THAT DIGITAL DATA
TRANSITIONS ON FALLING EDGE
OF 50% DUTY CYCLE CLOCK.

T1-1T

TO HP3589A
SPECTRUM/
NETWORK
ANALYZER
50V INPUT

–6–

REV. B

Typical AC Characterization Curves

FREQUENCY – MHz

SFDR – dBc

90

40

02 1246810

85

60
55
50
45

80
75

65

70

0dBFS

–6dBFS

–12dBFS

FREQUENCY – MHz

90

85

50

0.0 2.0 10.0

4.0 6.0 8.0

70

65

60

55

80

75

5mA @ 3V

5mA @ 5V

10mA @ 3V

10mA @ 5V

20mA @ 3V

20mA @ 5V

SFDR – dBc

A

OUT

– dBFS

SFDR – dBc

90

80

50

–30 –25 0

–20 –15 –10 –5

70

60

0.675/0.725MHz @ 5 MSPS

3.38/3.63MHz @ 25 MSPS

13.5/14.5MHz @ 100 MSPS

6.75/7.25 @ 50 MSPS

(AVDD = +5 V, DVDD = +3 V, I

= 20 mA, 50 ⍀ Doubly Terminated Load, Differential Output, TA = +25ⴗC, SFDR up to Nyquist, unless otherwise noted)

OUTFS

AD9764

90
85

5 MSPS

80

25 MSPS

75
70

65
60

SFDR – dBc

55
50

45
40

Figure 3. SFDR vs. f

90
85

80
75

70
65
60

SFDR – dBc

55
50

45
40

Figure 6. SFDR vs. f

50 MSPS

100 MSPS

0.1 1 10010

05 25

FREQUENCY – MHz

–6dBFS

–12dBFS

0dBFS

10 15 20

FREQUENCY – MHz

@ 0 dBFS

OUT

@ 50 MSPS

OUT

90
85

0dBFS

80
75

70
65

60

SFDR – dBc

55
50

45
40

–12dBFS

0 0.5 2.5

Figure 4. SFDR vs. f

90
85

80
75
70
65

60

SFDR – dBc

55
50

45
40

010 5020 30 40

–6dBFS

0dBFS

Figure 7. SFDR vs. f

–6dBFS

1.0 1.5 2.0

FREQUENCY – MHz

OUT

–12dBFS

FREQUENCY – MHz

OUT

@ 5 MSPS

@100 MSPS

Figure 5. SFDR vs. f

Figure 8. SFDR vs. f
I

@ 25 MSPS and 0 dBFS

OUTFS

@ 25 MSPS

OUT

and

OUT

90

2.27MHz @ 25 MSPS

80

70

SFDR – dBc

60

4.55MHz @ 50 MSPS

50

–30 –25 0–20 –15 –10 –5

Figure 9. Single-Tone SFDR vs. A
@ f

OUT

REV. B

= f

CLOCK

455kHz @ 5 MSPS

9.09MHz @ 100 MSPS

A

– dBFS

OUT

/11

OUT

90

80

70

SFDR – dBc

60

50

1MHz @ 5 MSPS

5MHz @ 25 MSPS

20MHz @ 100 MSPS

10MHz @ 50 MSPS

–30 –25 0–20 –15 –10 –5

A

– dBFS

OUT

Figure 10. Single-Tone SFDR vs.
A

OUT

@ f

OUT

= f

CLOCK

/5

–7–

Figure 11. Dual-Tone SFDR vs. A
@ f

OUT

= f

CLOCK

/7

OUT