a
(
)
14-Bit, 125 MSPS
TxDAC
®
D/A Converter
AD9764*
FEATURES
Member of Pin-Compatible TxDAC Product Family
125 MSPS Update Rate
14-Bit Resolution
Excellent SFDR and IMD
Differential Current Outputs: 2 mA to 20 mA
Power Dissipation: 190 mW @ 5 V to 45 mW @ 3 V
Power-Down Mode: 25 mW @ 5 V
On-Chip 1.20 V Reference
Single +5 V or +3 V Supply Operation
Packages: 28-Lead SOIC and TSSOP
Edge-Triggered Latches
APPLICATIONS
Communication Transmit Channel:
Basestations
ADSL/HFC Modems
Instrumentation
PRODUCT DESCRIPTION
The AD9764 is the 14-bit resolution member of the TxDAC
series of high performance, low power CMOS digital-to-analog
converters (DACs). The TxDAC
family, which consists of pin
compatible 8-, 10-, 12-, and 14-bit DACs, is specifically optimized for the transmit signal path of communication systems.
All of the devices share the same interface options, small outline
package and pinout, providing an upward or downward component selection path based on performance, resolution and cost.
The AD9764 offers exceptional ac and dc performance while
supporting update rates up to 125 MSPS.
The AD9764’s flexible single-supply operating range of 2.7 V to
5.5 V and low power dissipation are well suited for portable and
low power applications. Its power dissipation can be further
reduced to a mere 45 mW with a slight degradation in performance
by lowering the full-scale current output. Also, a power-down
mode reduces the standby power dissipation to approximately
25 mW.
The AD9764 is manufactured on an advanced CMOS process.
A segmented current source architecture is combined with a
proprietary switching technique to reduce spurious components
and enhance dynamic performance. Edge-triggered input
latches and a 1.2 V temperature compensated bandgap reference have been integrated to provide a complete monolithic
DAC solution. Flexible supply options support +3 V and +5 V
CMOS logic families.
The AD9764 is a current-output DAC with a nominal full-scale
output current of 20 mA and > 100 kΩ output impedance.
TxDAC is a registered trademark of Analog Devices, Inc.
*Patent pending.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
+5V
0.1mF
50pF
LATCHES
COMP1
CURRENT
SOURCE
ARRAY
SWITCHES
AVDD ACOM
AD9764
LSB
DB13–DB0
COMP2
I
OUTA
I
OUTB
0.1mF
R
SET
CLOCK
0.1mF
+5V
REFLO
+1.20V REF
REFIO
FS ADJ
DVDD
DCOM
CLOCK
SLEEP
DIGITAL DATA INPUTS
SEGMENTED
SWITCHES
Differential current outputs are provided to support singleended or differential applications. Matching between the two
current outputs ensures enhanced dynamic performance in a
differential output configuration. The current outputs may be
tied directly to an output resistor to provide two complementary, single-ended voltage outputs or fed directly into a transformer. The output voltage compliance range is 1.25 V.
The on-chip reference and control amplifier are configured for
maximum accuracy and flexibility. The AD9764 can be driven
by the on-chip reference or by a variety of external reference
voltages. The internal control amplifier, which provides a wide
(>10:1) adjustment span, allows the AD9764 full-scale current
to be adjusted over a 2 mA to 20 mA range while maintaining
excellent dynamic performance. Thus, the AD9764 may operate
at reduced power levels or be adjusted over a 20 dB range to
provide additional gain ranging capabilities.
The AD9764 is available in 28-lead SOIC and TSSOP packages.
It is specified for operation over the industrial temperature range.
PRODUCT HIGHLIGHTS
1. The AD9764 is a member of the TxDAC product family that
provides an upward or downward component selection path
based on resolution (8 to 14 bits), performance and cost.
2. Manufactured on a CMOS process, the AD9764 uses a proprietary switching technique that enhances dynamic performance beyond that previously attainable by higher power/cost
bipolar or BiCMOS devices.
3. On-chip, edge-triggered input CMOS latches readily interface
to +3 V and +5 V CMOS logic families. The AD9764 can
support update rates up to 125 MSPS.
4. A flexible single-supply operating range of 2.7 V to 5.5 V, and
a wide full-scale current adjustment span of 2 mA to 20 mA,
allows the AD9764 to operate at reduced power levels.
5. The current output(s) of the AD9764 can be easily configured for various single-ended or differential circuit topologies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1999
AD9764–SPECIFICATIONS
DC SPECIFICATIONS
(T
to T
MIN
, AVDD = +5 V, DVDD = +5 V, I
MAX
= 20 mA, unless otherwise noted)
OUTFS
Parameter Min Typ Max Units
RESOLUTION 14 Bits
DC ACCURACY
1
Integral Linearity Error (INL)
= +25°C –4.5 ±2.5 +4.5 LSB
T
A
to T
T
MIN
MAX
–6.5 +6.5 LSB
Differential Nonlinearity (DNL)
= +25°C –2.5 ±1.5 +2.5 LSB
T
A
T
MIN
to T
MAX
–4.5 +4.5 LSB
ANALOG OUTPUT
Offset Error –0.025 +0.025 % of FSR
Gain Error
Gain Error
Full-Scale Output Current
(Without Internal Reference) –2 ±1 +2 % of FSR
(With Internal Reference) –7 ±1 +7 % of FSR
2
2.0 20.0 mA
Output Compliance Range –1.0 1.25 V
Output Resistance 100 kΩ
Output Capacitance 5 pF
REFERENCE OUTPUT
Reference Voltage 1.08 1.20 1.32 V
Reference Output Current
3
100 nA
REFERENCE INPUT
Input Compliance Range 0.1 1.25 V
Reference Input Resistance 1 MΩ
Small Signal Bandwidth (w/o C
COMP1
4
)
1.4 MHz
TEMPERATURE COEFFICIENTS
Offset Drift 0 ppm of FSR/°C
Gain Drift
Gain Drift
(Without Internal Reference) ±50 ppm of FSR/°C
(With Internal Reference) ±100 ppm of FSR/°C
Reference Voltage Drift ±50 ppm/°C
POWER SUPPLY
Supply Voltages
AVDD
5
2.7 5.0 5.5 V
DVDD 2.7 5.0 5.5 V
Analog Supply Current (I
Digital Supply Current (I
Supply Current Sleep Mode (I
Power Dissipation
Power Dissipation
Power Dissipation
6
(5 V, I
7
(5 V, I
7
(3 V, I
Power Supply Rejection Ratio
)2530mA
AVDD
6
)
DVDD
OUTFS
OUTFS
OUTFS
) 5.0 8.5 mA
AVDD
= 20 mA) 133 170 mW
= 20 mA) 190 mW
= 2 mA) 45 mW
8
—AVDD –0.4 +0.4 % of FSR/V
1.5 4 mA
Power Supply Rejection Ratio8—DVDD –0.025 +0.025 % of FSR/V
OPERATING RANGE –40 +85 °C
NOTES
1
Measured at I
2
Nominal full-scale current, I
3
Use an external buffer amplifier to drive any external load.
4
Reference bandwidth is a function of external cap at COMP1 pin and signal level.
5
For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance.
6
Measured at f
7
Measured as unbuffered voltage output with I
8
±5% Power supply variation.
Specifications subject to change without notice.
, driving a virtual ground.
OUTA
= 25 MSPS and f
CLOCK
, is 32 × the I
OUTFS
= 1.0 MHz.
OUT
current.
REF
= 20 mA and 50 Ω R
OUTFS
LOAD
at I
OUTA
and I
OUTB
, f
= 100 MSPS and f
CLOCK
= 40 MHz.
OUT
REV. B–2–
AD9764
(T
to T
, AVDD = +5 V, DVDD = +5 V, I
MAX
DYNAMIC SPECIFICATIONS
MIN
50 ⍀ Doubly Terminated, unless otherwise noted)
Parameter Min Typ Max Units
DYNAMIC PERFORMANCE
Maximum Output Update Rate (f
Output Settling Time (t
Output Propagation Delay (t
) (to 0.1%)
ST
)1ns
PD
Glitch Impulse 5 pV-s
Output Rise Time (10% to 90%)
Output Fall Time (10% to 90%)
Output Noise (I
Output Noise (I
= 20 mA) 50 pA/√Hz
OUTFS
= 2 mA) 30 pA/√Hz
OUTFS
) 125 MSPS
CLOCK
1
1
1
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
f
= 25 MSPS; f
CLOCK
= 1.00 MHz
OUT
0 dBFS Output
= +25°C 75 82 dBc
T
A
to T
T
MIN
MAX
73 dBc
–6 dBFS Output 85 dBc
–12 dBFS Output 77 dBc
–18 dBFS Output 70 dBc
= 50 MSPS; f
f
CLOCK
= 50 MSPS; f
f
CLOCK
= 50 MSPS; f
f
CLOCK
= 50 MSPS; f
f
CLOCK
= 1.00 MHz 80 dBc
OUT
= 2.51 MHz 77 dBc
OUT
= 5.02 MHz 70 dBc
OUT
= 20.2 MHz 58 dBc
OUT
Spurious-Free Dynamic Range within a Window
= 25 MSPS; f
f
CLOCK
= +25°C 78 89 dBc
T
A
to T
T
f
CLOCK
f
CLOCK
MIN
MAX
= 50 MSPS; f
= 100 MSPS; f
= 1.00 MHz; 2 MHz Span
OUT
76 dBc
= 5.02 MHz; 2 MHz Span 84 dBc
OUT
= 5.04 MHz; 4 MHz Span 84 dBc
OUT
Total Harmonic Distortion
= 25 MSPS; f
f
CLOCK
= +25°C –78 –74 dBc
T
A
to T
T
f
CLOCK
f
CLOCK
MIN
MAX
= 50 MHz; f
= 100 MHz; f
= 1.00 MHz
OUT
= 2.00 MHz –75 dBc
OUT
= 2.00 MHz –75 dBc
OUT
Multitone Power Ratio (Eight Tones at 110 kHz Spacing)
= 20 MSPS; f
f
CLOCK
= 2.00 MHz to 2.99 MHz
OUT
0 dBFS Output 73 dBc
–6 dBFS Output 76 dBc
–12 dBFS Output 73 dBc
–18 dBFS Output 64 dBc
NOTES
1
Measured single-ended into 50 Ω load.
Specifications subject to change without notice.
= 20 mA, Differential Transformer Coupled Output,
OUTFS
35 ns
2.5 ns
2.5 ns
–72 dBc
REV. B –3–
AD9764
WARNING!
ESD SENSITIVE DEVICE
DIGITAL SPECIFICATIONS
Parameter Min Typ Max Units
DIGITAL INPUTS
Logic “1” Voltage @ DVDD = +5 V 3.5 5 V
Logic “1” Voltage @ DVDD = +3 V 2.1 3 V
Logic “0” Voltage @ DVDD = +5 V 0 1.3 V
Logic “0” Voltage @ DVDD = +3 V 0 0.9 V
Logic “1” Current –10 +10 µA
Logic “0” Current –10 +10 µA
Input Capacitance 5 pF
Input Setup Time (tS) 2.0 ns
Input Hold Time (t
Latch Pulsewidth (t
Specifications subject to change without notice.
) 1.5 ns
H
) 3.5 ns
LPW
DB0–DB13
t
S
CLOCK
t
PD
IOUTA
OR
IOUTB
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS*
With
Parameter Respect to Min Max Units
AVDD ACOM –0.3 +6.5 V
DVDD DCOM –0.3 +6.5 V
ACOM DCOM –0.3 +0.3 V
AVDD DVDD –6.5 +6.5 V
CLOCK, SLEEP DCOM –0.3 DVDD + 0.3 V
Digital Inputs DCOM –0.3 DVDD + 0.3 V
I
OUTA
, I
OUTB
ACOM –1.0 AVDD + 0.3 V
COMP1, COMP2 ACOM –0.3 AVDD + 0.3 V
REFIO, FSADJ ACOM –0.3 AVDD + 0.3 V
REFLO ACOM –0.3 +0.3 V
Junction Temperature +150 °C
Storage Temperature –65 +150 °C
Lead Temperature
(10 sec) +300 °C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
t
H
t
LPW
t
ST
0.1%
0.1%
ORDERING GUIDE
Temperature Package Package
Model Range Description Options*
AD9764AR –40°C to +85°C 28-Lead 300 mil SOIC R-28
AD9764ARU –40°C to +85°C 28-Lead TSSOP RU-28
AD9764-EB Evaluation Board
*R = Small Outline IC, RU = TSSOP.
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead 300 mil SOIC
= 71.4°C/W
θ
JA
= 23°C/W
θ
JC
28-Lead TSSOP
= 97.9°C/W
θ
JA
= 14.0°C/W
θ
JC
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9764 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
REV. B
PIN CONFIGURATION
AD9764
(MSB) DB13
1
2
DB12
DB11
3
DB10
4
DB9
5
6
DB8
DB7
7
8
DB6
9
DB5
10
DB4
11
DB3
DB2
12
DB1
13
DB0
14
NC = NO CONNECT
AD9764
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CLOCK
DVDD
DCOM
NC
AVDD
COMP2
I
OUTA
I
OUTB
ACOM
COMP1
FS ADJ
REFIO
REFLO
SLEEP
PIN FUNCTION DESCRIPTIONS
Pin No. Name Description
1 DB13 Most Significant Data Bit (MSB).
2–13 DB12–DB1 Data Bits 1–12.
14 DB0 Least Significant Data Bit (LSB).
15 SLEEP Power-Down Control Input. Active High. Contains active pull-down circuit; it may be left unterminated if
not used.
16 REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference.
17 REFIO Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to
AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM).
Requires 0.1 µF capacitor to ACOM when internal reference activated.
18 FS ADJ Full-Scale Current Output Adjust.
19 COMP1 Bandwidth/Noise Reduction Node. Add 0.1 µF to AVDD for optimum performance.
20 ACOM Analog Common.
21 I
22 I
OUTB
OUTA
Complementary DAC Current Output. Full-scale current when all data bits are 0s.
DAC Current Output. Full-scale current when all data bits are 1s.
23 COMP2 Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 µF capacitor.
24 AVDD Analog Supply Voltage (+2.7 V to +5.5 V).
25 NC No Internal Connection.
26 DCOM Digital Common.
27 DVDD Digital Supply Voltage (+2.7 V to +5.5 V).
28 CLOCK Clock Input. Data latched on positive edge of clock.
REV. B
–5–
AD9764
DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input
code.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For I
inputs are all 0s. For I
, 0 mA output is expected when the
OUTA
, 0 mA output is expected when all
OUTB
inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (+25°C) value to the value at either T
MIN
or T
MAX
. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree C. For reference drift, the drift is
reported in ppm per degree C.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied over a specified range.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Total Harmonic Distortion
THD is the ratio of the sum of the rms value of the first six
harmonic components to the rms value of the measured output
signal. It is expressed as a percentage or in decibels (dB).
Multitone Power Ratio
The spurious-free dynamic range for an output containing multiple carrier tones of equal amplitude. It is measured as the
difference between the rms amplitude of a carrier tone to the
peak spurious signal in the region of a removed tone.
DVDD
DCOM
R
SET
2kV
RETIMED
CLOCK
OUTPUT*
50V
LECROY 9210
PULSE GENERATOR
0.1mF
+5V
+5V
0.1mF
+1.20V REF
REFIO
FS ADJ
DVDD
DCOM
CLOCK
SLEEP
REFLO
SEGMENTED SWITCHES
FOR DB13–DB5
CLOCK
OUTPUT
50pF
COMP1
LATCHES
TEKTRONIX
AWG-2021
AVDD ACOM
PMOS
CURRENT SOURCE
ARRAY
SWITCHES
DIGITAL
DATA
AD9764
LSB
Figure 2. Basic AC Characterization Test Setup
COMP2
I
OUTA
I
OUTB
50V
0.1mF
MINI-CIRCUITS
100V
50V
20pF
20pF
* AWG2021 CLOCK RETIMED
SUCH THAT DIGITAL DATA
TRANSITIONS ON FALLING EDGE
OF 50% DUTY CYCLE CLOCK.
T1-1T
TO HP3589A
SPECTRUM/
NETWORK
ANALYZER
50V INPUT
–6–
REV. B
Typical AC Characterization Curves
FREQUENCY – MHz
SFDR – dBc
90
40
02 1246810
85
60
55
50
45
80
75
65
70
0dBFS
–6dBFS
–12dBFS
FREQUENCY – MHz
90
85
50
0.0 2.0 10.0
4.0 6.0 8.0
70
65
60
55
80
75
5mA @ 3V
5mA @ 5V
10mA @ 3V
10mA @ 5V
20mA @ 3V
20mA @ 5V
SFDR – dBc
A
OUT
– dBFS
SFDR – dBc
90
80
50
–30 –25 0
–20 –15 –10 –5
70
60
0.675/0.725MHz @ 5 MSPS
3.38/3.63MHz @ 25 MSPS
13.5/14.5MHz @ 100 MSPS
6.75/7.25 @ 50 MSPS
(AVDD = +5 V, DVDD = +3 V, I
= 20 mA, 50 ⍀ Doubly Terminated Load, Differential Output, TA = +25ⴗC, SFDR up to Nyquist, unless otherwise noted)
OUTFS
AD9764
90
85
5 MSPS
80
25 MSPS
75
70
65
60
SFDR – dBc
55
50
45
40
Figure 3. SFDR vs. f
90
85
80
75
70
65
60
SFDR – dBc
55
50
45
40
Figure 6. SFDR vs. f
50 MSPS
100 MSPS
0.1 1 10010
05 25
FREQUENCY – MHz
–6dBFS
–12dBFS
0dBFS
10 15 20
FREQUENCY – MHz
@ 0 dBFS
OUT
@ 50 MSPS
OUT
90
85
0dBFS
80
75
70
65
60
SFDR – dBc
55
50
45
40
–12dBFS
0 0.5 2.5
Figure 4. SFDR vs. f
90
85
80
75
70
65
60
SFDR – dBc
55
50
45
40
010 5020 30 40
–6dBFS
0dBFS
Figure 7. SFDR vs. f
–6dBFS
1.0 1.5 2.0
FREQUENCY – MHz
OUT
–12dBFS
FREQUENCY – MHz
OUT
@ 5 MSPS
@100 MSPS
Figure 5. SFDR vs. f
Figure 8. SFDR vs. f
I
@ 25 MSPS and 0 dBFS
OUTFS
@ 25 MSPS
OUT
and
OUT
90
2.27MHz @ 25 MSPS
80
70
SFDR – dBc
60
4.55MHz @ 50 MSPS
50
–30 –25 0–20 –15 –10 –5
Figure 9. Single-Tone SFDR vs. A
@ f
OUT
REV. B
= f
CLOCK
455kHz @ 5 MSPS
9.09MHz @ 100 MSPS
A
– dBFS
OUT
/11
OUT
90
80
70
SFDR – dBc
60
50
1MHz @ 5 MSPS
5MHz @ 25 MSPS
20MHz @ 100 MSPS
10MHz @ 50 MSPS
–30 –25 0–20 –15 –10 –5
A
– dBFS
OUT
Figure 10. Single-Tone SFDR vs.
A
OUT
@ f
OUT
= f
CLOCK
/5
–7–
Figure 11. Dual-Tone SFDR vs. A
@ f
OUT
= f
CLOCK
/7
OUT
AD9764
OUTPUT FREQUENCY – MHz
SFDR – dBc
80
70
50
1 10 100
60
I
DIFF
@ 0dBFS
I
DIFF
@ –6dBFS
IA @ 0dBFS
IA @ –6dBFS
TEMPERATURE – 8C
SFDR – dBc
80
75
50
–40 –20 80
60
70
65
60
55
40200
2.5MHz
10MHz
40MHz
–70
–75
–80
dBc
–85
–90
–95
000.0E+0 40.0E+6 80.0E+6 120.0E+6
2ND HARMONIC
3RD HARMONIC
4TH HARMONIC
Figure 12. THD vs. f
f
= 2 MHz
OUT
2.0
1.5
1.0
0.5
0.0
–0.5
ERROR – LSB
–1.0
–1.5
–2.0
0 160004000 8000 12000
CODE
Figure 15. Typical INL
CLOCK
@
85
I
= 20mA,
80
75
SNR – dB
70
65
60
Figure 13. SNR vs. f
OUTFS
DVDD = +3V
I
= 20mA,
OUTFS
DVDD = +5V
I
OUTFS
DVDD = +3V
I
= 5mA,
OUTFS
DVDD = +3V
0 10 100
I
= 5mA,
OUTFS
DVDD = +5V
20 30 40 50 60 70 80 90
f
– MSPS
CLOCK
CLOCK
2.0 MHz
2.0
1.5
1.0
0.5
ERROR – LSB
0.0
–0.5
–1.0
0 16000
4000 8000 12000
CODE
Figure 16. Typical DNL
= 10mA,
I
= 10mA,
OUTFS
DVDD = +5V
@ f
OUT
=
Figure 14. Differential vs. Single-
Ended SFDR vs. f
@ 50 MSPS
OUT
Figure 17. SFDR vs. Temperature
@ 100 MSPS, 0 dBFS
0
–10
–20
–30
–40
–50
10dB – Div
–60
–70
–80
–90
000.0E+0 7.5E+6 15.0E+6 22.5E+6
Figure 18. Single-Tone SFDR
f
= 50MSPS
CLK
f
= 1.25MHz
OUT
SFDR = 78dBc
AMPLITUDE = 0dBFS
0
–10
–20
–30
–40
–50
10dB – Div
–60
–70
–80
–90
0E+0 25E+65E+6 10E+6 15E+6 20E+6
f
= 50MSPS
CLK
f
= 6.75MHz
OUT1
f
= 7.25MHz
OUT2
SFDR = 69dBc
AMPLITUDE = 0dBFS
Figure 19. Dual-Tone SFDR
–8–
0
–10
–20
–30
–40
–50
–60
10dB – Div
–70
–80
–90
–100
000.0E+0 7.5E+6 15.0E+6 22.5E+6
f
= 50MSPS
CLK
f
= 6.25MHz
OUT1
f
= 6.75MHz
OUT2
f
= 7.25MHz
OUT3
f
= 7.75MHz
OUT4
SFDR = 66dBc
AMPLITUDE = 0dBFS
Figure 20. Four-Tone SFDR
REV. B
)
0.1mF
AD9764
+5V
0.1mF
V
REFIO
R
2kV
CLOCK
SET
I
REF
+5V
+1.20V REF
REFIO
FS ADJ
DVDD
DCOM
CLOCK
SLEEP
REFLO
SEGMENTED SWITCHES
FOR DB13–DB5
DIGITAL DATA INPUTS (DB13–DB0
COMP1
50pF
CURRENT SOURCE
LATCHES
Figure 21. Functional Block Diagram
FUNCTIONAL DESCRIPTION
Figure 21 shows a simplified block diagram of the AD9764. The
AD9764 consists of a large PMOS current source array that is
capable of providing up to 20 mA of total current. The array
is divided into 31 equal currents that make up the five most
significant bits (MSBs). The next four bits or middle bits consist
of 15 equal current sources whose value is 1/16th of an MSB
current source. The remaining LSBs are binary weighted fractions of the middle bits current sources. Implementing the
middle and lower bits with current sources, instead of an R-2R
ladder, enhances its dynamic performance for multitone or low
amplitude signals and helps maintain the DAC’s high output
impedance (i.e., >100 kΩ).
All of these current sources are switched to one or the other of
the two output nodes (i.e., I
OUTA
or I
) via PMOS differen-
OUTB
tial current switches. The switches are based on a new architecture that drastically improves distortion performance. This new
switch architecture reduces various timing errors and provides
matching complementary drive signals to the inputs of the differential current switches.
The analog and digital sections of the AD9764 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 2.7 volt to 5.5 volt range. The digital
section, which is capable of operating up to a 125 MSPS clock
rate, consists of edge-triggered latches and segment decoding
logic circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.20 V bandgap
voltage reference and a reference control amplifier.
The full-scale output current is regulated by the reference control amplifier and can be set from 2 mA to 20 mA via an external resistor, R
. The external resistor, in combination with
SET
both the reference control amplifier and voltage reference
, sets the reference current I
V
REFIO
, which is mirrored over to
REF
the segmented current sources with the proper scaling factor.
The full-scale current, I
, is 32 times the value of I
OUTFS
REF
.
DAC TRANSFER FUNCTION
The AD9764 provides complementary current outputs, I
and I
I
OUTFS
I
OUTB
current output appearing at I
both the input code and I
. I
OUTB
will provide a near full-scale current output,
OUTA
, when all bits are high (i.e., DAC CODE = 16383) while
, the complementary output, provides no current. The
I
= (DAC CODE/16384) × I
OUTA
and I
OUTA
and can be expressed as:
OUTFS
is a function of
OUTB
OUTFS
OUTA
(1)
AVDD ACOM
AD9764
PMOS
ARRAY
SWITCHES
LSB
= (16383 – DAC CODE)/16384 × I
I
OUTB
COMP2
I
OUTA
I
OUTB
0.1mF
I
OUTB
I
OUTA
V
DIFF
V
R
50V
= V
OUTB
LOAD
OUTA
– V
V
OUTA
R
LOAD
50V
OUTB
OUTFS
(2)
where DAC CODE = 0 to 16383 (i.e., Decimal Representation).
As mentioned previously, I
current I
V
REFIO
I
where I
, which is nominally set by a reference voltage
REF
and external resistor R
= 32 × I
OUTFS
REF
= V
REF
REFIO/RSET
is a function of the reference
OUTFS
. It can be expressed as:
SET
(3)
(4)
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, I
and I
loads, R
that R
I
OUTA
should be directly connected to matching resistive
OUTB
, that are tied to analog common, ACOM. Note
LOAD
may represent the equivalent load resistance seen by
LOAD
or I
as would be the case in a doubly terminated
OUTB
OUTA
50 Ω or 75 Ω cable. The single-ended voltage output appearing
OUTA
= I
= I
and I
OUTA
OUTB
at the I
V
OUTA
V
OUTB
Note that the full-scale value of V
nodes is simply:
OUTB
× R
LOAD
× R
LOAD
OUTA
and V
should not
OUTB
(5)
(6)
exceed the specified output compliance range to maintain specified distortion and linearity performance.
The differential voltage, V
is:
I
OUTB
V
DIFF
= (I
OUTA
– I
OUTB
Substituting the values of I
, appearing across I
DIFF
) × R
LOAD
, I
OUTB
and I
OUTA
REF
; V
OUTA
DIFF
and
(7)
can be
expressed as:
V
= {(2 DAC CODE – 16383)/16384} ×
DIFF
V
DIFF
= {(32 R
LOAD/RSET
) × V
REFIO
(8)
These last two equations highlight some of the advantages of
operating the AD9764 differentially. First, the differential operation will help cancel common-mode error sources associated
with I
OUTA
and I
such as noise, distortion and dc offsets.
OUTB
Second, the differential code-dependent current and subsequent
voltage, V
output (i.e., V
, is twice the value of the single-ended voltage
DIFF
OUTA
or V
), thus providing twice the signal
OUTB
power to the load.
Note that the gain drift temperature performance for a singleended (V
OUTA
and V
) or differential output (V
OUTB
DIFF
) of the
AD9764 can be enhanced by selecting temperature tracking
resistors for R
LOAD
and R
due to their ratiometric relation-
SET
ship as shown in Equation 8.
REV. B
–9–
AD9764
COMP1 CAPACITOR – nF
1000
10
0.1
0.1 10001
BANDWIDTH – kHz
10 100
REFERENCE OPERATION
The AD9764 contains an internal 1.20 V bandgap reference
that can be easily disabled and overridden by an external
reference. REFIO serves as either an input or output, depending
on whether the internal or external reference is selected. If
REFLO is tied to ACOM, as shown in Figure 22, the internal
reference is activated, and REFIO provides a 1.20 V output. In
this case, the internal reference must be compensated externally
with a ceramic chip capacitor of 0.1 µF or greater from REFIO
to REFLO. Also, REFIO should be buffered with an external
amplifier having an input bias current less than 100 nA if any
additional loading is required.
+5V
50pF
0.1mF
COMP1
CURRENT
SOURCE
AVDD
ARRAY
ADDITIONAL
LOAD
OPTIONAL
EXTERNAL
REF BUFFER
0.1mF
2kV
REFLO
+1.2V REF
REFIO
FS ADJ
AD9764
Figure 22. Internal Reference Configuration
The internal reference can be disabled by connecting REFLO to
AVDD. In this case, an external reference may then be applied
to REFIO as shown in Figure 23. The external reference may
provide either a fixed reference voltage to enhance accuracy and
drift performance or a varying reference voltage for gain control.
Note that the 0.1 µF compensation capacitor is not required
since the internal reference is disabled, and the high input im-
pedance (i.e., 1 MΩ) of REFIO minimizes any loading of the
external reference.
AVDD
provides several application benefits. The first benefit relates
directly to the power dissipation of the AD9764, which is proportional to I
(refer to the Power Dissipation section). The
OUTFS
second benefit relates to the 20 dB adjustment, which is useful
for system gain control purposes.
The small signal bandwidth of the reference control amplifier is
approximately 1.4 MHz and can be reduced by connecting an
external capacitor between COMP1 and AVDD. The output of
the control amplifier, COMP1, is internally compensated via a
50 pF capacitor that limits the control amplifier small-signal
bandwidth and reduces its output impedance. Any additional
external capacitance further limits the bandwidth and acts as a
filter to reduce the noise contribution from the reference amplifier. Figure 24 shows the relationship between the external
capacitor and the small signal –3 dB bandwidth of the reference amplifier. Since the –3 dB bandwidth corresponds to the
dominant pole, and hence the time constant, the settling time of
the control amplifier to a stepped reference input response can
be approximated.
EXTERNAL
REFERENCE CONTROL AMPLIFIER
The AD9764 also contains an internal control amplifier that is
used to regulate the DAC’s full-scale output current, I
The control amplifier is configured as a V-I converter, as shown
in Figure 23, such that its current output, I
the ratio of the V
in Equation 4. I
sources with the proper scaling factor to set I
Equation 3.
The control amplifier allows a wide (10:1) adjustment span of
I
OUTFS
62.5 µA and 625 µA. The wide adjustment span of I
0.1mF
AVDD
REF
REFLO
+1.2V REF
V
REFIO
R
I
SET
REF
V
REFIO/RSET
REFIO
FS ADJ
=
AD9764
COMP1
50pF
REFERENCE
CONTROL
AMPLIFIER
AVDD
CURRENT
SOURCE
ARRAY
Figure 23. External Reference Configuration
.
OUTFS
, is determined by
and an external resistor, R
REFIO
is copied over to the segmented current
REF
REF
OUTFS
, as stated
SET
as stated in
over a 2 mA to 20 mA range by setting IREF between
OUTFS
Figure 24. External COMP1 Capacitor vs. –3 dB Bandwidth
The optimum distortion performance for any reconstructed
waveform is obtained with a 0.1 µF external capacitor installed.
Thus, if I
is fixed for an application, a 0.1 µF ceramic chip
REF
capacitor is recommended. Also, since the control amplifier is
optimized for low power operation, multiplying applications
requiring large signal swings should consider using an external
control amplifier to enhance the application’s overall large signal
multiplying bandwidth and/or distortion performance.
There are two methods in which I
. The first method is suitable for a single-supply system in
R
SET
can be varied for a fixed
REF
which the internal reference is disabled, and the common-mode
voltage of REFIO is varied over its compliance range of 1.25 V
to 0.10 V. REFIO can be driven by a single-supply amplifier or
DAC, thus allowing I
to be varied for a fixed R
REF
. Since the
SET
input impedance of REFIO is approximately 1 MΩ, a simple,
low cost R-2R ladder DAC configured in the voltage mode
topology may be used to control the gain. This circuit is shown
in Figure 25 using the AD7524 and an external 1.2 V reference,
the AD1580.
–10–
REV. B
AVDD
AD9764
AVDD
1.2V
AD1580
R
OUT1
OUT2
AGND
FB
AD7524
V
DD
V
DB7–DB0
REF
0.1V TO 1.2V
R
SET
I
REF
V
REF/RSET
Figure 25. Single-Supply Gain Control Circuit
The second method may be used in a dual-supply system in
which the common-mode voltage of REFIO is fixed, and I
varied by an external voltage, V
GC
, applied to R
via an ampli-
SET
REF
is
fier. An example of this method is shown in Figure 26 in which
the internal reference is used to set the common-mode voltage
of the control amplifier to 1.20 V. The external voltage, V
GC
, is
referenced to ACOM and should not exceed 1.2 V. The value of
is such that I
R
SET
REFMAX
and I
do not exceed 62.5 µA
REFMIN
and 625 µA, respectively. The associated equations in Figure 26
can be used to determine the value of R
BANDLIMITING
+1.2V REF
REFIO
I
REF
I
= (1.2–VGC)/R
REF
WITH V
FS ADJ
AD9764
< V
GC
SET
AND 62.5mA # I
REFIO
1mF
V
R
SET
GC
SET
OPTIONAL
CAPACITOR
50pF
.
COMP1 AVDDREFLO
CURRENT
# 625A
REF
AVDD
SOURCE
ARRAY
Figure 26. Dual-Supply Gain Control Circuit
In some applications, the user may elect to use an external
control amplifier to enhance the multiplying bandwidth,
distortion performance and/or settling time. External amplifiers
capable of driving a 50 pF load such as the AD817 are suitable
for this purpose. It is configured in such a way that it is in
parallel with the weaker internal reference amplifier as shown in
Figure 27. In this case, the external amplifier simply overdrives
the weaker reference control amplifier. Also, since the internal
control amplifier has a limited current output, it will sustain no
damage if overdriven.
EXTERNAL
CONTROL AMPLIFIER
V
REF
INPUT
R
SET
+1.2V REF
REFIO
FS ADJ
AD9764
REFLO
50pF
COMP1
CURRENT
SOURCE
AVDD
AVDD
ARRAY
Figure 27. Configuring an External Reference Control
Amplifier
OPTIONAL
BANDLIMITING
CAPACITOR
REFLO
+1.2V REF
REFIO
FS ADJ
=
AD9764
50pF
COMP1
CURRENT
SOURCE
AVDD
ARRAY
ANALOG OUTPUTS
The AD9764 produces two complementary current outputs,
and I
I
OUTA
or differential operation. I
complementary single-ended voltage outputs, V
, via a load resistor, R
V
OUTB
, which may be configured for single-end
OUTB
OUTA
and I
LOAD
can be converted into
OUTB
, as described in the DAC
OUTA
and
Transfer Function section by Equations 5 through 8. The
differential voltage, V
, existing between V
DIFF
OUTA
and V
OUTB
can also be converted to a single-ended voltage via a transformer
or differential amplifier configuration.
Figure 28 shows the equivalent analog output circuit of the
AD9764 consisting of a parallel combination of PMOS differential current switches associated with each segmented current
source. The output impedance of I
OUTA
and I
is determined
OUTB
by the equivalent parallel combination of the PMOS switches
and is typically 100 kΩ in parallel with 5 pF. Due to the na-
ture of a PMOS device, the output impedance is also slightly
dependent on the output voltage (i.e., V
OUTA
and V
OUTB
) and, to
a lesser extent, the analog supply voltage, AVDD, and full-scale
current, I
. Although the output impedance’s signal depen-
OUTFS
dency can be a source of dc nonlinearity and ac linearity (i.e.,
distortion), its effects can be limited if certain precautions are
noted.
AD9764
AVDD
I
OUTA
R
LOAD
I
OUTB
R
LOAD
Figure 28. Equivalent Analog Output Circuit
I
OUTA
and I
also have a negative and positive voltage compli-
OUTB
ance range. The negative output compliance range of –1.0 V is
set by the breakdown limits of the CMOS process. Operation
beyond this maximum limit may result in a breakdown of the
output stage and affect the reliability of the AD9764. The positive output compliance range is slightly dependent on the fullscale output current, I
. It degrades slightly from its nominal
OUTFS
REV. B
–11–
AD9764
DVDD
DIGITAL
INPUT
1.25 V for an I
= 20 mA to 1.00 V for an I
OUTFS
OUTFS
= 2 mA.
Operation beyond the positive compliance range will induce
clipping of the output signal which severely degrades the
AD9764’s linearity and distortion performance.
For applications requiring the optimum dc linearity, I
or I
amp configuration. Maintaining I
should be maintained at a virtual ground via an I-V op
OUTB
OUTA
and/or I
OUTB
and/
OUTA
at a virtual
ground keeps the output impedance of the AD9764 fixed, significantly reducing its effect on linearity. However, it does not
necessarily lead to the optimum distortion performance due to
limitations of the I-V op amp. Note that the INL/DNL specifications for the AD9764 are measured in this manner using
. In addition, these dc linearity specifications remain
I
OUTA
virtually unaffected over the specified power supply range of
2.7 V to 5.5 V.
Operating the AD9764 with reduced voltage output swings at
I
OUTA
and I
in a differential or single-ended output configu-
OUTB
ration reduces the signal dependency of its output impedance
thus enhancing distortion performance. Although the voltage
compliance range of I
OUTA
and I
extends from –1.0 V to
OUTB
+1.25 V, optimum distortion performance is achieved when the
maximum full-scale signal at I
OUTA
and I
does not exceed
OUTB
approximately 0.5 V. A properly selected transformer with a
grounded center-tap will allow the AD9764 to provide the required power and voltage levels to different loads while maintaining reduced voltage swings at I
OUTA
and I
. DC-coupled
OUTB
applications requiring a differential or single-ended output configuration should size R
accordingly. Refer to Applying the
LOAD
AD9764 section for examples of various output configurations.
The most significant improvement in the AD9764’s distortion
and noise performance is realized using a differential output
configuration. The common-mode error sources of both I
and I
can be substantially reduced by the common-mode
OUTB
OUTA
rejection of a transformer or differential amplifier. These
common-mode error sources include even-order distortion
products and noise. The enhancement in distortion performance
becomes more significant as the reconstructed waveform’s
frequency content increases and/or its amplitude decreases.
This is evident in Figure 14, which compares the differential
vs. single-ended performance of the AD9764 at 50 MSPS for
0.0 and –6.0 dBFS single tone waveforms over frequency.
The distortion and noise performance of the AD9764 is also
slightly dependent on the analog and digital supply as well as the
full-scale current setting, I
. Operating the analog supply at
OUTFS
5.0 V ensures maximum headroom for its internal PMOS current
sources and differential switches leading to improved distortion
performance as shown in Figure 8. Although I
between 2 mA and 20 mA, selecting an I
OUTFS
can be set
OUTFS
of 20 mA will
provide the best distortion and noise performance also shown in
Figure 8. The noise performance of the AD9764 is affected by
the digital supply (DVDD), output frequency, and increases
with increasing clock rate as shown in Figure 13. Operating the
AD9764 with low voltage logic levels between 3 V and 3.3 V
will slightly reduce the amount of on-chip digital noise.
In summary, the AD9764 achieves the optimum distortion and
noise performance under the following conditions:
(1) Differential Operation.
(2) Positive voltage swing at I
(3) I
set to 20 mA.
OUTFS
OUTA
and I
limited to +0.5 V.
OUTB
(4) Analog Supply (AVDD) set at 5.0 V.
(5) Digital Supply (DVDD) set at 3.0 V to 3.3 V with appro-
priate logic levels.
Note that the ac performance of the AD9764 is characterized
under the above mentioned operating conditions.
DIGITAL INPUTS
The AD9764’s digital input consists of 14 data input pins and a
clock input pin. The 14-bit parallel data inputs follow standard
positive binary coding where DB13 is the most significant bit
(MSB), and DB0 is the least significant bit (LSB). I
OUTA
pro-
duces a full-scale output current when all data bits are at Logic
1. I
produces a complementary output with the full-scale
OUTB
current split between the two outputs as a function of the input
code.
The digital interface is implemented using an edge-triggered
master slave latch. The DAC output is updated following the
rising edge of the clock as shown in Figure 1 and is designed to
support a clock rate as high as 125 MSPS. The clock can be
operated at any duty cycle that meets the specified latch pulsewidth. The setup and hold times can also be varied within the
clock cycle as long as the specified minimum times are met,
although the location of these transition edges may affect digital
feedthrough and distortion performance. Best performance is
typically achieved when the input data transitions on the falling
edge of a 50% duty cycle clock.
The digital inputs are CMOS-compatible with logic thresholds,
V
THRESHOLD,
set to approximately half the digital positive supply
(DVDD) or
V
THRESHOLD
= DVDD/2 (±20%)
The internal digital circuitry of the AD9764 is capable of operating
over a digital supply range of 2.7 V to 5.5 V. As a result, the
digital inputs can also accommodate TTL levels when DVDD is
set to accommodate the maximum high level voltage of the TTL
drivers V
OH(MAX)
. A DVDD of 3 V to 3.3 V will typically ensure
proper compatibility with most TTL logic families. Figure 29
shows the equivalent digital input circuit for the data and clock
inputs. The sleep mode input is similar with the exception that
it contains an active pull-down circuit, thus ensuring that the
AD9764 remains enabled if this input is left disconnected.
–12–
Figure 29. Equivalent Digital Input
REV. B
AD9764
RATIO – f
OUT/fCLK
18
16
0
0.01 10.1
I
DVDD
– mA
8
6
4
2
12
10
14
5MSPS
25MSPS
50MSPS
100MSPS
125MSPS
Since the AD9764 is capable of being updated up to 125 MSPS,
the quality of the clock and data input signals are important in
achieving the optimum performance. Operating the AD9764
with reduced logic swings and a corresponding digital supply
(DVDD) will result in the lowest data feedthrough and on-chip
digital noise. The drivers of the digital data interface circuitry
should be specified to meet the minimum setup and hold times
of the AD9764 as well as its required min/max input logic level
thresholds.
Digital signal paths should be kept short and run lengths
matched to avoid propagation delay mismatch. The insertion
of a low value resistor network (i.e., 20 Ω to 100 Ω) between
the AD9764 digital inputs and driver outputs may be helpful in
reducing any overshooting and ringing at the digital inputs that
contribute to data feedthrough. For longer run lengths and high
data update rates, strip line techniques with proper termination
resistors should be considered to maintain “clean” digital inputs.
The external clock driver circuitry should provide the AD9764
with a low jitter clock input meeting the min/max logic levels
while providing fast edges. Fast clock edges will help minimize
any jitter that will manifest itself as phase noise on a reconstructed waveform. Thus, the clock input should be driven by
the fastest logic family suitable for the application.
Note, that the clock input could also be driven via a sine wave,
which is centered around the digital threshold (i.e., DVDD/2)
and meets the min/max logic threshold. This will typically result
in a slight degradation in the phase noise, which becomes more
noticeable at higher sampling rates and output frequencies.
Also, at higher sampling rates, the 20% tolerance of the digital
logic threshold should be considered since it will affect the effective clock duty cycle and, subsequently, cut into the required
data setup and hold times.
30
25
20
– mA
15
AVDD
I
10
5
0
2204 6 8 10 12141618
Figure 30. I
Conversely, I
form, f
CLOCK
show I
DVDD
(f
OUT/fCLOCK
is dependent on both the digital input wave-
DVDD
, and digital supply DVDD. Figures 31 and 32
as a function of full-scale sine wave output ratios
) for various update rates with DVDD = 5 V and
DVDD = 3 V, respectively. Note, how I
I
OUTFS
AVDD
– mA
vs. I
OUTFS
is reduced by more
DVDD
than a factor of 2 when DVDD is reduced from 5 V to 3 V.
SLEEP MODE OPERATION
The AD9764 has a power-down function that turns off the
output current and reduces the supply current to less than
8.5 mA over the specified supply range of 2.7 V to 5.5 V and
temperature range. This mode can be activated by applying a
logic level “1” to the SLEEP pin. This digital input also contains an active pull-down circuit that ensures the AD9764 remains enabled if this input is left disconnected. The SLEEP
input with active pull-down requires <40 µA of drive current.
The power-up and power-down characteristics of the AD9764
are dependent upon the value of the compensation capacitor
connected to COMP1. With a nominal value of 0.1 µF, the
AD9764 takes less than 5 µs to power down and approximately
3.25 ms to power back up. Note, the SLEEP MODE should not
be used when the external control amplifier is used as shown in
Figure 27.
POWER DISSIPATION
The power dissipation, PD, of the AD9764 is dependent on
several factors, including: (1) AVDD and DVDD, the power
supply voltages; (2) I
, the update rate; and (4) the reconstructed digital input
f
CLOCK
waveform. The power dissipation is directly proportional to the
analog supply current, I
. I
I
DVDD
Figure 30, and is insensitive to f
REV. B
, the full-scale current output; (3)
OUTFS
, and the digital supply current,
is directly proportional to I
AVDD
AVDD
CLOCK
.
OUTFS,
as shown in
–13–
Figure 31. I
8
6
– mA
4
DVDD
I
2
0
0.01 10.1
Figure 32. I
vs. Ratio @ DVDD = 5 V
DVDD
RATIO – f
vs. Ratio @ DVDD = 3 V
DVDD
125MSPS
100MSPS
50MSPS
25MSPS
5MSPS
OUT/fCLK
AD9764
AD9764
22
I
OUTA
I
OUTB
21
C
OPT
500V
225V
225V
500V
25V25V
AD8047
APPLYING THE AD9764
OUTPUT CONFIGURATIONS
The following sections illustrate some typical output configurations for the AD9764. Unless otherwise noted, it is assumed
that I
is set to a nominal 20 mA. For applications requir-
OUTFS
ing the optimum dynamic performance, a differential output
configuration is suggested. A differential output configuration
may consist of either an RF transformer or a differential op amp
configuration. The transformer configuration provides the optimum high frequency performance and is recommended for any
application allowing for ac coupling. The differential op amp
configuration is suitable for applications requiring dc coupling, a
bipolar output, signal gain and/or level shifting.
A single-ended output is suitable for applications requiring a
unipolar voltage output. A positive unipolar output voltage will
result if I
OUTA
and/or I
sized load resistor, R
is connected to an appropriately
OUTB
, referred to ACOM. This configura-
LOAD
tion may be more suitable for a single-supply system requiring a
dc coupled, ground referred output voltage. Alternatively, an
amplifier could be configured as an I-V converter, thus convert-
OUTA
or I
ing I
figuration provides the best dc linearity since I
maintained at a virtual ground. Note, I
better performance than I
into a negative unipolar voltage. This con-
OUTB
OUTB
.
OUTA
or I
OUTA
provides slightly
OUTB
DIFFERENTIAL COUPLING USING A TRANSFORMER
An RF transformer can be used to perform a differential-tosingle-ended signal conversion as shown in Figure 33. A
differentially coupled transformer output provides the optimum
distortion performance for output signals whose spectral content
lies within the transformer’s passband. An RF transformer such
as the Mini-Circuits T1-1T provides excellent rejection of common-mode distortion (i.e., even-order harmonics) and noise
over a wide frequency range. It also provides electrical isolation
and the ability to deliver twice the power to the load. Transformers with different impedance ratios may also be used for
impedance matching purposes. Note that the transformer
provides ac coupling only.
MINI-CIRCUITS
I
OUTA
AD9764
I
OUTB
22
21
T1-1T
OPTIONAL R
DIFF
R
LOAD
Figure 33. Differential Output Using a Transformer
The center tap on the primary side of the transformer must be
connected to ACOM to provide the necessary dc current path
for both I
ing at I
OUTA
OUTA
and I
and I
. The complementary voltages appear-
OUTB
OUTB
(i.e., V
OUTA
and V
) swing sym-
OUTB
metrically around ACOM and should be maintained with the
specified output compliance range of the AD9764. A differential
resistor, R
output of the transformer is connected to the load, R
passive reconstruction filter or cable. R
transformer’s impedance ratio and provides the proper source
termination that results in a low VSWR. Note that approximately half the signal power will be dissipated across R
, may be inserted in applications in which the
DIFF
is determined by the
DIFF
LOAD
DIFF
is
, via a
.
DIFFERENTIAL USING AN OP AMP
An op amp can also be used to perform a differential-to-singleended conversion as shown in Figure 34. The AD9764 is configured with two equal load resistors, R
differential voltage developed across I
OUTA
, of 25 Ω. The
LOAD
and I
OUTB
is converted to a single-ended signal via the differential op amp configuration. An optional capacitor can be installed across I
and I
, forming a real pole in a low-pass filter. The addition
OUTB
OUTA
of this capacitor also enhances the op amp’s distortion performance by preventing the DAC’s high slewing output from overloading the op amp’s input.
Figure 34. DC Differential Coupling Using an Op Amp
The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the differential op amp circuit using the AD8047 is configured to provide
some additional signal gain. The op amp must operate from a
dual supply since its output is approximately ±1.0 V. A high
speed amplifier capable of preserving the differential performance of the AD9764 while meeting other system level objectives
(i.e., cost, power) should be selected. The op amps differential
gain, its gain setting resistor values and full-scale output swing
capabilities should all be considered when optimizing this circuit.
The differential circuit shown in Figure 35 provides the necessary level-shifting required in a single supply system. In this
case, AVDD, which is the positive analog supply for both the
AD9764 and the op amp, is also used to level-shift the differential output of the AD9764 to midsupply (i.e., AVDD/2). The
AD8041 is a suitable op amp for this application.
500V
AD9764
I
OUTA
I
OUTB
22
21
C
OPT
225V
1kV
AD8041
1kV
AVDD
225V
25V25V
Figure 35. Single-Supply DC Differential Coupled Circuit
SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT
Figure 36 shows the AD9764 configured to provide a unipolar
output range of approximately 0 V to +0.5 V for a doubly termi-
nated 50 Ω cable since the nominal full-scale current, I
20 mA flows through the equivalent R
represents the equivalent load resistance seen by I
R
LOAD
. The unused output (I
I
OUTB
OUTA
or I
ACOM directly or via a matching R
of 25 Ω. In this case,
LOAD
) can be connected to
OUTB
. Different values of
LOAD
–14–
OUTFS
OUTA
REV. B
, of
or
100mF
ELECT.
10-22mF
TANT.
0.1mF
CER.
TTL/CMOS
LOGIC
CIRCUITS
+5V OR +3V
POWER SUPPLY
FERRITE
BEADS
AVDD
ACOM
I
OUTFS
and R
can be selected as long as the positive compli-
LOAD
ance range is adhered to. One additional consideration in this
mode is the integral nonlinearity (INL) as discussed in the Analog Output section of this data sheet. For optimum INL performance, the single-ended, buffered voltage output configuration
is suggested.
AD9764
I
OUTA
I
OUTB
I
= 20mA
OUTFS
22
50V
21
25V
V
OUTA
= 0 TO +0.5V
50V
Figure 36. 0 V to +0.5 V Unbuffered Voltage Output
SINGLE-ENDED BUFFERED VOLTAGE OUTPUT
CONFIGURATION
Figure 37 shows a buffered single-ended output configuration in
which the op amp U1 performs an I-V conversion on the
AD9764 output current. U1 maintains I
OUTA
(or I
OUTB
) at a
virtual ground, thus minimizing the nonlinear output impedance
effect on the DAC’s INL performance as discussed in the Analog Output section. Although this single-ended configuration
typically provides the best dc linearity performance, its ac distortion performance at higher DAC update rates may be limited by
U1’s slewing capabilities. U1 provides a negative unipolar
output voltage and its full-scale output voltage is simply the
product of R
FB
and I
within U1’s voltage output swing capabilities by scaling I
. The full-scale output should be set
OUTFS
OUTFS
and/or RFB. An improvement in ac distortion performance may
result with a reduced I
since the signal current U1 will be
OUTFS
required to sink will be subsequently reduced.
C
OPT
R
FB
200V
AD9764
I
OUTA
I
OUTB
I
= 10mA
OUTFS
22
U1
21
200V
V
= I
OUTFS
3 R
FB
OUT
Figure 37. Unipolar Buffered Voltage Output
POWER AND GROUNDING CONSIDERATIONS
In systems seeking to simultaneously achieve high speed and
high performance, the implementation and construction of the
printed circuit board design is often as important as the circuit
design. Proper RF techniques must be used in device selection,
placement and routing and supply bypassing and grounding.
Figures 42–47 illustrate the recommended printed circuit board
ground, power and signal plane layouts that are implemented on
the AD9764 evaluation board.
Proper grounding and decoupling should be a primary objective
in any high speed, high resolution system. The AD9764 features
separate analog and digital supply and ground pins to optimize
the management of analog and digital ground currents in a
AD9764
system. In general, AVDD, the analog supply, should be decoupled
to ACOM, the analog common, as close to the chip as physically possible. Similarly, DVDD, the digital supply, should be
decoupled to DCOM as close as physically as possible.
For those applications requiring a single +5 V or +3 V supply
for both the analog and digital supply, a clean analog supply
may be generated using the circuit shown in Figure 38. The
circuit consists of a differential LC filter with separate power
supply and return lines. Lower noise can be attained using low
ESR type electrolytic and tantalum capacitors.
Figure 38. Differential LC Filter for Single +5 V or +3 V
Applications
Maintaining low noise on power supplies and ground is critical
to obtain optimum results from the AD9764. If properly
implemented, ground planes can perform a host of functions on
high speed circuit boards: bypassing, shielding current transport, etc. In mixed signal design, the analog and digital portions
of the board should be distinct from each other, with the analog
ground plane confined to the areas covering the analog signal
traces, and the digital ground plane confined to areas covering
the digital interconnects.
All analog ground pins of the DAC, reference and other analog
components should be tied directly to the analog ground plane.
The two ground planes should be connected by a path 1/8 to
1/4 inch wide underneath or within 1/2 inch of the DAC to
maintain optimum performance. Care should be taken to ensure
that the ground plane is uninterrupted over crucial signal paths.
On the digital side, this includes the digital input lines running
to the DAC as well as any clock signals. On the analog side, this
includes the DAC output signal, reference signal and the supply
feeders.
The use of wide runs or planes in the routing of power lines is
also recommended. This serves the dual role of providing a low
series impedance power supply to the part, as well as providing
some “free” capacitive decoupling to the appropriate ground
plane. It is essential that care be taken in the layout of signal and
power ground interconnects to avoid inducing extraneous voltage drops in the signal ground paths. It is recommended that all
connections be short, direct and as physically close to the package as possible in order to minimize the sharing of conduction
paths between different currents. When runs exceed an inch in
length, strip line techniques with proper termination resistors
should be considered. The necessity and value of this resistor
will be dependent upon the logic family used.
For a more detailed discussion of the implementation and construction of high speed, mixed signal printed circuit boards,
refer to Analog Devices’ application notes AN-280 and AN-333.
REV. B
–15–
AD9764
MULTITONE PERFORMANCE CONSIDERATIONS AND
CHARACTERIZATION
The frequency domain performance of high speed DACs has
traditionally been characterized by analyzing the spectral output
of a reconstructed full-scale (i.e., 0 dBFS), single-tone sine wave
at a particular output frequency and update rate. Although this
characterization data is useful, it is often insufficient to reflect a
DAC’s performance for a reconstructed multitone or spreadspectrum waveform. In fact, evaluating a DAC’s spectral
performance using a full-scale, single tone at the highest specified
frequency (i.e., f
) of a bandlimited waveform is typically
H
indicative of a DAC’s “worst-case” performance for that given
waveform. In the time domain, this full-scale sine wave represents the lowest peak-to-rms ratio or crest factor (i.e., V
PEAK
/V
rms) that this bandlimited signal will encounter.
–10
–20
–30
–40
–50
–60
–70
MAGNITUDE – dBm
–80
–90
–100
–110
2.19 2.812.25 2.31 2.38 2.44 2.50 2.56 2.63 2.69 2.75
FREQUENCY – MHz
Figure 39a. Multitone Spectral Plot
1.0000
0.8000
0.6000
0.4000
0.2000
0.0000
VOLTS
–0.2000
–0.4000
–0.6000
–0.8000
–1.0000
TIME
Figure 39b. Time Domain “Snapshot” of the Multitone
Waveform
However, the inherent nature of a multitone, spread spectrum,
or QAM waveform, in which the spectral energy of the waveform is spread over a designated bandwidth, will result in a
higher peak-to-rms ratio when compared to the case of a simple
sine wave. As the reconstructed waveform’s peak-to-average
ratio increases, an increasing amount of the signal energy is
concentrated around the DAC’s midscale value. Figure 39a is
just one example of a bandlimited multitone vector (i.e., eight
tones) centered around one-half the Nyquist bandwidth (i.e.,
/4). This particular multitone vector, has a peak-to-rms
f
CLOCK
ratio of 13.5 dB compared to a sine waves peak-to-rms ratio of
3 dB. A “snapshot” of this reconstructed multitone vector in the
time domain as shown in Figure 39b reveals the higher signal
content around the midscale value. As a result, a DAC’s
“small-scale” dynamic and static linearity becomes increasingly critical in obtaining low intermodulation distortion and
maintaining sufficient carrier-to-noise ratios for a given modulation scheme.
A DAC’s small-scale linearity performance is also an important
consideration in applications where additive dynamic range is
required for gain control purposes or “predistortion” signal
conditioning. For instance, a DAC with sufficient dynamic
range can be used to provide additional gain control of its
reconstructed signal. In fact, the gain can be controlled in
6 dB increments by simply performing a shift left or right on the
DAC’s digital input word. Other applications may intentionally
predistort a DAC’s digital input signal to compensate for
nonlinearities associated with the subsequent analog components in the signal chain. For example, the signal compression
associated with a power amplifier can be compensated for by
predistorting the DAC’s digital input with the inverse nonlinear
transfer function of the power amplifier. In either case, the
DAC’s performance at reduced signal levels should be carefully
evaluated.
A full-scale single tone will induce all of the dynamic and static
nonlinearities present in a DAC that contribute to its distortion
and hence SFDR performance. Referring to Figure 3, as the
frequency of this reconstructed full-scale, single-tone waveform
increases, the dynamic nonlinearities of any DAC (i.e., AD9764)
tend to dominate thus contributing to the rolloff in its SFDR
performance. However, unlike most DACs, which employ an R-2R
ladder for the lower bit current segmentation, the AD9764 (as
well as other TxDAC members) exhibits an improvement in
distortion performance as the amplitude of a single tone is reduced from its full-scale level. This improvement in distortion
performance at reduced signal levels is evident if one compares
the SFDR performance vs. frequency at different amplitudes
(i.e., 0 dBFS, –6 dBFS and –12 dBFS) and sample rates as
shown in Figures 4 through 7. Maintaining decent “small-scale”
linearity across the full span of a DAC transfer function is also
critical in maintaining excellent multitone performance.
Although characterizing a DAC’s multitone performance tends
to be application-specific, much insight into the potential performance of a DAC can also be gained by evaluating the DAC’s
swept power (i.e., amplitude) performance for single, dual and
multitone test vectors at different clock rates and carrier frequencies. The DAC is evaluated at different clock rates when reconstructing a specific waveform whose amplitude is decreased in
3 dB increments from full-scale (i.e., 0 dBFS). For each specific
waveform, a graph showing the SFDR (over Nyquist) performance vs. amplitude can be generated at the different tested
clock rates as shown in Figures 9–11. Note that the carrier(s)to-clock ratio remains constant in each figure. In each case, an
improvement in SFDR performance is seen as the amplitude is
reduced from 0 dBFS to approximately –9.0 dBFS.
A multitone test vector may consist of several equal amplitude,
spaced carriers each representative of a channel within a defined
bandwidth as shown in Figure 39a. In many cases, one or more
tones are removed so the intermodulation distortion performance
–16–
REV. B
AD9764
of the DAC can be evaluated. Nonlinearities associated with the
DAC will create spurious tones of which some may fall back into
the “empty” channel thus limiting a channel’s carrier-to-noise
ratio. Other spurious components falling outside the band of
interest may also be important, depending on the system’s spectral
mask and filtering requirements.
This particular test vector was centered around one-half the
Nyquist bandwidth (i.e., f
Centering the tones at a much lower region (i.e., f
/4) with a passband of f
CLOCK
CLOCK
CLOCK
/16.
/10)
would lead to an improvement in performance while centering
the tones at a higher region (i.e., f
/2.5) would result in a
CLOCK
degradation in performance. Figure 40a shows the SFDR vs.
amplitude at different sample rates up to the Nyquist frequency
while Figure 40b shows the SFDR vs. amplitude within the
passband of the test vector. In assessing a DAC’s multitone
performance, it is also recommended that several units be tested
under exactly the same conditions to determine any performance
variability.
80
75
70
65
60
55
50
SFDR – dBc
45
40
35
30
–20 –15 0
Figure 40a. Multitone SFDR vs. A
10 MSPS
50 MSPS
20 MSPS
100 MSPS
A
OUT
–10 –5
– dBFS
OUT
(Up to Nyquist)
AD9764 EVALUATION BOARD
General Description
The AD9764-EB is an evaluation board for the AD9764 14-bit
DAC converter. Careful attention to layout and circuit design,
combined with a prototyping area, allows the user to easily and
effectively evaluate the AD9764 in any application where high
resolution, high speed conversion is required.
This board allows the user the flexibility to operate the AD9764
in various configurations. Possible output configurations include
transformer coupled, resistor terminated, inverting/noninverting
and differential amplifier outputs. The digital inputs are designed
to be driven directly from various word generators with the
onboard option to add a resistor network for proper load termination. Provisions are also made to operate the AD9764 with
either the internal or external reference or to exercise the powerdown feature.
Refer to the application note AN-420, Using the AD9760/AD9764/
AD9764-EB Evaluation Board for a thorough description and
operating instructions for the AD9764 evaluation board.
80
75
70
65
60
SFDR – dBc
55
50
45
40
–20 –15 0–10 –5
50 MSPS
A
OUT
20 MSPS
100 MSPS
– dBFS
Figure 40b. Multitone SFDR vs. A
Passband)
10 MSPS
(Within Multitone
OUT
REV. B
–17–
AD9764
AVCC
AVEE
AGND
AVDD
DGND
DVDD
TP13
A
B
2
1
3
JP3
TP8
C9
0.1mF
A
AVDD
C8
0.1mF
C7
1mF
3
2
CLK
JP1
1
AB
R15
49.9V
TP1
J1
EXTCLK
A
DVDD
C6
10mF
TP7
B6
A
C5
10mF
TP6
B5
TP5
TP19
TP18
B4
B3
B2
B1
TP4
TP2
TP3
A
C4
10mF
DVDD
C3
10mF
R7
R3
R5
R1
U1
1
1
RES PK
16 PINDIP
1
1
2827262524
DVDD
CLOCK
AD9764
DB13
DB12
123456789
10
98765432
10
98765432
16151413121110
1234567
C19C1C2
10
98765432
10
98765432
13579
P1
246
OUT 2
OUT 1
TP10 TP9
TP11
AVDD
ACOM
FS ADJ
COMP1
DB5
DB4
DB3
1011121314
16 PINDIP
15
16
REFIO
SLEEP
REFLO
DB2
DB1
DB0
RES PK
25
2729313335
1615141312
12345
C30
23222120191817
NC
AVDD
DCOM
IOUTA
IOUTB
COMP2
DB11
DB10
DB9
DB8
DB7
DB6
9
8
C25
C26
C27
C28
C29
11131517192123
8
101214161820222426283032343638
C10
0.1mF
AVDD
TP14
R16
2kV
JP4
C11
0.1mF
1
2
3
AVDD
A
A
CT1
C31
C32
C33
C34
37
A A A
JP2
J2
PDIN
R17
49.9V
TP12
1
DVDD
R8
1098765432
1
R4
1098765432
11
10
6
7
C35
C36
39
40
1098765432
98765432
10
1
DVDD
R6
1
R2
AVCC
R18
C17
0.1mF
AVCC
R42
1kV
6
VOUT
U7
GND
REF43
VIN
2
C16
AVCC
C18
J6
C22
1mF
A
C21
0.1mF
7
U4
3
1kV
JP8
A
JP7A
JP7B
R12
JP6A
J7
OUT1
J3
A
7
U6
3
R43
4
1mF
0.1mF
R37
6
AD8047
2
B
B
B
OPEN
C12
22pF
R20
49.9V
A
4
6
5kV
49.9V
4
C20
CW
R10
A
0
3
AVEE
4
AD8047
2
A
A
A
A
1kV
A
A
T1
5
0
R14
A A
123
JP5
R45
1kV
C14
1mF
J5
EXTREFIN
R36
1kV
JP6B
1
6
A
A
R13
R35
A
R9
J4
C15
R44
C24
C23
1kV
1kV
OPEN
A
0.1mF
R46
50V
1mF
0.1mF
OUT2
A
1kV
A
A
A
AVEE
B
A
JP9
A
C13
22pF
R38
49.9V
A A
Figure 41. Evaluation Board Schematic
–18–
REV. B
AD9764
Figure 42. Silkscreen Layer—Top
REV. B
Figure 43. Component Side PCB Layout (Layer 1)
–19–
AD9764
Figure 44. Ground Plane PCB Layout (Layer 2)
Figure 45. Power Plane PCB Layout (Layer 3)
–20–
REV. B
AD9764
Figure 46. Solder Side PCB Layout (Layer 4)
REV. B
Figure 47. Silkscreen Layer—Bottom
–21–
AD9764
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead, 300 Mil SOIC
(R-28)
0.7125 (18.10)
0.6969 (17.70)
28 15
1
PIN 1
0.0500
0.0118 (0.30)
0.0040 (0.10)
28 15
PIN 1
0.006 (0.15)
0.002 (0.05)
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.386 (9.80)
0.378 (9.60)
0.2992 (7.60)
0.2914 (7.40)
14
0.1043 (2.65)
0.0926 (2.35)
SEATING
0.0125 (0.32)
PLANE
0.0091 (0.23)
28-Lead TSSOP
(RU-28)
0.177 (4.50)
0.169 (4.30)
141
0.0433 (1.10)
MAX
0.4193 (10.65)
0.3937 (10.00)
0.0291 (0.74)
0.0098 (0.25)
88
08
0.256 (6.50)
0.246 (6.25)
C2467b–1–10/99
3 458
0.0500 (1.27)
0.0157 (0.40)
SEATING
PLANE
0.0256 (0.65)
BSC
0.0118 (0.30)
0.0075 (0.19)
–22–
0.0079 (0.20)
0.0035 (0.090)
88
08
0.028 (0.70)
0.020 (0.50)
PRINTED IN U.S.A.
REV. B
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