ANALOG DEVICES AD9763 Service Manual

10-/12-/14-Bit, 125 MSPS

Dual TxDAC+ Digital-to-Analog Converters

Data Sheet

FEATURES

10-/12-/14-bit dual transmit digital-to-analog converters (DACs) 125 MSPS update rate Excellent SFDR to Nyquist @ 5 MHz output: 75 dBc Excellent gain and offset matching: 0.1% Fully independent or single-resistor gain control Dual-port or interleaved data On-chip 1.2 V reference 5 V or 3.3 V operation Power dissipation: 380 mW @ 5 V Power-down mode: 50 mW @ 5 V 48-lead LQFP

APPLICATIONS

Communications Base stations Digital synthesis Quadrature modulation 3D ultrasound

GENERAL DESCRIPTION

The AD9763/AD9765/AD9767 are dual-port, high speed, 2-channel, 10-/12-/14-bit CMOS DACs. Each part integrates two high quality TxDAC+® cores, a voltage reference, and digital interface circuitry into a small 48-lead LQFP. The AD9763/ AD9765/AD9767 offer exceptional ac and dc performance while supporting update rates of up to 125 MSPS.

The AD9763/AD9765/AD9767 have been optimized for processing I and Q data in communications applications. The digital interface consists of two double-buffered latches as well as control logic. Separate write inputs allow data to be written to the two DAC ports independent of one another. Separate clocks control the update rate of the DACs.

A mode control pin allows the AD9763/AD9765/AD9767 to interface to two separate data ports, or to a single interleaved high speed data port. In interleaving mode, the input data stream is demuxed into its original I and Q data and then latched. The I and Q data is then converted by the two DACs and updated at half the input data rate.

The GAINCTRL pin allows two modes for setting the full-scale current (I independently using two external resistors, or I DACs can be set by using a single external resistor. See the Gain Control Mode section for important date code information on this feature.

) of the two DACs. I

OUTFS

for each DAC can be set

OUTFS

for both

OUTFS

AD9763/AD9765/AD9767

FUNCTIONAL BLOCK DIAGRAM

DCOM1/

DVDD1/

DCOM2

DVDD2

PORT1

WRT1/IQWRT

WRT2/IQSEL

PORT2

DIGITAL

INTERFACE

MODE

1

LATCH

AD9763/ AD9765/

AD9767

2

LATCH

Figure 1.

The DACs utilize a segmented current source architecture combined with a proprietary switching technique to reduce glitch energy and maximize dynamic accuracy. Each DAC provides differential current output, thus supporting single-ended or differential applications. Both DACs of the AD9763, AD9765, or AD9767 can be simultaneously updated and can provide a nominal full-scale current of 20 mA. The full-scale currents between each DAC are matched to within 0.1%.

The AD9763/AD9765/AD9767 are manufactured on an advanced, low cost CMOS process. They operate from a single supply of 3.3 V to 5 V and consume 380 mW of power.

PRODUCT HIGHLIGHTS

1. The AD9763/AD9765/AD9767 are members of a pin-

compatible family of dual TxDACs providing 8-, 10-, 12-, and 14-bit resolution.

2. Dual 10-/12-/14-Bit, 125 MSPS DACs. A pair of high

performance DACs for each part is optimized for low distortion performance and provides flexible transmission of I and Q information.

3. Matching. Gain matching is typically 0.1% of full scale, and

offset error is better than 0.02%.

4. Low Power. Complete CMOS dual DAC function operates on

380 mW from a 3.3 V to 5 V single supply. The DAC full-scale current can be reduced for lower power operation, and a sleep mode is provided for low power idle periods.

5. On-Chip Voltage Reference. The AD9763/AD9765/AD9767

each include a 1.20 V temperature-compensated band gap voltage reference.

6. Dual 10-/12-/14-Bit Inputs. The AD9763/AD9765/AD9767

each feature a flexible dual-port interface, allowing dual or interleaved input data.

CLK1AVDD ACOM

1

DAC

REFERENCE

BIAS

GENERATOR

2

DAC

CLK2/IQ RESET

I

OUTA1

I

OUTB1

REFIO FSADJ1 FSADJ2 GAINCTRL

SLEEP

I

OUTA2

I

OUTB2

00617-001

Rev. G

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9763/AD9765/AD9767 Data Sheet

REVISION HISTORY

Revision History: AD9763/AD9765/AD9767

8/11—Rev. F to Rev. G

Changes to Gain Control Mode Section and Setting the Full-

Scale Current Section..................................................................... 22

Changes to DAC Transfer Function Section............................... 23

Changes to Power Supply Rejection Section............................... 29

6/09—Rev. E to Rev. F

Replaced Figure 86 to Figure 90 with Figure 86 to Figure 91,

Deleted Original Figure 91 to Figure 94...................................... 34

1/08—Revision E: Initial Combined Version

Rev. G | Page 2 of 44

Revision History: AD9763

1/08—Rev. D to Rev. E

Combined with AD9765 and AD9767 Data Sheets.......Universal

Changes to Figure 1...........................................................................1

Changes to Applications Section .....................................................1

Changes to Timing Diagram Section .............................................7

Added Figure 4 and Figure 5............................................................9

Changes to Table 6.......................................................................... 10

Change to Typical Performance Characteristics Section

Conditions Statement .................................................................... 11

Added Figure 23 to Figure 56 ....................................................... 14

Added Note to Figure 58 ............................................................... 20

Changes to Functional Description Section ............................... 22

Changes to Figure 59 and Figure 60............................................. 22

Changes to Gain Control Mode Section ..................................... 22

Data Sheet AD9763/AD9765/AD9767

Replaced Reference Control Amplifier Section with Setting

the Full-Scale Current Section.......................................................22

Changes to DAC Transfer Section ................................................23

Change to Analog Outputs Section ..............................................24

Changes to Dual-Port Mode Timing............................................24

Changes to Interleaved Mode Timing Section ............................25

Added Figure 64 ..............................................................................25

Change to Differential Coupling Using a Transformer Section .....28

Changes to Power and Grounding Considerations Section............ 30

Added VDSL Example Applications Using the AD9765 and

AD9767 Section...............................................................................31

Added Figure 79 to Figure 82........................................................31

Changes to Figure 84 ......................................................................32

Changes to CDMA Section............................................................33

Changes to Figure 85 Caption .......................................................33

Changes to Figure 86 ......................................................................34

Changes to Figure 88 ......................................................................36

Changes to Ordering Guide...........................................................40

9/06—Rev. C to Rev. D

Updated Format.................................................................. Universal

Renumbered Figures.......................................................... Universal

Changes to Specifications Section...................................................3

Changes to Applications Section...................................................21

Updated Outline Dimensions........................................................32

Changes to Ordering Guide...........................................................32

10/01—Rev. B to Rev. C

Changes to Figure 29 ......................................................................21

2/00—Rev. A to Rev. B

12/99—Rev. 0 to Rev. A

Revision History: AD9765

1/08—Rev. C to Rev. E

Combined with AD9763 and AD9767 Data Sheets ...... Universal

Changes to Figure 1...........................................................................1

Changes to Applications Section.....................................................1

Changes to Timing Diagram Section .............................................7

Change to Absolute Maximum Ratings .........................................8

Added Figure 3 and Figure 5 ...........................................................9

Changes to Table 6 ..........................................................................10

Added Figure 6 to Figure 22..........................................................11

Added Figure 40 to Figure 56........................................................17

Added Note to Figure 58 ................................................................20

Changes to Functional Description Section................................22

Changes to Reference Operation Section ....................................22

Changes to Figure 59 and Figure 60 .............................................22

Changes to Gain Control Mode Section ......................................22

Replaced Reference Control Amplifier Section with Setting

the Full-Scale Current Section.......................................................22

Changes to DAC Transfer Section ................................................23

Rev. G | Page 3 of 44

Changes to Interleaved Mode Timing Section............................25

Added Figure 64..............................................................................25

Changes to Power and Grounding Considerations Section............ 30

Added Figure 80 and Figure 82 ..................................................... 31

Changes to Quadrature Amplitude Modulation (QAM)

Example Using the AD9763 Section.............................................32

Changes to Figure 83 and Figure 84 .............................................32

Changes to CDMA Section............................................................33

Changes to Figure 85 Caption .......................................................33

Changes to Figure 86 ......................................................................34

Changes to Figure 88 ......................................................................36

Changes to Ordering Guide...........................................................40

9/06—Rev. B to Rev. C

Updated Format ................................................................. Universal

Changes to Figure 2 .......................................................................... 5

Changes to Figure 3 .......................................................................... 7

Changes to Functional Description Section................................12

Changes to Figure 25 and Figure 26 .............................................15

Changes to Figure 28 and Figure 29 .............................................16

Changes to Power Dissipation Section......................................... 17

Changes to Power and Grounding Considerations Section...... 19

Changes to Figure 39 ......................................................................19

Changes to Figure 45 ......................................................................22

Changes to Evaluation Board Section ..........................................24

Changes to Figure 47 ......................................................................24

Updated Outline Dimensions........................................................30

Changes to Ordering Guide...........................................................30

2/00—Rev. A to Rev. B

12/99—Rev. 0 to Rev. A

8/99—Revision 0: Initial Version

Revision History: AD9767

1/08—Rev. C to Rev. E

Combined with AD9763 and AD9765 Data Sheets...... Universal

Changes to Figure 1 .......................................................................... 1

Changes to Features Section............................................................1

Changes to Applications Section..................................................... 1

Changes to Timing Diagram Section ............................................. 7

Change to Absolute Maximum Ratings ......................................... 8

Added Figure 3 and Figure 4 ...........................................................9

Changes to Table 6 ..........................................................................10

Added Figure 6 to Figure 39..........................................................11

Added Note to Figure 58 ................................................................20

Changes to Functional Description Section................................22

Changes to Reference Operation Section ....................................22

Changes to Figure 59 and Figure 60 .............................................22

Changes to Gain Control Mode Section ......................................22

Replaced Reference Control Amplifier Section with Setting

the Full-Scale Current Section ......................................................22

Changes to DAC Transfer Section ................................................23

AD9763/AD9765/AD9767 Data Sheet

Changes to Dual-Port Mode Timing........................................... 24

Changes to Interleaved Mode Timing Section ........................... 25

Added Figure 64.............................................................................. 25

Change to Differential Coupling Using a Transformer Section......28

Changes to Power and Grounding Considerations Section............ 30

Added Figure 79 and Figure 81..................................................... 31

Added to Quadrature Amplitude Modulation (QAM)

Example Using the AD9763 Section ............................................ 32

Added Figure 83 and Figure 84..................................................... 32

Changes to CDMA Section ........................................................... 33

Changes to Figure 85 Caption....................................................... 33

Changes to Figure 86...................................................................... 34

Changes to Figure 88...................................................................... 36

Changes to Ordering Guide.......................................................... 40

10/06—Rev. B to Rev. C

Updated Format.................................................................. Universal

Changes to Figure 2...........................................................................5

Changes to Figure 3...........................................................................7

Changes to Functional Description Section ............................... 12

Changes to Figure 25 and Figure 26............................................. 15

Changes to Figure 28 and Figure 29............................................. 16

Changes to Power Dissipation Section ........................................ 18

Changes to Figure 39...................................................................... 19

Changes to Power and Grounding Considerations Section ..... 19

Changes to Figure 45...................................................................... 22

Changes to Figure 47...................................................................... 24

Updated Outline Dimensions....................................................... 28

Changes to Ordering Guide.......................................................... 28

2/00—Rev. A to Rev. B

12/99—Rev. 0 to Rev. A

8/99—Revision 0: Initial Version

Rev. G | Page 4 of 44

Data Sheet AD9763/AD9765/AD9767

SPECIFICATIONS

DC SPECIFICATIONS

T

to T

MIN

Table 1.

Parameter Min Typ Max Min Typ Max Min Typ Max Unit

RESOLUTION 10 12 14 Bits DC ACCURACY1

Integral Linearity Error (INL) −1 ±0.1 +1 LSB

Differential Nonlinearity (DNL) LSB

ANALOG OUTPUT

Offset Error −0.02 +0.02 −0.02 +0.02 −0.02 +0.02 % of FSR Gain Error Without Internal Reference −2 ±0.25 +2 −2 ±0.25 +2 −2 ±0.25 +2 % of FSR Gain Error with Internal Reference −5 ±1 +5 −5 ±1 +5 −5 ±1 +5 % of FSR Gain Match −1.6 ±0.1 +1.6 −1.6 ±0.1 +1.6 −1.6 ±0.1 +1.6 % of FSR

−0.14 +0.14 −0.14 +0.14 −0.14 +0.14 dB Full-Scale Output Current2 2.0 20.0 2.0 20.0 2.0 20.0 mA Output Compliance Range −1.0 +1.25 −1.0 +1.25 −1.0 +1.25 V Output Resistance 100 100 100 kΩ Output Capacitance 5 5 5 pF

REFERENCE OUTPUT

Reference Voltage 1.14 1.20 1.26 1.14 1.20 1.26 1.14 1.20 1.26 V Reference Output Current3 100 100 100 nA

REFERENCE INPUT

Input Compliance Range 0.1 1.25 0.1 1.25 0.1 1.25 V Reference Input Resistance 1 1 1 MΩ Small-Signal Bandwidth 0.5 0.5 0.5 MHz

TEMPERATURE COEFFICIENTS

Offset Drift 0 0 0 ppm of FSR/°C Gain Drift Without Internal Reference ±50 ±50 ±50 ppm of FSR/°C Gain Drift with Internal Reference ±100 ±100 ±100 ppm of FSR/°C Reference Voltage Drift ±50 ±50 ±50 ppm/°C

POWER SUPPLY

Supply Voltages

Analog Supply Current (I Digital Supply Current (I Digital Supply Current (I Supply Current Sleep Mode (I Power Dissipation4 (5 V, I

Power Dissipation5 (5 V, I Power Dissipation6 (5 V, I Power Supply Rejection Ratio7—AVDD –0.4 +0.4 –0.4 +0.4 –0.4 +0.4 % of FSR/V Power Supply Rejection Ratio7—DVDD

OPERATING RANGE –40 +85 –40 +85 –40 +85 °C

1

Measured at I

2

Nominal full-scale current, I

3

An external buffer amplifier with input bias current <100 nA should be used to drive any external load.

4

Measured at f

5

Measured at f

6

Measured as unbuffered voltage output with I

7

±10% power supply variation.

, AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V, I

MAX

AD9763 AD9765 AD9767

= 20 mA, unless otherwise noted.

OUTFS

TA = 25°C −1.5 ±0.4 +1.5 −3.5 ±1.5 +3.5 LSB T

to T

MIN

−2.0 +2.0 −4.0 +4.0 LSB

MAX

TA = 25°C −0.5 ±0.07 +0.5 −0.75 ±0.3 +0.75 −2.5 ±1.0 +2.5 LSB T

to T

MIN

−1.0 +1.0 −3.0 +3.0 LSB

MAX

AVDD 3 5 5.5 3 5 5.5 3 5 5.5 V DVDD1, DVDD2 2.7 5 5.5 2.7 5 5.5 2.7 5 5.5 V

) 71 75 71 75 71 75 mA

AVDD

)4 5 7 5 7 5 7 mA

DVDD

)5 15 15 15 mA

DVDD

) 8 12.0 8 12.0 8 12.0 mA

AVDD

= 20 mA)

OUTFS

= 20 mA)

OUTFS

= 20 mA) 450 450 450 mW

OUTFS

380 410 380 410 380 410 mW 420 450 420 450 420 450 mW

–0.025 +0.025 –0.025 +0.025 –0.025 +0.025 % of FSR/V

, driving a virtual ground.

OUTA

= 25 MSPS and f

CLK

= 100 MSPS and f

CLK

, is 32 times the I

OUTFS

= 1.0 MHz.

OUT

= 1 MHz.

OUT

current.

REF

= 20 mA and R

OUTFS

= 50 Ω at I

LOAD

OUTA

and I

, f

= 100 MSPS, and f

OUTB

CLK

= 40 MHz.

OUT

Rev. G | Page 5 of 44

AD9763/AD9765/AD9767 Data Sheet

DYNAMIC SPECIFICATIONS

T

to T

MIN

doubly terminated, unless otherwise noted.

Table 2.

AD9763 AD9765 AD9767 Parameter Min Typ Max Min Typ Max Min Typ Max Unit

DYNAMIC PERFORMANCE

Maximum Output Update Rate (f Output Settling Time (tST) to 0.1%1 35 35 35 ns Output Propagation Delay (tPD) 1 1 1 ns Glitch Impulse 5 5 5 pV-s Output Rise Time (10% to 90%)1 2.5 2.5 2.5 ns Output Fall Time (90% to 10%)1 2.5 2.5 2.5 ns Output Noise (I Output Noise (I

AC LINEARITY

Spurious-Free Dynamic Range to Nyquist

Spurious-Free Dynamic Range Within a Window

Total Harmonic Distortion

Multitone Power Ratio (Eight Tones at 110 kHz Spacing)

Channel Isolation

1

Measured single-ended into 50 Ω load.

, AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V, I

MAX

) 125 125 125 MSPS

CLK

= 20 mA) 50 50 50 pA/√Hz

OUTFS

= 2 mA) 30 30 30 pA/√Hz

OUTFS

f

= 100 MSPS, f

CLK

= 1.00 MHz

OUT

= 20 mA, differential transformer-coupled output, 50 Ω

OUTFS

0 dBFS Output 69 78 70 81 71 82 dBc –6 dBFS Output 74 77 77 dBc –12 dBFS Output 69 72 73 dBc –18 dBFS Output 61 70 70 dBc

f

= 65 MSPS, f

CLK

f

= 65 MSPS, f

CLK

f

= 65 MSPS, f

CLK

f

= 65 MSPS, f

CLK

f

= 65 MSPS, f

CLK

f

= 125 MSPS, f

CLK

f

= 125 MSPS, f

CLK

f

= 100 MSPS, f

CLK

f

= 50 MSPS, f

CLK

f

= 65 MSPS, f

CLK

f

= 125 MSPS, f

CLK

f

= 100 MSPS, f

CLK

f

= 50 MSPS, f

CLK

f

= 125 MSPS, f

CLK

f

= 125 MSPS, f

CLK

f

= 65 MSPS, f

CLK

= 1.00 MHz 79 81 82 dBc

OUT

= 2.51 MHz 78 79 80 dBc

OUT

= 5.02 MHz 75 78 79 dBc

OUT

= 14.02 MHz 66 68 70 dBc

OUT

= 25 MHz 55 55 55 dBc

OUT

= 25 MHz 67 67 67 dBc

OUT

= 40 MHz 60 60 70 dBc

OUT

= 1.00 MHz; 2 MHz Span 78 85 80 90 82 91 dBc

OUT

= 5.02 MHz; 10 MHz Span 80 88 88 dBc

OUT

= 5.03 MHz; 10 MHz Span 82 88 88 dBc

OUT

= 5.04 MHz; 10 MHz Span 82 88 88 dBc

OUT

= 1.00 MHz −77 −69 −80 –70 −81 −71 dBc

OUT

= 2.00 MHz −77 −78 −79 dBc

OUT

= 4.00 MHz −74 −75 −83 dBc

OUT

= 10.00 MHz −72 −75 −80 dBc

OUT

= 2.00 MHz to 2.99 MHz

OUT

0 dBFS Output 76 80 80 dBc

−6 dBFS Output 74 79 79 dBc

−12 dBFS Output 71 77 78 dBc

−18 dBFS Output 67 75 76 dBc

f

= 125 MSPS, f

CLK

f

= 125 MSPS, f

CLK

= 10 MHz 85 85 85 dBc

OUT

= 40 MHz 77 77 77 dBc

OUT

Rev. G | Page 6 of 44

Data Sheet AD9763/AD9765/AD9767

DIGITAL SPECIFICATIONS

T

to T

MIN

Table 3.

Parameter Min Typ Max Unit

DIGITAL INPUTS

Logic 1 Voltage @ DVDD1 = DVDD2 = 5 V 3.5 5 V Logic 1 Voltage @ DVDD1 = DVDD2 = 3.3 V 2.1 3 V Logic 0 Voltage @ DVDD1 = DVDD2 = 5 V 0 1.3 V Logic 0 Voltage @ DVDD1 = DVDD2 = 3.3 V 0 0.9 V Logic 1 Current −10 +10 μA Logic 0 Current −10 +10 μA Input Capacitance 5 pF Input Setup Time (tS) 2.0 ns Input Hold Time (tH) 1.5 ns Latch Pulse Width (t

Timing Diagram

See Tab l e 3 and the DAC Timing section for more information about the timing specifications.

, AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V, I

MAX

, t

) 3.5 ns

LPW

CPW

DATA IN

= 20 mA, unless otherwise noted.

OUTFS

t

S

t

H

(WRT2) (WRT1/IQWRT)

(CLK2) (CLK1/IQCLK)

I

OUTA

OR

I

OUTB

t

LPW

t

CPW

t

PD

00617-002

Figure 2. Timing Diagram for Dual and Interleaved Modes

Rev. G | Page 7 of 44

AD9763/AD9765/AD9767 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 4.

With

Parameter

AVDD ACOM −0.3 V to +6.5 V DVDD1, DVDD2 DCOM1/DCOM2 −0.3 V to +6.5 V ACOM DCOM1/DCOM2 −0.3 V to +0.3 V AVDD DVDD1/DVDD2 −6.5 V to +6.5 V MODE,

CLK1/IQCLK, CLK2/IQRESET, WRT1/IQWRT, WRT2/IQSEL

Digital Inputs DCOM1/DCOM2

I

OUTA1/IOUTA2

I

REFIO, FSADJ1,

FSADJ2 GAINCTRL, SLEEP ACOM −0.3 V to AVDD + 0.3 V Junction

Temperature Storage

Temperature

Range Lead Temperature

(10 sec)

,

OUTB1/IOUTB2

Respect To Ra ting

DCOM1/DCOM2

ACOM −1.0 V to AVDD + 0.3 V

ACOM −0.3 V to AVDD + 0.3 V

150°C

−65°C to +150°C

300°C

−0.3 V to DVDD1/ DVDD2 + 0.3 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θ

is specified for the worst-case conditions, that is, a device

JA

soldered in a circuit board for surface-mount packages.

Table 5. Thermal Resistance

Package Type θJA Unit

48-Lead LQFP 91 °C/W

ESD CAUTION

Rev. G | Page 8 of 44

Data Sheet AD9763/AD9765/AD9767

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

OUTA1

DB8P1

DB7P1

DB6P1

DB5P1

DB4P1

DB3P1

DB2P1

DB1P1

NC

1

2

3

4

5

6

7

8

9

10

11

12

DB9P1 (MSB)

DB0P1 (LSB)

NC = NO CONNECT

OUTA1

MODE

AVDD46I

48

47

PIN 1

13NC14NC15

OUTB1

I

45

44

(Not to Scale)

16

17

DVDD1

DCOM1

FSADJ143REFIO42GAINCTRL41FSADJ240I

AD9763

TOP VIEW

18

CLK1/IQCL K

WRT1/IQWRT

OUTB2

OUTA2

I

39

38

19

20

21

22

23

DVDD2

DCOM2

WRT2/IQSEL

CLK2/IQRESET

Figure 3. AD9763 Pin Configuration

ACOM37SLEEP

24

DB8P2

DB9P2 (MSB)

36

NC

35

NC

34

NC

33

NC

32

DB0P2 (LSB)

31

DB1P2

30

DB2P2

29

DB3P2

28

DB4P2

27

DB5P2

26

DB6P2

25

DB7P2

PIN 1

14

15

DB0P1 (LSB)

OUTB1

I

45

44

(Not to Scale)

16

17

DVDD1

DCOM1

FSADJ143REFIO42GAINCTRL41FSADJ240I

AD9767

TOP VIEW

18

CLK1/IQCL K

WRT1/IQWRT

MODE47AVDD46I

48

DB12P1

DB11P1

DB10P1

DB9P1

DB8P1

DB7P1

DB6P1

DB5P1

DB4P1

DB3P1

DB2P1

1

2

3

4

5

6

7

8

9

10

11

12

13

DB13P1 (MSB)

DB1P1

0617-003

Figure 5. AD9767 Pin Configuration

19

20

CLK2/IQRESET

OUTB2

OUTA2

I

ACOM37SLEEP

39

38

36

DB0P2 (LSB)

35

DB1P2

34

DB2P2

33

DB3P2

32

DB4P2

31

DB5P2

30

DB6P2

29

DB7P2

28

DB8P2

27

DB9P2

26

DB10P2

25

DB11P2

21

22

23

24

DVDD2

DCOM2

WRT2/IQSEL

DB12P2

DB13P2 (MSB)

0617-005

DB11P1 (MSB)

DB10P1

DB9P1

DB8P1

DB7P1

DB6P1

DB5P1

DB4P1

DB3P1

DB2P1

DB1P1

DB0P1 (LSB)

NC = NO CONNECT

OUTA1

47

PIN 1

AVDD46I

15

OUTB1

I

FSADJ143REFIO42GAINCTRL41FSADJ240I

45

44

AD9765

TOP VIEW

(Not to Scale)

16

17

18

19

MODE

48

1

2

3

4

5

6

7

8

9

10

11

12

13

NC14NC

DVDD1

DCOM1

CLK1/IQCL K

WRT1/IQWRT

CLK2/IQRESET

Figure 4. AD9765 Pin Configuration

OUTB2

OUTA2

I

ACOM37SLEEP

39

38

36

NC

35

NC

34

DB0P2 (LSB)

33

DB1P2

32

DB2P2

31

DB3P2

30

DB4P2

29

DB5P2

28

DB6P2

27

DB7P2

26

DB8P2

25

DB9P2

20

21

22

23

24

DVDD2

DCOM2

WRT2/IQSEL

DB10P2

DB11P2 (MSB)

0617-004

Rev. G

| Page 9 of 44

AD9763/AD9765/AD9767 Data Sheet

Table 6. Pin Function Descriptions

Pin No.

AD9763 AD9765 AD9767 Mnemonic Description

1 to 10 1 to 12 1 to 14 DBxP1 Data Bit Pins (Port 1) 11 to 14,

33 to 36

13, 14,

35, 36 15, 21 15, 21 15, 21 DCOM1, DCOM2 Digital Common 16, 22 16, 22 16, 22 DVDD1, DVDD2 Digital Supply Voltage 17 17 17 WRT1/IQWRT Input Write Signal for PORT 1 (IQWRT in Interleaving Mode) 18 18 18 CLK1/IQCLK Clock Input for DAC1 (IQCLK in Interleaving Mode) 19 19 19 CLK2/IQRESET Clock Input for DAC2 (IQRESET in Interleaving Mode) 20 20 20 WRT2/IQSEL Input Write Signal for PORT 2 (IQSEL in Interleaving Mode) 23 to 32 23 to 34 23 to 36 DBxP2 Data Bit Pins (Port 2) 37 37 37 SLEEP Power-Down Control Input 38 38 38 ACOM Analog Common 39, 40 39, 40 39, 40 I 41 41 41 FSADJ2 Full-Scale Current Output Adjust for DAC2 42 42 42 GAINCTRL Master/Slave Resistor Control Mode 43 43 43 REFIO Reference Input/Output 44 44 44 FSADJ1 Full-Scale Current Output Adjust for DAC1 45, 46 45, 46 45, 46 I 47 47 47 AVDD Analog Supply Voltage 48 48 48 MODE Mode Select (1 = dual port, 0 = interleaved)

N/A NC No Connect

, I

OUTA2

OUTB1

Port 2 Differential DAC Current Outputs

OUTB2

, I

Port 1 Differential DAC Current Outputs

OUTA1

Rev. G | Page 10 of 44

Data Sheet AD9763/AD9765/AD9767

TYPICAL PERFORMANCE CHARACTERISTICS

AD9763

AVDD = 3.3 V or 5 V, DVDD = 3.3 V, I unless otherwise noted.

90

80

f

= 5MSPS

CLK

f

= 25MSPS

70

SFDR (dBc)

60

50

1 10 100

CLK

f

= 65MSPS

CLK

f

OUT

Figure 6. SFDR vs. f

(MHz)

OUT

= 20 mA, 50 Ω doubly terminated load, differential output, TA = 25°C, SFDR up to Nyquist,

OUTFS

80

0dBFS

75

–6dBFS

f

OUT

(MHz)

OUT

@ 65 MSPS

@ 0 dBFS

f

= 125MSPS

CLK

70

–12dBFS

65

SFDR (dBc)

60

55

50

0 5 10 15 20 25 30 35

00617-006

Figure 9. SFDR vs. f

00617-009

80

0dBFS

75

SFDR (dBc)

70

65

0 0.5 1.0 1.5 2.0 2.5

80

75

70

SFDR (dBc)

65

–6dBFS

–12dBFS

f

(MHz)

OUT

Figure 7. SFDR vs. f

0dBFS

–12dBFS

@ 5 MSPS

OUT

–6dBFS

80

75

70

65

SFDR (dBc)

60

55

50

0 10203040506070

00617-007

80

75

70

65

SFDR (dBc)

60

55

0dBFS

–12dBFS

Figure 10. SFDR vs. f

I

= 20mA

OUTFS

I

OUTFS

f

= 5mA

–6dBFS

OUT

(MHz)

@ 125 MSPS

OUT

I

OUTFS

= 10mA

0617-010

60

02 1246810

Figure 8. SFDR vs. f

f

OUT

(MHz)

@ 25 MSPS

OUT

00617-008

Rev. G | Page 11 of 44

50

0 5 10 15 20 25 30 35

Figure 11. SFDR vs. f

OUT

f

OUT

and I

(MHz)

@ 65 MSPS and 0 dBFS

OUTFS

0617-011

AD9763/AD9765/AD9767 Data Sheet

85

80

75

70

SFDR (dBc)

65

60

55

–20 –16 –12 –8 –4 0

Figure 12. Single-Tone SFDR vs. A

85

80

75

70

SFDR (dBc)

65

60

55

–20 –16 –12 –8 –4 0

2MHz/10MSPS

Figure 13. Single-Tone SFDR vs. A

910kHz/10MSPS

2.27MHz/25M SPS

5.91MHz/65MSPS

(dBFS)

A

OUT

1MHz/5MSPS

13MHz/65MSP S

(dBFS)

A

OUT

11.37MHz/125M SPS

@ f

OUT

5MHz/25MSPS

25MHz/125MSPS

@ f

OUT

= f

CLK

/11

/5

0617-012

00617-013

70

I

= 20mA

OUTFS

65

I

= 10mA

OUTFS

SINAD (dBc)

60

I

= 5mA

OUTFS

55

20 40 60 80 100 120 140

Figure 15. SINAD vs. f

0.25

0.20

0.15

0.10

0.05

0

INL (LSB)

–0.05

–0.10

–0.15

–0.20

–0.25

0 200 400 600 800 1000

CLK

f

CLK

and I

(MSPS)

@ f

OUTFS

CODE

= 5 MHz and 0 dBFS

OUT

Figure 16. Typical INL

00617-015

0617-016

80

3.38MHz/3. 36MHz @ 25MSPS

75

70

65

SFDR (dBc)

60

55

6.75MHz/7. 25MHz @ 65MSPS

–20 –16 –12 –8 –4 0

Figure 14. Dual-Tone SFDR vs. A

0.965MHz/1.035MHz @ 7MSPS

16.9MHz/18. 1MHz @ 125MSPS

(dBFS)

A

OUT

@ f

OUT

= f

CLK

0.30

0.25

0.20

0.15

0.10

DNL (LSB)

0.05

0

–0.05

–0.10

0 200 40 0 600 800 1000

00617-014

/7

Figure 17. Typical DNL

CODE

00617-017

Rev. G | Page 12 of 44

Data Sheet AD9763/AD9765/AD9767

85

f

= 1MHz

80

75

70

65

SFDR (dBc)

60

55

50

45

–60 –40 –20 0 20 40 60 80 100

Figure 18. SFDR vs. Temperature @ f

OUT

f

= 10MHz

OUT

f

= 25MHz

OUT

f

= 40MHz

OUT

f

= 60MHz

OUT

TEMPERATURE (° C)

CLK

= 125 MSPS, 0 dBFS

00617-018

0

–10

–20

–30

–40

–50

SFDR (dBm)

–60

–70

–80

–90

0 1020304

Figure 21. Dual-Tone SFDR @ f

FREQUENCY (MHz )

CLK

= 125 MSPS

0

00617-021

0.05

0.03

OFFSET ERROR

0

OFFSET ERROR (%FS)

–0.03

–0.05

–40 –20 0 20 40 60 80

GAIN ERROR

TEMPERATURE (° C)

Figure 19. Gain and Offset Error vs. Temperature @ f

10

0

–10

–20

–30

–40

–50

SFDR (dBm)

–60

–70

–80

–90

0 1020304

Figure 20. Single-Tone SFDR @ f

FREQUENCY (MHz)

CLK

= 125 MSPS

CLK

= 125 MSPS

1.0

0.5

0

GAIN ERROR (%FS)

–0.5

–1.0

0

00617-020

0

–10

–20

–30

–40

–50

SFDR (dBm)

–60

–70

–80

–90

0 1020304

00617-019

Figure 22. Four-Tone SFDR @ f

FREQUENCY (MHz)

CLK

= 125 MSPS

0

00617-022

Rev. G | Page 13 of 44

AD9763/AD9765/AD9767 Data Sheet

AD9765

AVDD = 3.3 V or 5 V, DVDD = 3.3 V or 5 V, I Nyquist, unless otherwise noted.

90

f

= 5MSPS

CLK

f

= 25MSPS

CLK

80

f

= 65MSPS

@ 0 dBFS

OUT

CLK

70

SFDR (dBc)

60

f

CLK

50

110

f

(MHz)

OUT

Figure 23. SFDR vs. f

= 20 mA, 50 Ω doubly terminated load, differential output, TA = 25°C, SFDR up to

OUTFS

85

= 125MSPS

SFDR (dBc)

100

0617-023

80

75

70

65

60

55

50

0330252015105

0dBFS

–6dBFS

–12dBFS

f

OUT

Figure 26. SFDR vs. f

(MHz)

@ 65 MSPS

OUT

5

0617-026

95

90

85

SFDR (dBc)

80

75

1.00 2.252.001.751.501.25

90

85

80

75

SFDR (dBc)

70

–6dBFS

Figure 24. SFDR vs. f

–6dBFS

0dBFS

f

OUT

(MHz)

OUT

–12dBFS

@ 5 MSPS

–12dBFS

85

80

75

70

65

SFDR (dBc)

60

55

50

07605040302010

0617-024

85

80

75

70

65

SFDR (dBc)

60

0dBFS

–12dBFS

Figure 27. SFDR vs. f

I

OUTFS

= 5mA

I

OUTFS

= 10mA

f

OUT

(MHz)

@ 125 MSPS

OUT

= 20mA

I

OUTFS

–6dBFS

0

0617-027

65

60

01108642

f

OUT

Figure 25. SFDR vs. f

(MHz)

@ 25 MSPS

OUT

55

2

0617-025

50

03252015105

Figure 28. SFDR vs. f

OUT

and I

Rev. G | Page 14 of 44

f

(MHz)

OUT

@ 65 MSPS and 0 dBFS

OUTFS

0

0617-028

ANALOG DEVICES AD9763 Service Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

Revision History: AD9763/AD9765/AD9767

Revision History: AD9763

Revision History: AD9765

Revision History: AD9767

SPECIFICATIONS

DC SPECIFICATIONS

DYNAMIC SPECIFICATIONS

DIGITAL SPECIFICATIONS

Timing Diagram

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

AD9763

AD9765