Analog Devices AD9762ARU, AD9762AR, AD9762-EB Datasheet

12-Bit, 125 MSPS

(

)

a

FEATURES
Member of Pin-Compatible TxDAC Product Family
125 MSPS Update Rate
12-Bit Resolution
Excellent Spurious Free Dynamic Range Performance
SFDR to Nyquist @ 5 MHz Output: 70 dBc
Differential Current Outputs: 2 mA to 20 mA
Power Dissipation: 175 mW @ 5 V to 45 mW @ 3 V
Power-Down Mode: 25 mW @ 5 V
On-Chip 1.20 V Reference
Single +5 V or +3 V Supply Operation
Package: 28-Lead SOIC and TSSOP
Edge-Triggered Latches

APPLICATIONS
Communication Transmit Channel:

Basestations (Single/Multichannel Applications)

ADSL/HFC Modems
Direct Digital Synthesis (DDS)
Instrumentation

PRODUCT DESCRIPTION

The AD9762 is the 12-bit resolution member of the TxDAC
series of high performance, low power CMOS digital-to-analog
converters (DACs). The TxDAC
compatible 8-, 10-, 12-, and 14-bit DACs is specifically opti­mized for the transmit signal path of communication systems.
All of the devices share the same interface options, small outline
package and pinout, thus providing an upward or downward
component selection path based on performance, resolution and
cost. The AD9762 offers exceptional ac and dc performance
while supporting update rates up to 125 MSPS.

The AD9762’s flexible single-supply operating range of 2.7 V to

5.5 V and low power dissipation are well suited for portable and
low power applications. Its power dissipation can be further
reduced to a mere 45 mW without a significant degradation in
performance by lowering the full-scale current output. Also, a
power-down mode reduces the standby power dissipation to
approximately 25 mW.

The AD9762 is manufactured on an advanced CMOS process.
A segmented current source architecture is combined with a
proprietary switching technique to reduce spurious components
and enhance dynamic performance. Edge-triggered input
latches and a 1.2 V temperature compensated bandgap refer­ence have been integrated to provide a complete monolithic
DAC solution. Flexible supply options support +3 V and +5 V
CMOS logic families.

The AD9762 is a current-output DAC with a nominal full-scale
output current of 20 mA and > 100 kΩ output impedance.

TxDAC is a registered trademark of Analog Devices, Inc.
*Patent pending.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

family which consists of pin

®

TxDAC

D/A Converter

AD9762*

FUNCTIONAL BLOCK DIAGRAM

+5V

0.1␮F

REFLO

+1.20V REF

REFIO

FS ADJ

DVDD

DCOM

CLOCK

SLEEP

SEGMENTED

SWITCHES

DIGITAL DATA INPUTS

R

SET

CLOCK

0.1␮F

+5V

Differential current outputs are provided to support single­ended or differential applications. Matching between the two
current outputs ensures enhanced dynamic performance in a
differential output configuration. The current outputs may be
tied directly to an output resistor to provide two complemen­tary, single-ended voltage outputs or fed directly into a trans­former. The output voltage compliance range is 1.25 V.

The on-chip reference and control amplifier are configured for
maximum accuracy and flexibility. The AD9762 can be driven
by the on-chip reference or by a variety of external reference
voltages. The internal control amplifier which provides a wide
(>10:1) adjustment span allows the AD9762 full-scale current
to be adjusted over a 2 mA to 20 mA range while maintaining
excellent dynamic performance. Thus, the AD9762 may oper­ate at reduced power levels or be adjusted over a 20 dB range to
provide additional gain ranging capabilities.

The AD9762 is available in 28-lead SOIC and TSSOP pack­ages. It is specified for operation over the industrial tempera­ture range.

PRODUCT HIGHLIGHTS

1. The AD9762 is a member of the TxDAC product family which
provides an upward or downward component selection path
based on resolution (8 to 14 bits), performance and cost.

2. Manufactured on a CMOS process, the AD9762 uses a pro­prietary switching technique that enhances dynamic perfor­mance beyond what was previously attainable by higher
power/cost bipolar or BiCMOS devices.

3. On-chip, edge-triggered input CMOS latches interface readily
to +3 V and +5 V CMOS logic families. The AD9762 can
support update rates up to 125 MSPS.

4. A flexible single-supply operating range of 2.7 V to 5.5 V and
a wide full-scale current adjustment span of 2 mA to 20 mA
allow the AD9762 to operate at reduced power levels.

5. The current output(s) of the AD9762 can be easily config­ured for various single-ended or differential circuit topologies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

50pF

LATCHES

COMP1

CURRENT

SOURCE

ARRAY

SWITCHES

AVDD ACOM

AD9762

LSB

DB11–DB0

COMP2

IOUTA

IOUTB

0.1␮F

AD9762–SPECIFICATIONS

(T

to T

DC SPECIFICATIONS

MIN

, AVDD = +5 V, DVDD = +5 V, I

MAX

Parameter Min Typ Max Units

RESOLUTION 12 Bits

DC ACCURACY

1

Integral Linearity Error (INL)

= +25°C –2.5 ± 0.75 +2.5 LSB

T

A

T

MIN

to T

MAX

–4.0 ± 1.0 +4.0 LSB

Differential Nonlinearity (DNL)

= +25°C –1.5 ± 0.5 +1.5 LSB

T

A

T

MIN

to T

MAX

–2.0 ± 0.75 +2.0 LSB

ANALOG OUTPUT

Offset Error –0.025 +0.025 % of FSR
Gain Error
Gain Error
Full-Scale Output Current

(Without Internal Reference) –10 ±2 +10 % of FSR
(With Internal Reference) –10 ±1 +10 % of FSR

2

2.0 20.0 mA

Output Compliance Range –1.0 +1.25 V
Output Resistance 100 kΩ
Output Capacitance 5 pF

REFERENCE OUTPUT

Reference Voltage 1.08 1.20 1.32 V
Reference Output Current

3

REFERENCE INPUT

Input Compliance Range 0.1 1.25 V
Reference Input Resistance 1 MΩ
Small Signal Bandwidth (w/o C

COMP1

4

)

TEMPERATURE COEFFICIENTS

Offset Drift 0 ppm of FSR/°C
Gain Drift
Gain Drift

(Without Internal Reference) ±50 ppm of FSR/°C
(With Internal Reference) ±100 ppm of FSR/°C

Reference Voltage Drift ±50 ppm/°C

POWER SUPPLY

Supply Voltages

AVDD

5

2.7 5.0 5.5 V

DVDD 2.7 5.0 5.5 V
Analog Supply Current (I
Digital Supply Current (I
Supply Current Sleep Mode (I
Power Dissipation
Power Dissipation
Power Dissipation

6

(5 V, I

7

(5 V, I

7

(3 V, I

)2530mA

AVDD

6

)

DVDD

OUTFS

OUTFS

OUTFS

) 8.5 mA

AVDD

= 20 mA) 133 160 mW
= 20 mA) 190 mW

= 2 mA) 45 mW
Power Supply Rejection Ratio—AVDD –0.4 +0.4 % of FSR/V
Power Supply Rejection Ratio—DVDD –0.025 +0.025 % of FSR/V

OPERATING RANGE –40 +85 °C

NOTES

1

Measured at IOUTA, driving a virtual ground.

2

Nominal full-scale current, I

3

Use an external buffer amplifier to drive any external load.

4

Reference bandwidth is a function of external cap at COMP1 pin and signal level. Refer to Figure 41.

5

For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance.

6

Measured at f

7

Measured as unbuffered voltage output into 50 Ω R

Specifications subject to change without notice.

= 25 MSPS and f

CLOCK

, is 32 × the I

OUTFS

= 1.0 MHz.

OUT

current.

REF

at IOUTA and IOUTB, f

LOAD

CLOCK

= 20 mA, unless otherwise noted)

OUTFS

100 nA

1.4 MHz

1.5 2 mA

= 100 MSPS and f

= 40 MHz.

OUT

–2–

REV. B

AD9762

(T

to T

, AVDD = +5 V, DVDD = +5 V, I

MAX

DYNAMIC SPECIFICATIONS

MIN

50 ⍀ Doubly Terminated, unless otherwise noted)

Parameter Min Typ Max Units

DYNAMIC PERFORMANCE

Maximum Output Update Rate (f
Output Settling Time (t
Output Propagation Delay (t

) (to 0.1%)

ST

)1ns

PD

Glitch Impulse 5 pV-s
Output Rise Time (10% to 90%)
Output Fall Time (10% to 90%)
Output Noise (I
Output Noise (I

= 20 mA) 50 pA/√Hz

OUTFS

= 2 mA) 30 pA/√Hz

OUTFS

) 125 MSPS

CLOCK

1

1

1

AC LINEARITY

Spurious-Free Dynamic Range to Nyquist

f

= 25 MSPS; f

CLOCK

= +25°C 75 79 dBc

T

A

T

to T

f

CLOCK

f

CLOCK

f

CLOCK

f

CLOCK

f

CLOCK

f

CLOCK

f

CLOCK

f

CLOCK

MIN

MAX

= 50 MSPS; f
= 50 MSPS; f
= 50 MSPS; f
= 50 MSPS; f
= 100 MSPS; f
= 100 MSPS; f
= 100 MSPS; f
= 100 MSPS; f

= 1.00 MHz

OUT

73 dBc

= 1.00 MHz 79 dBc

OUT

= 2.51 MHz 74 dBc

OUT

= 5.02 MHz 70 dBc

OUT

= 20.2 MHz 57 dBc

OUT

= 2.51 MHz 73 dBc

OUT

= 5.04 MHz 67 dBc

OUT

= 20.2 MHz 57 dBc

OUT

= 40.4 MHz 53 dBc

OUT

Spurious-Free Dynamic Range within a Window

f

= 25 MSPS; f

CLOCK

= +25°C 78 86 dBc

T

A

T

to T

f

CLOCK

f

CLOCK

MIN

MAX

= 50 MSPS; f
= 100 MSPS; f

=1.00 MHz; 2 MHz Span

OUT

76 dBc

= 5.02 MHz; 2 MHz Span 84 dBc

OUT

= 5.04 MHz; 4 MHz Span 84 dBc

OUT

Total Harmonic Distortion

f

= 25 MSPS; f

CLOCK

= +25°C –78 –74 dBc

T

A

T

to T

f

CLOCK

f

CLOCK

MIN

MAX

= 50 MHz; f
= 100 MHz; f

= 1.00 MHz

OUT

= 2.00 MHz –75 dBc

OUT

= 2.00 MHz –75 dBc

OUT

Multitone Power Ratio (8 Tones at 110 kHz Spacing)

f

= 20 MSPS; f

CLOCK

NOTES

1

Measured single ended into 50 Ω load.

Specifications subject to change without notice.

= 2.00 MHz to 2.99 MHz 73 dBc

OUT

= 20 mA, Differential Transformer Coupled Output,

OUTFS

35 ns

2.5 ns

2.5 ns

–72 dBc

REV. B

–3–

AD9762

(T

to T

DIGITAL SPECIFICATIONS

MIN

, AVDD = +5 V, DVDD = +5 V, I

MAX

Parameter Min Typ Max Units

DIGITAL INPUTS

Logic “1” Voltage @ DVDD = +5 V 3.5 5 V
Logic “1” Voltage @ DVDD = +3 V 2.1 3 V
Logic “0” Voltage @ DVDD = +5 V 0 1.3 V
Logic “0” Voltage @ DVDD = +3 V 0 0.9 V
Logic “1” Current –10 +10 µA
Logic “0” Current –10 +10 µA
Input Capacitance 5 pF
Input Setup Time (t
Input Hold Time (t
Latch Pulsewidth (t

Specifications subject to change without notice.

) 2.0 ns

S

) 1.5 ns

H

) 3.5 ns

LPW

DB0–DB11

= 20 mA unless otherwise noted)

OUTFS

t

S

CLOCK

t

PD

IOUTA

OR

IOUTB

Figure 1. Timing Diagram

ABSOLUTE MAXIMUM RATINGS*

With

Parameter Respect to Min Max Units

AVDD ACOM –0.3 +6.5 V
DVDD DCOM –0.3 +6.5 V
ACOM DCOM –0.3 +0.3 V
AVDD DVDD –6.5 +6.5 V
CLOCK, SLEEP DCOM –0.3 DVDD + 0.3 V
Digital Inputs DCOM –0.3 DVDD + 0.3 V
IOUTA, IOUTB ACOM –1.0 AVDD + 0.3 V
COMP1, COMP2 ACOM –0.3 AVDD + 0.3 V
REFIO, FSADJ ACOM –0.3 AVDD + 0.3 V
REFLO ACOM –0.3 +0.3 V
Junction Temperature +150 °C
Storage Temperature –65 +150 °C
Lead Temperature

(10 sec) +300 °C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may effect device reliability.

t

H

t

LPW

t

ST

0.1%

0.1%

ORDERING GUIDE

Temperature Package Package

Model Range Description Option*

AD9762AR –40°C to +85°C 28-Lead 300 mil SOIC R-28
AD9762ARU –40°C to +85°C 28-Lead TSSOP RU-28
AD9762-EB Evaluation Board

*R = SOIC, RU = TSSOP.

THERMAL CHARACTERISTICS
Thermal Resistance

28-Lead 300 mil SOIC

= 71.4°C/W

θ

JA

θ

= 23°C/W

JC

28-Lead TSSOP

= 97.9°C/W

θ

JA

θ

= 14.0°C/W

JC

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9762 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–4–

WARNING!

ESD SENSITIVE DEVICE

REV. B

PIN CONFIGURATION

AD9762

(MSB) DB11

1

2

DB10

DB9

3

DB8

4

DB7

5

6

DB6

DB5

7

8

DB4

9

DB3

10

DB2

11

DB1

DB0

12

NC

13

NC

14

NC = NO CONNECT

AD9762

TOP VIEW

(Not to Scale)

28

27

26

25

24

23

22

21

20

19

18

17

16

15

CLOCK

DVDD

DCOM

NC

AVDD

COMP2

IOUTA

IOUTB

ACOM

COMP1

FS ADJ

REFIO

REFLO

SLEEP

PIN DESCRIPTIONS

Pin No. Name Description

1 DB11 Most Significant Data Bit (MSB).
2–11 DB10–DB1 Data Bits 1–10.
12 DB0 Least Significant Data Bit (LSB).
13, 14, 25 NC No Internal Connection.
15 SLEEP Power-down Control Input. Active High. Contains active pull-down circuit, thus may be left unterminated if

not used.
16 REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference.
17 REFIO Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to

AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM).

Requires 0.1 µF capacitor to ACOM when internal reference activated.
18 FS ADJ Full-Scale Current Output Adjust.
19 COMP1 Bandwidth/Noise Reduction Node. Add 0.1 µF to AVDD for optimum performance.
20 ACOM Analog Common.
21 IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s.
22 IOUTA DAC Current Output. Full-scale current when all data bits are 1s.
23 COMP2 Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 µF capacitor.
24 AVDD Analog Supply Voltage (+2.7 V to +5.5 V).
26 DCOM Digital Common.
27 DVDD Digital Supply Voltage (+2.7 V to +5.5 V).
28 CLOCK Clock Input. Data latched on positive edge of clock.

REV. B

–5–

AD9762

DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)

Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.

Differential Nonlinearity (or DNL)

DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input
code.

Monotonicity

A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.

Offset Error

The deviation of the output current from the ideal of zero is
called offset error. For I
inputs are all 0s. For I

, 0 mA output is expected when the

OUTA

, 0 mA output is expected when all

OUTB

inputs are set to 1s.

Gain Error

The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.

Output Compliance Range

The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown resulting in
nonlinear performance.

Temperature Drift

Temperature drift is specified as the maximum change from the
ambient (+25°C) value to the value at either T

MIN

or T

MAX

. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree C. For reference drift, the drift is
reported in ppm per degree C.

Power Supply Rejection

The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.

Settling Time

The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.

Glitch Impulse

Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.

Spurious-Free Dynamic Range

The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.

Total Harmonic Distortion

THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured output signal. It is
expressed as a percentage or in decibels (dB).

Multitone Power Ratio

The spurious-free dynamic range for an output containing mul­tiple carrier tones of equal amplitude. It is measured as the
difference between the rms amplitude of a carrier tone to the
peak spurious signal in the region of a removed tone.

DVDD

DCOM

R

SET

2k⍀

RETIMED

CLOCK

OUTPUT*

LECROY 9210

PULSE GENERATOR

0.1␮F

50⍀

+5V

+5V

0.1␮F

+1.20V REF

REFIO

FS ADJ

DVDD

DCOM

CLOCK

SLEEP

REFLO

SEGMENTED SWITCHES

FOR DB11–DB3

CLOCK

OUTPUT

50pF

COMP1

LATCHES

DIGITAL

TEKTRONIX

AWG-2021

AVDD ACOM

PMOS

CURRENT SOURCE

ARRAY

LSB

SWITCHES

DATA

AD9762

COMP2

IOUTA

IOUTB

Figure 2. Basic AC Characterization Test Set-Up

50⍀

0.1␮F

MINI-CIRCUITS

100⍀

50⍀

20pF

20pF

* AWG2021 CLOCK RETIMED
SUCH THAT DIGITAL DATA
TRANSITIONS ON FALLING EDGE
OF 50% DUTY CYCLE CLOCK.

T1-1T

TO HP3589A
SPECTRUM/
NETWORK
ANALYZER
50⍀ INPUT

–6–

REV. B

Typical AC Characterization Curves @ +5 V Supplies

(AVDD = +5 V, DVDD = +5 V, I

= 20 mA, 50 ⍀ Doubly Terminated Load, Differential Output, TA = +25ⴗC, SFDR up to Nyquist, unless otherwise noted)

OUTFS

AD9762

90

80

5MSPS

50MSPS

70

SFDR – dBc

60

50

0.1 100

Figure 3. SFDR vs. f

85

80

75

70

65

SFDR – dBc

0dBFS

60

55

50

0.00 5.00 25.0010.00 15.00 20.00

Figure 6. SFDR vs. f

25MSPS

125MSPS

110

FREQUENCY – MHz

@ 0 dBFS

OUT

–6dBFS

–12dBFS

FREQUENCY – MHz

@ 50 MSPS

OUT

100MSPS

85

80

75

70

65

SFDR – dBc

60

55

50

0.00 2.50

Figure 4. SFDR vs. f

85

80

75

70

65

SFDR – dBc

60

55

50

0.00 10.00 50.00

Figure 7. SFDR vs. f

–6dBFS

0dBFS

–12dBFS

0.50 1.00 1.50 2.00
FREQUENCY – MHz

@ 5 MSPS

OUT

–6dBFS

0dBFS

20.00 30.00 40.00

FREQUENCY – MHz

@100 MSPS

OUT

–12dBFS

85

–6dBFS

80

75

70

65

SFDR – dBc

60

55

50

0.00 2.00 12.004.00 6.00 8.00 10.00

Figure 5. SFDR vs. f

85

80

75

70

65

SFDR – dBc

60

0dBFS

55

50

0.00 10.00 60.0020.00 30.00 40.00 50.00

Figure 8. SFDR vs. f

–12dBFS

0dBFS

FREQUENCY – MHz

–6dBFS

FREQUENCY – MHz

OUT

–12dBFS

OUT

@ 25 MSPS

@ 125 MSPS

85

75

@ 25MSPS

65

SFDR – dBc

55

45

–30 –25 0

455kHz

@ 5MSPS

2.27MHz

–20 –15 –10 –5

A

9.1MHz
@ 100MSPS

– dBFS

OUT

4.55MHz
@ 50MSPS

11.37MHz

@ 125MSPS

Figure 9. Single-Tone SFDR vs. A
@ f

OUT

= f

CLOCK

/11

REV. B

OUT

85

75

@ 25MSPS

65

SFDR – dBc

55

45

–30 –25 0

1MHz

@ 5MSPS

5.0MHz

25MHz

@ 125MSPS

–20 –15 –10 –5

A

OUT

10MHz

@ 50MSPS

@ 100MSPS

– dBFS

20MHz

Figure 10. Single-Tone SFDR vs.

@ f

A

OUT

OUT

= f

CLOCK

/5

–7–

0.675/0.725MHz

80

70

60

SFDR – dBc

50

40

–30 –25 0

@ 5MSPS

3.38/3.63MHz
@ 25MSPS

6.75/7.25MHz
@ 50MSPS

13.5/14.5MHz
@ 100MSPS

16.9/18.1MHz
@ 125MSPS

–20 –15 –10 –5

A

– dBFS

OUT

Figure 11. Dual-Tone SFDR vs. A
@ f

OUT

= f

CLOCK

/7

OUT