Analog Devices AD9761 Datasheet

Dual 10-Bit TxDAC+™

ACOM

REFLO

"I"

DAC

FSADJ

IOUTA
IOUTB

WRITE INPUT

SELECT INPUT

DCOM

DVDD

CLOCK

AD9761

23

LATCH

"I"

REFIO

REFERENCE

COMP1
COMP2
COMP3

BIAS

GENERATOR

QOUTA
QOUTB

23

LATCH

"Q"

MUX

CONTROL

AVDD

DAC DATA

INPUTS

(10 BITS)

SLEEP

"Q"

DAC

a

FEATURES
Complete 10-Bit, 40 MSPS Dual Transmit DAC
Excellent Gain and Offset Matching
Differential Nonlinearity Error: 0.5 LSB
Effective Number of Bits: 9.5
Signal-to-Noise and Distortion Ratio: 59 dB
Spurious-Free Dynamic Range: 71 dB
2ⴛ Interpolation Filters
20 MSPS/Channel Data Rate
Single Supply: +2.7 V to +5.5 V
Low Power Dissipation: 200 mW (+3 V Supply @

40 MSPS)
On-Chip Reference
28-Lead SSOP

PRODUCT DESCRIPTION

The AD9761 is a complete dual channel, high speed, 10-bit
CMOS DAC. The AD9761 has been developed specifically for
use in wide bandwidth communication applications (e.g., spread
spectrum) where digital I and Q information is being processed
during transmit operations. It integrates two 10-bit, 40 MSPS

DACs, dual 2× interpolation filters, a voltage reference, and

digital input interface circuitry. The AD9761 supports a
20 MSPS per channel input data rate that is then interpolated

by 2× up to 40 MSPS before simultaneously updating each

DAC.

The interleaved I and Q input data stream is presented to the
digital interface circuitry, which consists of I and Q latches as well
as some additional control logic. The data is de-interleaved back
into its original I and Q data. An on-chip state machine ensures the
proper pairing of I and Q data. The data output from each latch is

then processed by a 2× digital interpolation filter that eases the

reconstruction filter requirements. The interpolated output of each
filter serves as the input of their respective 10-bit DAC.

The DACs utilize a segmented current source architecture com­bined with a proprietary switching technique to reduce glitch
energy and to maximize dynamic accuracy. Each DAC provides
differential current output thus supporting single-ended or
differential applications. Both DACs are simultaneously up­dated and provide a nominal full-scale current of 10 mA. Also,
the full-scale currents between each DAC are matched to within

0.07 dB (i.e., 0.75%), thus eliminating the need for additional
gain calibration circuitry.

The AD9761 is manufactured on an advanced low cost CMOS
process. It operates from a single supply of 2.7 V to 5.5 V and
consumes 200 mW of power. To make the AD9761 complete it
also offers an internal 1.20 V temperature-compensated bandgap
reference.

TxDAC+ is a trademark of Analog Devices, Inc.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

with 2ⴛ Interpolation Filters

AD9761

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

1. Dual 10-Bit, 40 MSPS DACs: A pair of high performance
40 MSPS DACs optimized for low distortion performance
provide for flexible transmission of I and Q information.

2. 2× Digital Interpolation Filters: Dual matching FIR interpo-

lation filters with 62.5 dB stop band rejection precede each
DAC input thus reducing the DACs’ reconstruction filter
requirements.

3. Low Power: Complete CMOS Dual DAC function operates
on a low 200 mW on a single supply from 2.7 V to 5.5 V.
The DAC full-scale current can be reduced for lower power
operation, and a sleep mode is provided for power reduction
during idle periods.

4. On-Chip Voltage Reference: The AD9761 includes a 1.20 V
temperature-compensated bandgap voltage reference.

5. Single 10-Bit Digital Input Bus: The AD9761 features a
flexible digital interface allowing each DAC to be addressed
in a variety of ways including different update rates.

6. Small Package: The AD9761 offers the complete integrated
function in a compact 28-lead SSOP package.

7. Product Family: The AD9761 Dual Transmit DAC has a
pair of Dual Receive ADC companion products, the AD9281
(8 bits) and AD9201 (10 bits).

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

AD9761–SPECIFICATIONS

(T

to T

DC SPECIFICATIONS

MIN

, AVDD = +5 V, DVDD = +5 V, I

MAX

Parameter Min Typ Max Units

RESOLUTION 10 Bits

DC ACCURACY

1

Integral Linearity Error (INL)

= +25°C –1.75 ±0.5 1.75 LSB

T

A

T

MIN

to T

MAX

–2.75 ±0.7 2.75 LSB

Differential Nonlinearity (DNL)

= +25°C–1±0.4 1.25 LSB

T

A

T

MIN

to T

MAX

–1 ±0.5 1.75 LSB

Monotonicity (10 Bit) GUARANTEED OVER RATED SPECIFICATION TEMPERATURE RANGE

ANALOG OUTPUT

Offset Error –0.05 ±0.025 0.05 % of FSR
Offset Matching between DACs –0.10 ±0.05 0.10 % of FSR
Gain Error (without Internal Reference) –5.5 ±1.0 5.5 % of FSR
Gain Error (with Internal Reference) –5.5 ±1.0 5.5 % of FSR
Gain Matching between DACs –1.0 ±0.25 1.0 % of FSR

Full-Scale Output Current

2

Output Compliance Range –1.0 1.25 V

Output Resistance 100 kΩ

Output Capacitance 5 pF

REFERENCE OUTPUT

Reference Voltage 1.14 1.20 1.26 V
Reference Output Current

3

REFERENCE INPUT

Input Compliance Range 0.1 1.25 V

Reference Input Resistance 1 MΩ

TEMPERATURE COEFFICIENTS

Unipolar Offset Drift 0 ppm/°C
Gain Drift (without Internal Reference) ±50 ppm/°C
Gain Drift (with Internal Reference) ±140 ppm/°C
Gain Matching Drift (Between DACs) ±25 ppm/°C
Reference Voltage Drift ±50 ppm/°C

POWER SUPPLY

AVDD

Voltage Range 2.7 5.0 5.5 V
Analog Supply Current (I

)2635mA

AVDD

DVDD

Voltage Range 2.7 5.0 5.5 V
Digital Supply Current at 5 V (I
Digital Supply Current at 3 V (I

Nominal Power Dissipation

5

DVDD

DVDD

4

)

4

)

AVDD and DVDD at 3 V 200 250 mW
AVDD and DVDD at 5 V 500 650 mW
Power Supply Rejection Ratio (PSRR)–AVDD –0.25 0.25 % of FSR/V
Power Supply Rejection Ratio (PSRR)–DVDD –0.02 0.02 % of FSR/V

OPERATING RANGE –40 +85 °C

NOTES

1

Measured at IOUTA and QOUTA, driving a virtual ground.

2

Nominal full-scale current, I

3

Use an external amplifier to drive any external load.

4

Measured at f

5

Measured as unbuffered voltage output into 50 Ω R

Specifications subject to change without notice.

= 40 MSPS and f

CLOCK

OUTFS

, is 16× the I

= 1 MHz.

OUT

current.

REF

at IOUTA, IOUTB, QOUTA, and QOUTB, f

LOAD

= 10 mA, unless otherwise noted)

OUTFS

10 mA

100 nA

70 85 mA
35 mA

= 40 MSPS and f

CLOCK

= 8 MHz.

OUT

–2– REV. A

AD9761

(T

to T

, AVDD = +5 V, DVDD = +5 V, I

MAX

DYNAMIC SPECIFICATIONS

MIN

50 ⍀ Doubly Terminated, unless otherwise noted)

Parameter Min Typ Max Units

DYNAMIC PERFORMANCE

Maximum Output Update Rate 40 MSPS
Output Settling Time (t
Output Propagation Delay (t

to 0.025%) 35 ns

ST

) 55 Input Clock Cycles

PD

Glitch Impulse 5 pV-s
Output Rise Time (10% to 90%) 2.5 ns
Output Fall Time (10% to 90%) 2.5 ns

AC LINEARITY TO NYQUIST

Signal-to-Noise and Distortion (SINAD)

f

= 1 MHz; CLOCK = 40 MSPS 56 59 dB

OUT

Effective Number of Bits (ENOBs) 9.0 9.5 Bits
Total Harmonic Distortion (THD)

= 1 MHz; CLOCK = 40 MSPS –68 –58 dB

f

OUT

Spurious-Free Dynamic Range (SFDR)

= 1 MHz; CLOCK = 40 MSPS; 10 MHz Span 59 68 dB

f

OUT

Channel Isolation

f

= 8 MHz; CLOCK = 40 MSPS; 10 MHz Span 90 dBC

OUT

(T

to T

DIGITAL SPECIFICATIONS

MIN

, AVDD = +5 V, DVDD = +5 V, I

MAX

Parameter Min Typ Max Units

DIGITAL INPUTS

Logic “1” Voltage @ DVDD = +5 V 3.5 5 V
Logic “1” Voltage @ DVDD = +3 V 2.4 3 V
Logic “0” Voltage @ DVDD = +5 V 0 1.3 V
Logic “0” Voltage @ DVDD = +3 V 0 0.9 V

Logic “1” Current –10 +10 µA
Logic “0” Current –10 +10 µA

Input Capacitance 5 pF
Input Setup Time (tS)3ns
Input Hold Time (t

)2ns

H

CLOCK High 5 ns
CLOCK Low 5 ns
Invalid CLOCK/WRITE Window (t

NOTES

1

t

is an invalid window of 4 ns duration beginning 1 ns AFTER the rising edge of WRITE in which the rising edge of CLOCK MUST NOT occur.

CINV

Specifications subject to change without notice.

CINV

1

)

15ns

= 10 mA, Differential Transformer Coupled Output,

OUTFS

= 10 mA unless otherwise noted)

OUTFS

DB9–DB0

DAC

INPUTS

SELECT

WRITE

CLOCK

t

H

t

S

"I" DATA "Q" DATA

NOTES: WRITE AND CLOCK CAN BE TIED
TOGETHER. FOR TYPICAL EXAMPLES, REFER
TO DIGITAL INPUTS AND INTERLEAVED INTERFACE
CONSIDERATION SECTION.

t

CINV

Figure 1. Timing Diagram

–3–REV. A

AD9761

(T

to T

, AVDD = +2.7 V to 5.5 V, DVDD = +2.7 V to 5.5 V, I

MAX

DIGITAL FILTER SPECIFICATIONS

MIN

otherwise noted)

Parameter Min Typ Max Units

MAXIMUM INPUT CLOCK RATE (f

DIGITAL FILTER CHARACTERISTICS

Passband Width

1

: 0.005 dB 0.2010 f

) 40 MSPS

CLOCK

Passband Width: 0.01 dB 0.2025 f
Passband Width: 0.1 dB 0.2105 f
Passband Width: –3 dB 0.239 f
Linear Phase (FIR Implementation)
Stopband Rejection: 0.3 f
Group Delay

2

Impulse Response Duration

CLOCK

3

to 0.7 f

CLOCK

–62.5 dB
32 Input Clock Cycles

–40 dB 28 Input Clock Cycles
–60 dB 40 Input Clock Cycles

NOTES

1

Excludes SINX/X characteristic of DAC.

2

Defined as the number of data clock cycles between impulse input and peak of output response.

3

55 input clock periods from input to I DAC, 56 to Q DAC. Propagation delay is delay from data input to DAC update.

= 10 mA unless

OUTFS

OUT/fCLOCK

OUT/fCLOCK

OUT/fCLOCK

OUT/fCLOCK

0

–20

–40

–60

OUTPUT – dBFS

–80

–100

–120

0 0.50.1 0.2 0.3 0.4

FREQUENCY RESPONSE – DC to f

CLOCK

/2

Figure 2a. FIR Filter Frequency Response

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

NORMALIZED OUTPUT

0
–0.1
–0.2
–0.3

0405101520253035

TIME – Samples

Figure 2b. FIR Filter Impulse Response

Table I. Integer Filter Coefficients for 43-Tap Halfband
FIR Filter

Lower Coefficient Upper Coefficient Integer Value

H(1) H(43) 1
H(2) H(42) 0
H(3) H(41) –3
H(4) H(40) 0
H(5) H(39) 8
H(6) H(38) 0
H(7) H(37) –16
H(8) H(36) 0
H(9) H(35) 29
H(10) H(34) 0
H(11) H(33) –50
H(12) H(32) 0
H(13) H(31) 81
H(14) H(30) 0
H(15) H(29) –131
H(16) H(28) 0
H(17) H(27) 216
H(18) H(26) 0
H(19) H(25) –400
H(20) H(24) 0
H(21) H(23) 1264
H(22) 1998

–4– REV. A

AD9761

WARNING!

ESD SENSITIVE DEVICE

ORDERING GUIDE

Package Package

Model Description Option

AD9761ARS 28-Lead Shrink Small Outline (SSOP) RS-28
AD9761-EB Evaluation Board

ABSOLUTE MAXIMUM RATINGS*

With

Parameter Respect to Min Max Units

AVDD ACOM –0.3 +6.5 V
DVDD DCOM –0.3 +6.5 V
ACOM DCOM –0.3 +0.3 V
AVDD DVDD –6.5 +6.5 V
CLOCK, WRITE DCOM –0.3 DVDD+0.3 V
SELECT, SLEEP DCOM –0.3 DVDD+0.3 V
Digital Inputs DCOM –0.3 DVDD+0.3 V
IOUTA, IOUTB ACOM –1.0 AVDD+0.3 V
QOUTA, QOUTB ACOM –1.0 AVDD+0.3 V
COMP1, COMP2 ACOM –0.3 AVDD+0.3 V
COMP3 ACOM –0.3 AVDD+0.3 V
REFIO, FSADJ ACOM –0.3 AVDD+0.3 V
REFLO ACOM –0.3 +0.3 V

Junction Temperature +150 °C
Storage Temperature –65 +150 °C
Lead Temperature (10 sec) +300 °C

*This is a stress rating only; functional operation of the device at these or any other conditions above

those listed in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS
Thermal Resistance

28-Lead SSOP

= 109°C/W

θ

JA

+2.7V TO

COMP3

LATCH

"I"

LATCH

"Q"

5.5V

AVDD AVSS

2x

AD9761

2x

SLEEPCLOCK

COMP1

"I"

DAC

"Q"

DAC

0.1mF 0.1mF0.1mF

COMP2

IOUTA
IOUTB

REFLO

REFIO

FSADJ

QOUTA
QOUTB

0.1mF
R

SET

2kV

50V

50V

100V

20pF

100V

20pF

TEKTRONIX

AWG-2021

CLOCK

OUT

DIGITAL

DATA

MARKER 1

RETIMED

CLOCK

OUTPUT*

LE CROY 9210

PULSE GENERATOR

+2.7V TO

5.5V

DVDD DCOM

DB9–DB0

SELECT
WRITE

*AWG2021 CLOCK RETIMED SUCH THAT DIGITAL DATA

TRANSITIONS ON FALLING EDGE OF 50% DUTY CYCLE CLOCK.

MUX

CONTROL

Figure 3. Basic AC Characterization Test Setup

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9761 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–5–REV. A

MINI-CIRCUITS

T1-1T

20pF

50V

MINI-CIRCUITS

T1-1T

20pF

50V

TO HP3589A

SPECTRUM/NETWORK

ANALYZER
50V INPUT

TO HP3589A

SPECTRUM/NETWORK

ANALYZER
50V INPUT

AD9761

PIN FUNCTION DESCRIPTIONS

Pin No. Name Description

1 DB9 Most Significant Data Bit (MSB).
2–9 DB8–DB1 Data Bits 1-8.
10 DB0 Least Significant Data Bit (LSB).
11 CLOCK Clock Input. Both DACs’ outputs updated on positive edge of clock and digital filters read respective

input registers.
12 WRITE Write input. DAC input registers latched on positive edge of write.
13 SELECT Select Input. Select high routes input data to I DAC, select low routes data to Q DAC.
14 DVDD Digital Supply Voltage (+2.7 V to +5.5 V).
15 DCOM Digital Common.

16 COMP3 Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 µF capacitor.

17 QOUTA Q DAC Current Output. Full-scale current when all data bits are 1s.
18 QOUTB Q DAC Complementary Current Output. Full-scale current when all data bits are 0s.
19 REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal

reference.
20 REFIO Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.2 V

reference output when internal reference activated. Requires 0.1 µF capacitor to ACOM when inter-

nal reference activated.
21 FSADJ Full-Scale Current Output Adjust. Resistance to ACOM sets full-scale output current.

22 COMP2 Bandwidth/Noise Reduction Node. Add 0.1 µF to AVDD for optimum performance.

23 AVDD Analog Supply Voltage (+2.7 V to +5.5 V).
24 ACOM Analog Common.
25 IOUTB I DAC Complementary Current Output. Full-scale current when all data bits are 0s.
26 IOUTA I DAC Current Output. Full-scale current when all data bits are 1s.

27 COMP1 Internal Bias Node for Switch Driver Circuitry. Decouple to AGND with 0.1 µF capacitor.

28 RESET/SLEEP Power-Down control input if asserted for four clock cycles or longer. Reset control input if asserted

for less than four clock cycles. Active high. Connect to DCOM if not used. Refer to RESET/SLEEP

section.

PIN CONFIGURATION

28

RESET/SLEEP
COMP1

27
26

IOUTA

25

IOUTB

24

ACOM
AVDD

23
22

COMP2

21

FSADJ

20

REFIO
19
18

QOUTB

QOUTA

17
16

COMP3
15

DCOM

DB8
DB7
DB6
DB5

DB4
DB3
DB2
DB1

CLOCK

WRITE

SELECT

DVDD

1
2
3
4
5

AD9761

6

TOP VIEW

(Not to Scale)

7
8

9
10
11
12
13
14

(MSB) DB9

(LSB) DB0 REFLO

–6– REV. A

AD9761

DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)

Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.

Differential Nonlinearity (or DNL)

DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input
code.

Monotonicity

A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.

Offset Error

The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when
the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.

Gain Error

The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.

Output Compliance Range

The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.

Temperature Drift

Temperature drift is specified as the maximum change from the

ambient (+25°C) value to the value at either T

MIN

or T

MAX

. For

offset and gain drift, the drift is reported in ppm of full-scale

range (FSR) per °C. For reference drift, the drift is reported in
ppm per °C.

Power Supply Rejection

The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.

Settling Time

The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.

Glitch Impulse

Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified the net area of the glitch in pV-s.

Channel Isolation

Channel Isolation is a measure of the level of crosstalk between
channels. It is measured by producing a full-scale 8 MHz signal
output for one channel and measuring the leakage into the other
channel.

Spurious-Free Dynamic Range

The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.

Total Harmonic Distortion

THD is the ratio of the sum of the rms value of the first six
harmonic components to the rms value of the measured output
signal. It is expressed as a percentage or in decibels (dB).

Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio

S/N+D is the ratio of the rms value of the measured output
signal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/N+D is expressed in decibels.

Effective Number of Bits (ENOB)

For a sine wave, SINAD can be expressed in terms of the num­ber of bits. Using the following formula,

N = (SINAD – 1.76)/6.02

it is possible to get a measure of performance expressed as N,
the effective number of bits.

Thus, effective number of bits for a device for sine wave inputs
at a given input frequency can be calculated directly from its
measured SINAD.

Passband

Frequency band in which any input applied therein passes
unattenuated to the DAC output.

Stopband Rejection

The amount of attenuation of a frequency outside the passband
applied to the DAC, relative to a full-scale signal applied at the
DAC input within the passband.

Group Delay

Number of input clocks between an impulse applied at the
device input and peak DAC output current.

Impulse Response

Response of the device to an impulse applied to the input.

–7–REV. A