Analog Devices AD9760ARU, AD9760AR50, AD9760AR, AD9760-EB Datasheet

10-Bit, 125 MSPS

a

FEATURES
Member of Pin-Compatible TxDAC
125 MSPS Update Rate
10-Bit Resolution
Excellent Spurious Free Dynamic Range Performance
SFDR to Nyquist @ 40 MHz Output: 52 dBc
Differential Current Outputs: 2 mA to 20 mA
Power Dissipation: 175 mW @ 5 V to 45 mW @ 3 V
Power-Down Mode: 25 mW @ 5 V
On-Chip 1.20 V Reference
Single +5 V or +3 V Supply Operation
Packages: 28-Lead SOIC and TSSOP
Edge-Triggered Latches

APPLICATIONS
Communication Transmit Channel:

Basestations
Set Top Boxes

Digital Radio Link
Direct Digital Synthesis (DDS)
Instrumentation

PRODUCT DESCRIPTION

The AD9760 and AD9760-50 are the 10-bit resolution members
of the TxDAC series of high performance, low power CMOS
digital-to-analog converters (DACs). The AD9760-50 is a lower
performance option that is guaranteed and specified for 50 MSPS
operation. The TxDAC

family that consists of pin compatible 8-,
10-, 12- and 14-bit DACs is specifically optimized for the trans­mit signal path of communication systems. All of the devices
share the same interface options, small outline package and
pinout, thus providing an upward or downward component
selection path based on performance, resolution and cost. Both
the AD9760 and AD9760-50 offer exceptional ac and dc
performance while supporting update rates up to 125 MSPS
and 60 MSPS respectively.

The AD9760’s flexible single-supply operating range of 2.7 V to

5.5 V and low power dissipation are well suited for portable and
low power applications. Its power dissipation can be further
reduced to a mere 45 mW without a significant degradation in
performance by lowering the full-scale current output. Also, a
power-down mode reduces the standby power dissipation to
approximately 25 mW.

The AD9760 is manufactured on an advanced CMOS process. A
segmented current source architecture is combined with a propri­etary switching technique to reduce spurious components and
enhance dynamic performance. Edge-triggered input latches and a

1.2 V temperature compensated bandgap reference have been inte­grated to provide a complete monolithic DAC solution. Flexible
supply options support +3 V and +5 V CMOS logic families.

TxDAC is a registered trademark of Analog Devices, Inc.
*Patents Pending.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

Product Family

®

TxDAC

D/A Converter

AD9760*

FUNCTIONAL BLOCK DIAGRAM

+5V

0.1␮F

REFLO

+1.20V REF

REFIO

FS ADJ

DVDD

DCOM

CLOCK

SLEEP

SEGMENTED
SWITCHES

DIGITAL DATA INPUTS (DB9–DB0)

R

SET

CLOCK

0.1␮F

+5V

The AD9760 is a current-output DAC with a nominal full-scale
output current of 20 mA and > 100 kΩ output impedance.
Differential current outputs are provided to support single­ended or differential applications. Matching between the two
current outputs ensures enhanced dynamic performance in a
differential output configuration. The current outputs may be
tied directly to an output resistor to provide two complemen­tary, single-ended voltage outputs or fed directly into a trans­former. The output voltage compliance range is 1.25 V.

The on-chip reference and control amplifier are configured for
maximum accuracy and flexibility. The AD9760 can be driven
by the on-chip reference or by a variety of external reference
voltages. The internal control amplifier that provides a wide
(>10:1) adjustment span allows the AD9760 full-scale current
to be adjusted over a 2 mA to 20 mA range while maintaining
excellent dynamic performance. Thus, the AD9760 may oper­ate at reduced power levels or be adjusted over a 20 dB range to
provide additional gain ranging capabilities.

The AD9760 is available in a 28-lead SOIC and TSSOP packages.
It is specified for operation over the industrial temperature range.

PRODUCT HIGHLIGHTS

1. The AD9760 is a member of the TxDAC product family that
provides an upward or downward component selection path
based on resolution (8 to 14 bits), performance and cost.

2. Manufactured on a CMOS process, the AD9760 uses a pro­prietary switching technique that enhances dynamic perfor­mance beyond what was previously attainable by higher
power/cost bipolar or BiCMOS devices.

3. On-chip, edge-triggered input CMOS latches interface readily
to +3 V and +5 V CMOS logic families. The AD9760 can
support update rates up to 125 MSPS.

4. A flexible single-supply operating range of 2.7 V to 5.5 V and
a wide full-scale current adjustment span of 2 mA to 20 mA
allow the AD9760 to operate at reduced power levels.

5. The current output(s) of the AD9760 can be easily config­ured for various single-ended or differential circuit topologies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

50pF

LATCHES

COMP1

CURRENT

SOURCE

ARRAY

SWITCHES

AVDD ACOM

AD9760

LSB

COMP2

I

OUTA

I

OUTB

0.1␮F

AD9760/AD9760-50–SPECIFICATIONS

(T

to T

DC SPECIFICATIONS

MIN

, AVDD = +5 V, DVDD = +5 V, I

MAX

Parameter Min Typ Max Units

RESOLUTION 10 Bits

DC ACCURACY

1

Integral Linearity Error (INL) –1.0 ± 0.5 +1.0 LSB
Differential Nonlinearity (DNL) –0.5 ± 0.25 +0.5 LSB

MONOTONICITY Guaranteed Over Specified Temperature Range

ANALOG OUTPUT

Offset Error –0.025 +0.025 % of FSR
Gain Error
Gain Error
Full-Scale Output Current

(Without Internal Reference) –10 ±2 +10 % of FSR
(With Internal Reference) –10 ±1 +10 % of FSR

2

2.0 20.0 mA

Output Compliance Range –1.0 1.25 V
Output Resistance 100 kΩ
Output Capacitance 5 pF

REFERENCE OUTPUT

Reference Voltage 1.08 1.20 1.32 V
Reference Output Current

3

REFERENCE INPUT

Input Compliance Range 0.1 1.25 V
Reference Input Resistance 1 MΩ
Small Signal Bandwidth (w/o C

COMP1

4

)

TEMPERATURE COEFFICIENTS

Offset Drift 0 ppm of FSR/°C
Gain Drift
Gain Drift

(Without Internal Reference) ±50 ppm of FSR/°C
(With Internal Reference) ±100 ppm of FSR/°C

Reference Voltage Drift ±50 ppm/°C

POWER SUPPLY

Supply Voltages

AVDD

5

2.7 5.0 5.5 V

DVDD 2.7 5.0 5.5 V
Analog Supply Current (I
Digital Supply Current (I
Supply Current Sleep Mode (I
Power Dissipation
Power Dissipation
Power Dissipation

6

(5 V, I

7

(5 V, I

7

(3 V, I

)2530mA

AVDD

6

)

DVDD

OUTFS

OUTFS

OUTFS

) 8.5 mA

AVDD

= 20 mA) 140 175 mW
= 20 mA) 190 mW

= 2 mA) 45 mW
Power Supply Rejection Ratio—AVDD –0.04 +0.04 % of FSR/V
Power Supply Rejection Ratio—DVDD –0.025 +0.025 % of FSR/V

OPERATING RANGE –40 +85 °C

NOTES

1

Measured at I

2

Nominal full-scale current, I

3

Use an external buffer amplifier to drive any external load.

4

Reference bandwidth is a function of external cap at COMP1 pin and signal level. Refer to Figure 41.

5

For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance.

6

Measured at f

7

Measured as unbuffered voltage output into 50 Ω R

Specifications subject to change without notice.

, driving a virtual ground.

OUTA

= 50 MSPS and f

CLOCK

, is 32 × the I

OUTFS

= 1.0 MHz.

OUT

current.

REF

LOAD

at I

OUTA

and I

OUTB

, f

= 100 MSPS and f

CLOCK

= 20 mA, unless otherwise noted)

OUTFS

100 nA

1.4 MHz

35mA

= 40 MHz.

OUT

–2–

REV. B

AD9760

(T

to T

, AVDD = +5 V, DVDD = +5 V, I

MAX

DYNAMIC SPECIFICATIONS

MIN

50 ⍀ Doubly Terminated, unless otherwise noted)

Model AD9760 AD9760-50
Parameter Min Typ Max Min Typ Max Units

DYNAMIC PERFORMANCE

Maximum Output Update Rate (f
Output Settling Time (t
Output Propagation Delay (t

) (to 0.1%)

ST

)11ns

PD

Glitch Impulse 5 5 pV-s
Output Rise Time (10% to 90%)
Output Fall Time (10% to 90%)
Output Noise (I
Output Noise (I

= 20 mA) 50 50 pA/√Hz

OUTFS

= 2 mA) 30 30 pA/√Hz

OUTFS

) 125 50 60 MSPS

CLOCK

1

1

1

35 35 ns

2.5 2.5 ns

2.5 2.5 ns

AC LINEARITY

Spurious-Free Dynamic Range to Nyquist

= 50 MSPS; f

f

CLOCK

T

= +25°C 7073 6873 dBc

A

T

to T

f

CLOCK

f

CLOCK

f

CLOCK

f

CLOCK

f

CLOCK

f

CLOCK

f

CLOCK

MIN

MAX

= 50 MSPS; f
= 50 MSPS; f
= 50 MSPS; f
= 100 MSPS; f
= 100 MSPS; f
= 100 MSPS; f
= 100 MSPS; f

= 1.00 MHz

OUT

68 66 dBc

= 2.51 MHz 73 73 dBc

OUT

= 5.02 MHz 68 68 dBc

OUT

= 20.2 MHz 55 55 dBc

OUT

= 2.51 MHz 74 N/A dBc

OUT

= 5.04 MHz 68 N/A dBc

OUT

= 20.2 MHz 60 N/A dBc

OUT

= 40.4 MHz 52 N/A dBc

OUT

Spurious-Free Dynamic Range within a Window

f

= 50 MSPS; f

CLOCK

= +25°C 7478 7278 dBc

T

A

T

to T

f

CLOCK

f

CLOCK

MIN

MAX

= 50 MSPS; f
= 100 MSPS; f

= 1.00 MHz

OUT

72 70 dBc

= 5.02 MHz; 2 MHz Span 76 76 dBc

OUT

= 5.04 MHz; 4 MHz Span 76 N/A dBc

OUT

Total Harmonic Distortion

f

= 50 MSPS; f

CLOCK

= +25°C –76 –73 –76 –70 dBc

T

A

T

to T

MIN

f

CLOCK

f

CLOCK

NOTES

1

Measured single ended into 50 Ω load.

Specifications subject to change without notice.

MAX

= 50 MHz; f
= 100 MHz; f

= 1.00 MHz

OUT

= 2.00 MHz –71 –71 dBc

OUT

= 2.00 MHz –71 N/A dBc

OUT

= 20 mA, Differential Transformer Coupled Output,

OUTFS

–71 –68 dBc

REV. B

–3–

AD9760

WARNING!

ESD SENSITIVE DEVICE

(T

to T

DIGITAL SPECIFICATIONS

MIN

, AVDD = +5 V, DVDD = +5 V, I

MAX

Parameter Min Typ Max Units

DIGITAL INPUTS

Logic “1” Voltage @ DVDD = +5 V 3.5 5 V
Logic “1” Voltage @ DVDD = +3 V 2.1 3 V
Logic “0” Voltage @ DVDD = +5 V 0 1.3 V
Logic “0” Voltage @ DVDD = +3 V 0 0.9 V
Logic “1” Current –10 +10 µA
Logic “0” Current –10 +10 µA
Input Capacitance 5 pF
Input Setup Time (t
Input Hold Time (t
Latch Pulsewidth (t

Specification subject to change without notice.

) 2.0 ns

S

) 1.5 ns

H

) 3.5 ns

LPW

DB0–DB9

= 20 mA unless otherwise noted)

OUTFS

t

S

CLOCK

t

PD

I

OR

OUTA

I

OUTB

Figure 1. Timing Diagram

ABSOLUTE MAXIMUM RATINGS*

With

Parameter Respect to Min Max Units

AVDD ACOM –0.3 +6.5 V
DVDD DCOM –0.3 +6.5 V
ACOM DCOM –0.3 +0.3 V
AVDD DVDD –6.5 +6.5 V
CLOCK, SLEEP DCOM –0.3 DVDD + 0.3 V
Digital Inputs DCOM –0.3 DVDD + 0.3 V
I

OUTA

, I

OUTB

ACOM –1.0 AVDD + 0.3 V
COMP1, COMP2 ACOM –0.3 AVDD + 0.3 V
REFIO, FSADJ ACOM –0.3 AVDD + 0.3 V
REFLO ACOM –0.3 +0.3 V
Junction Temperature +150 °C
Storage Temperature –65 +150 °C
Lead Temperature

(10 sec) +300 °C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may effect device reliability.

t

H

t

LPW

t

ST

0.1%

0.1%

ORDERING GUIDE

Temperature Package Package

Model Range Descriptions Options

AD9760AR –40°C to +85°C 28-Lead 300 mil R-28

SOIC

AD9760ARU –40°C to +85°C 28-Lead 170 mil RU-28

TSSOP

AD9760AR50 –40°C to +85°C 28-Lead 300 mil R-28

SOIC

AD9760ARU50 –40°C to +85°C 28-Lead 170 mil RU-28

TSSOP

AD9760-EB Evaluation Board

THERMAL CHARACTERISTICS
Thermal Resistance

28-Lead 300 mil (7.5 mm) SOIC

= 71.4°C/W

θ

JA

θ

= 23°C/W

JC

28-Lead 170 mil (4.4 mm) TSSOP

= 97.9°C/W

θ

JA

θ

= 14.0°C/W

JC

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9760 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–4–

REV. B

AD9760

14

13

12

11

17

16

15

20

19

18

10

9

8

1

2

3

4

7

6

5

28

27

26

25

24

23

22

21

NC = NO CONNECT

(MSB) DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

NC

NC

NC

NC

CLOCK

DVDD

DCOM

NC

AVDD

COMP2

I

OUTA

I

OUTB

ACOM

COMP1

FS ADJ

REFIO

REFLO

SLEEP

TOP VIEW

(Not to Scale)

AD9760

PIN CONFIGURATION

PIN FUNCTION DESCRIPTIONS

Pin No. Name Description

1 DB9 Most Significant Data Bit (MSB).
2–9 DB8–DB1 Data Bits 1–8.
10 DB0 Least Significant Data Bit (LSB).
11–14, 25 NC No Internal Connection.
15 SLEEP Power-Down Control Input. Active High. Contains active pull-down circuit, thus may be left unterminated if

not used.
16 REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference.
17 REFIO Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to

AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM).

Requires 0.1 µF capacitor to ACOM when internal reference activated.
18 FS ADJ Full-Scale Current Output Adjust.
19 COMP1 Bandwidth/Noise Reduction Node. Add 0.1 µF to AVDD for optimum performance.
20 ACOM Analog Common.
21 I
22 I

OUTB

OUTA

23 COMP2 Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 µF capacitor.
24 AVDD Analog Supply Voltage (+2.7 V to +5.5 V).
26 DCOM Digital Common.
27 DVDD Digital Supply Voltage (+2.7 V to +5.5 V).
28 CLOCK Clock Input. Data latched on positive edge of clock.

Complementary DAC Current Output. Full-scale current when all data bits are 0s.

DAC Current Output. Full-scale current when all data bits are 1s.

REV. B

–5–

AD9760

DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)

Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.

Differential Nonlinearity (or DNL)

DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input
code.

Monotonicity

A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.

Offset Error

The deviation of the output current from the ideal of zero is
called offset error. For I
inputs are all 0s. For I

, 0 mA output is expected when the

OUTA

, 0 mA output is expected when all

OUTB

inputs are set to 1s.

Gain Error

The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.

Output Compliance Range

The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown resulting in
nonlinear performance.

Temperature Drift

Temperature drift is specified as the maximum change from the
ambient (+25°C) value to the value at either T

MIN

or T

MAX

. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree C. For reference drift, the drift is
reported in ppm per degree C.

Power Supply Rejection

The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.

Settling Time

The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.

Glitch Impulse

Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.

Spurious-Free Dynamic Range

The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.

Total Harmonic Distortion

THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured output signal. It is
expressed as a percentage or in decibels (dB).

DVDD
DCOM

R

SET

2k⍀

RETIMED

CLOCK

OUTPUT*

LECROY 9210

PULSE GENERATOR

0.1␮F

+5V

50⍀

+5V

0.1␮F

+1.20V REF

REFIO

FS ADJ

DVDD

DCOM

CLOCK

SLEEP

REFLO

SEGMENTED SWITCHES

FOR DB11–DB3

CLOCK

OUTPUT

50pF

TEKTRONIX

COMP1

PMOS

CURRENT SOURCE

ARRAY

LATCHES

DIGITAL

DATA

AWG-2021

AVDD ACOM

AD9760

LSB

SWITCHES

Figure 2. Basic AC Characterization Test Setup

COMP2

I

OUTA

I

OUTB

50⍀

0.1␮F

MINI-CIRCUITS

100⍀

50⍀

20pF

20pF

* AWG2021 CLOCK RETIMED
SUCH THAT DIGITAL DATA
TRANSITIONS ON FALLING EDGE
OF 50% DUTY CYCLE CLOCK.

T1-1T

TO HP3589A
SPECTRUM/
NETWORK
ANALYZER
50⍀ INPUT

–6–

REV. B

Typical AC Characterization Curves @ +5 V Supplies

(AVDD = +5 V, DVDD = +5 V, I

= 20 mA, 50 ⍀ Doubly Terminated Load, Differential Output, TA = +25ⴗC, SFDR up to Nyquist, unless otherwise noted)

OUTFS

AD9760

90

5MSPS

80

70

SFDR – dBc

60

50

0.1 100

Figure 3. SFDR vs. f

85

80

75

70

65

SFDR – dBc

60

55

50

–6dBFS

0dBFS

0.00 5.00 25.0010.00 15.00 20.00

Figure 6. SFDR vs. f

25MSPS

50MSPS

125MSPS

110

FREQUENCY – MHz

OUT

–12dBFS

FREQUENCY – MHz

OUT

100MSPS

@ 0 dBFS

@ 50 MSPS

85

80

75

70

65

SFDR – dBc

60

55

50

0.00 2.50

Figure 4. SFDR vs. f

85

80

75

70

65

SFDR – dBc

60

55

50

0.00 10.00 50.00

Figure 7. SFDR vs. f

0dBFS

–6dBFS

–12dBFS

0.50 1.00 1.50 2.00
FREQUENCY – MHz

OUT

–6dBFS

0dBFS

20.00 30.00 40.00

FREQUENCY – MHz

@100 MSPS

OUT

@ 5 MSPS

–12dBFS

85

80

75

70

65

SFDR – dBc

60

55

50

0.00 2.00 12.004.00 6.00 8.00 10.00

Figure 5. SFDR vs. f

85

80

75

70

65

SFDR – dBc

60

–12dBFS

55

50

0.00 10.00 60.0020.00 30.00 40.00 50.00

Figure 8. SFDR vs. f

–6dBFS

0dBFS

FREQUENCY – MHz

OUT

–6dBFS

0dBFS

FREQUENCY – MHz

OUT

–12dBFS

@ 25 MSPS

@ 125 MSPS

85

75

2.27MHz

@ 25MSPS

65

SFDR – dBc

55

45

–30 –25 0

4.55MHz
@ 50MSPS

–20 –15 –10 –5

A

9.1MHz
@ 100MSPS

– dBFS

OUT

455kHz

@ 5MSPS

@ 125MSPS

11.37MHz

Figure 9. Single-Tone SFDR vs. A
@ f

OUT

= f

CLOCK

/11

REV. B

OUT

85

1MHz

A

OUT

@ 5MSPS

10MHz

@ 50MSPS

@ 100MSPS

– dBFS

20MHz

75

65

SFDR – dBc

55

45

–30 –25 0

2.5MHz

@ 25MSPS

25MHz

@ 125MSPS

–20 –15 –10 –5

Figure 10. Single-Tone SFDR vs.
A

@ f

OUT

OUT

= f

CLOCK

/5

–7–

85

0.675/0.725MHz

75

65

SFDR – dBc

55

45

–30 –25 0

@ 5MSPS

3.38/3.63MHz
@ 25MSPS

–20 –15 –10 –5

A

OUT

6.75/7.25MHz
@ 50MSPS

13.5/14.5MHz
@ 100MSPS

16.9/18.1MHz
@ 125MSPS

– dBFS

Figure 11. Dual-Tone SFDR vs. A
@ f

OUT

= f

CLOCK

/7

OUT

AD9760

–70

–75

2ND

–80

dBc

–85

–90

–95

HARMONIC

HARMONIC

4TH
HARMONIC

0 20 140

40 60 80 100 120

FREQUENCY – MSPS

Figure 12. THD vs. f

= 2 MHz

f

OUT

0.5

0.4

0.3

0.2

0.1

0

–0.1

ERROR – LSB

–0.2

–0.3

–0.4

–0.5

0

125 500 750

250 375 625 875

CODE

Figure 15. Typical INL

3RD

CLOCK

@

1000

80

I

OUTFS

2.5MHz

– mA

OUT

10MHz

40MHz

14

and I

75

70

65

60

SFDR – dBc

55

50

45

40

28 20

28.6MHz

4 6 10 12 16 18

Figure 13. SFDR vs. f
@ 100 MSPS, 0 dBFS

0.5

0.4

0.3

0.2

0.1

ERROR – LSB

0

–0.1

–0.2

0

250 500 750

375 625 875125

CODE

Figure 16. Typical DNL

OUTFS

1000

75

70

65

I

OUTA

60

SFDR – dBc

55

50

45

1 10 100

IDIFF @ 0dBFS

IDIFF @ –6dBFS

@ 0dBFS

I

@ –6dBFS

OUTA

OUTPUT FREQUENCY – MHz

Figure 14. Differential vs. Single­Ended SFDR vs. f

80

75

70

65

SFDR – dBc

60

55

50

2.5MHz

10MHz

40MHz

–40 –20 8060

TEMPERATURE – ⴗC

@ 100 MSPS

OUT

40200

Figure 17. SFDR vs. Temperature
@ 100 MSPS, 0 dBFS

0

f

= 125MSPS

CLOCK

= 9.95MHz

f

OUT

SFDR = 62dBc
AMPLITUDE = 0dBFS

10dB – Div

–100

START: 0.3MHz STOP: 62.5MHz

Figure 18. Single-Tone SFDR

0

f

= 100MSPS

CLOCK

= 13.5MHz

f

OUT1

= 14.5MHz

f

OUT2

SFDR = 61dBc
AMPLITUDE = 0dBFS

10dB – Div

–100

START: 0.3MHz STOP: 50.0MHz

Figure 19. Dual-Tone SFDR

–10

f

= 50MSPS

CLOCK

= 6.25MHz

f

OUT1

= 6.75MHz

f

OUT2

= 7.25MHz

f

OUT3

= 7.75MHz

f

OUT4

SFDR = 70dBc
AMPLITUDE = 0dBFS

10dB – Div

–110

START: 0.3MHz STOP: 25.0MHz

Figure 20. Four-Tone SFDR

–8–

REV. B

Typical AC Characterization Curves @ +3 V Supplies

(AVDD = +3 V, DVDD = +3 V, I

= 20 mA, 50 ⍀ Doubly Terminated Load, Differential Output, TA = +25ⴗC, SFDR up to Nyquist, unless otherwise noted)

OUTFS

AD9760

90

5MSPS

80

25MSPS

70

SFDR – dBc

60

125MSPS

50

0.1 100

Figure 21. SFDR vs. f

85

80

75

70

65

SFDR – dBc

60

55

50

0.00 5.00 25.0010.00 15.00 20.00

Figure 24. SFDR vs. f

110

FREQUENCY – MHz

–6dBFS

–12dBFS

0dBFS

FREQUENCY – MHz

OUT

OUT

100MSPS

50MSPS

@ 0 dBFS

@ 50 MSPS

85

80

75

70

65

SFDR – dBc

60

55

50

0.00 2.50

Figure 22. SFDR vs. f

85

80

75

70

65

SFDR – dBc

60

55

50

0.00 10.00 50.00

Figure 25. SFDR vs. f

0dBFS

–12dBFS

0.50 1.00 1.50 2.00
FREQUENCY – MHz

OUT

–6dBFS

–12dBFS

0dBFS

20.00 30.00 40.00

FREQUENCY – MHz

OUT

–6dBFS

@ 5 MSPS

@ 100 MSPS

85

80

75

70

65

SFDR – dBc

60

55

50

0.00 2.00 12.004.00 6.00 8.00 10.00

0dBFS

FREQUENCY – MHz

Figure 23. SFDR vs. f

85

80

75

–6dBFS

70

65

SFDR – dBc

60

0dBFS

55

50

0.00 10.00 60.0020.00 30.00 40.00 50.00

–12dBFS

FREQUENCY – MHz

Figure 26. SFDR vs. f

–6dBFS

–12dBFS

@ 25 MSPS

OUT

@ 125 MSPS

OUT

90

2.27MHz

80

455kHz

70

@ 5MSPS

60

SFDR – dBc

50

40

–30 –25 0

–20 –15 –10 –5

4.55MHz

@ 50MSPS

@ 100MSPS

A

– dBFS

OUT

@ 25MSPS

9.1MHz

@ 125MSPS

11.37MHz

Figure 27. Single-Tone SFDR vs. A
@ f

OUT

= f

CLOCK

/11

REV. B

OUT

90

OUT

– dBFS

1MHz

@ 5MSPS

10MHz

@ 50MSPS

25MHz
@ 125MSPS

80

2.5MHz

@ 25MSPS

70

20MHz
@ 100MSPS

60

SFDR – dBc

50

40

–30 –25 0

–20 –15 –10 –5

A

Figure 28. Single-Tone SFDR vs.

@ f

A

OUT

OUT

= f

CLOCK

/5

–9–

90

80

70

60

SFDR – dBc

50

40

–30 –25 0

0.675/0.725MHz
@ 5MSPS

6.75/7.25MHz
@ 50MSPS

16.9/18.1MHz
@ 125MSPS

–20 –15 –10 –5

A

OUT

13.5/14.5MHz
@ 100MSPS

– dBFS

3.38/3.63MHz
@ 25MSPS

Figure 29. Dual-Tone SFDR vs. A
@ f

OUT

= f

CLOCK

/7

OUT

AD9760

–70

–75

–80

dBc

–85

–90

–95

2ND

HARMONIC

4TH
HARMONIC

0 20 140

40 60 80 100 120

FREQUENCY – MSPS

Figure 30. THD vs. f

f

–0.1

ERROR – LSB

–0.2

–0.3

–0.4

–0.5

0.5

0.4

0.3

0.2

0.1

0

0

= 2 MHz

OUT

250 500 750

CODE

Figure 33. Typical INL

3RD
HARMONIC

CLOCK

875125 375 625

1000

80

75

70

65

60

SFDR – dBc

55

50

45

40

24 20

6 8 10 12 16 1 8

Figure 31. SFDR vs. f

22.4MHz

28.6MHz

I

– mA

REF

2.5MHz

10MHz

OUT

@ 100 MSPS, 0 dBFS

0.5

0.4

0.3

0.2

0.1

ERROR – LSB

0

–0.1

–0.2

250 500 750

0 875125 375 625

CODE

Figure 34. Typical DNL

14

and I

OUTFS

1000

75

70

65

60

SFDR – dBc

55

50

45

1 10 100

OUTPUT FREQUENCY – MHz

I

OUTA

–6dBFS

I

OUTA

0dBFS

@

@

IDIFF @
–6dBFS

IDIFF @

0dBFS

Figure 32. Differential vs. Single
Ended SFDR vs. f

80

75

70

65

10MHz

60

55

SFDR – dBc

50

45

40

28.6MHz

–40 –20 80

TEMPERATURE – ⴗC

@ 100 MSPS

OUT

2.5MHz

60

40200

Figure 35. SFDR vs. Temperature
@ 100 MSPS, 0 dBFS

0

f

= 125MSPS

CLOCK

= 9.95MHz

f

OUT

SFDR = 62dBc
AMPLITUDE = 0dBFS

10dB – Div

–100

START: 0.3MHz STOP: 62.5MHz

Figure 36. Single-Tone SFDR

0

f

= 100MSPS

CLOCK

= 13.5MHz

f

OUT1

= 14.5MHz

f

OUT2

SFDR = 59.0dBc
AMPLITUDE = 0dBFS

10dB – Div

–100

START: 0.3MHz STOP: 50.0MHz

Figure 37. Dual-Tone SFDR

–10

f

= 50MSPS

CLOCK

= 6.25MHz

f

OUT1

= 6.75MHz

f

OUT2

= 7.25MHz

f

OUT3

= 7.75MHz

f

OUT4

SFDR = 71dBc
AMPLITUDE = 0dBFS

10dB – Div

–110

START: 0.3MHz STOP: 25.0MHz

Figure 38. Four-Tone SFDR

–10–

REV. B

AD9760

FUNCTIONAL DESCRIPTION

Figure 39 shows a simplified block diagram of the AD9760.
The AD9760 consists of a large PMOS current source array that
is capable of providing up to 20 mA of total current. The array
is divided into 31 equal currents that make up the 5 most sig­nificant bits (MSBs). The next 4 bits or middle bits consist
of 15 equal current sources whose value is 1/16th of an MSB
current source. The remaining LSBs is a binary weighted frac­tion of the middle-bits current sources. Implementing the
middle and lower bits with current sources, instead of an R-2R
ladder, enhances its dynamic performance for multitone or low
amplitude signals and helps maintain the DAC’s high output
impedance (i.e., >100 kΩ).

All of these current sources are switched to one or the other of
the two output nodes (i.e., I

OUTA

or I

) via PMOS differen-

OUTB

tial current switches. The switches are based on a new architec­ture that drastically improves distortion performance. This new
switch architecture reduces various timing errors and provides
matching complementary drive signals to the inputs of the dif­ferential current switches.

The analog and digital sections of the AD9760 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 2.7 volt to 5.5 volt range. The digital
section, which is capable of operating up to a 125 MSPS clock
rate, consists of edge-triggered latches and segment decoding
logic circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.20 V bandgap
voltage reference and a reference control amplifier.

The full-scale output current is regulated by the reference con­trol amplifier and can be set from 2 mA to 20 mA via an exter­nal resistor, R

. The external resistor, in combination with

SET

both the reference control amplifier and voltage reference

, sets the reference current I

V

REFIO

, which is mirrored over to

REF

the segmented current sources with the proper scaling factor.
The full-scale current, I

, is thirty-two times the value of I

OUTFS

REF

.

DAC TRANSFER FUNCTION

The AD9760 provides complementary current outputs, I
and I
I

OUTFS

I

OUTB

current output appearing at I
both the input code and I

. I

OUTB

will provide a near full-scale current output,

OUTA

, when all bits are high (i.e., DAC CODE = 1023) while

, the complementary output, provides no current. The

OUTA

OUTFS

I

= (DAC CODE/1024) × I

OUTA

I

= (1023 – DAC CODE)/1024 × I

OUTB

and I

and can be expressed as:

OUTFS

is a function of

OUTB

OUTFS

OUTA

(1)

(2)

where DAC CODE = 0 to 1023 (i.e., Decimal Representation).

As mentioned previously, I
current I
V

REFIO

I

where I

, which is nominally set by a reference voltage,

REF

and external resistor R

= 32 × I

OUTFS

REF

= V

REF

REFIO/RSET

is a function of the reference

OUTFS

. It can be expressed as:

SET

(3)

(4)

The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, I
and I
loads, R
R

LOAD

I

OUTA

should be directly connected to matching resistive

OUTB

, that are tied to analog common, ACOM. Note,

LOAD

may represent the equivalent load resistance seen by

or I

as would be the case in a doubly terminated

OUTB

OUTA

50 Ω or 75 Ω cable. The single-ended voltage output appearing
at the I

V

OUTA

V

OUTB

Note the full-scale value of V

OUTA

= I

= I

and I

OUTA

OUTB

nodes is simply:

OUTB

× R

LOAD

× R

LOAD

OUTA

and V

should not exceed

OUTB

(5)

(6)

the specified output compliance range to maintain specified
distortion and linearity performance.

REV. B

0.1␮F

V

REFIO

R

CLOCK

SET

2k⍀

I

+5V

REF

+5V

0.1␮F

+1.20V REF

REFIO

FS ADJ

DVDD

DCOM

CLOCK

SLEEP

REFLO

SEGMENTED SWITCHES

FOR DB9–DB1

DIGITAL DATA INPUTS (DB9–DB0)

50pF

COMP1

PMOS

CURRENT SOURCE

ARRAY

LATCHES

AVDD ACOM

Figure 39. Functional Block Diagram

–11–

LSB

SWITCH

AD9760

COMP2

I

I

OUTA

OUTB

0.1␮F

I

OUTB

I

OUTA

V

DIFF

V

R
50⍀

= V

OUTB

LOAD

OUTA

– V

OUTB

V

R
50⍀

OUTA

LOAD

AD9760

The differential voltage, V
I

is:

OUTB

V

DIFF

= (I

OUTA

– I

OUTB

Substituting the values of I

, appearing across I

DIFF

) × R

LOAD

, I

OUTB

and I

OUTA

REF

; V

OUTA

DIFF

and

(7)

can be

expressed as:

V

= {(2 DAC CODE – 1023)/1024} ×

DIFF

(32 R

LOAD/RSET

) × V

REFIO

(8)

These last two equations highlight some of the advantages of
operating the AD9760 differentially. First, the differential op­eration will help cancel common-mode error sources associated
with I

OUTA

and I

such as noise, distortion and dc offsets.

OUTB

Second, the differential code dependent current and subsequent
voltage, V
output (i.e., V

, is twice the value of the single-ended voltage

DIFF

OUTA

or V

), thus providing twice the signal

OUTB

power to the load.

Note, the gain drift temperature performance for a single-ended
(V

OUTA

and V

) or differential output (V

OUTB

) of the AD9760

DIFF

can be enhanced by selecting temperature tracking resistors for
R

LOAD

and R

due to their ratiometric relationship as shown

SET

in Equation 8.

REFERENCE OPERATION

The AD9760 contains an internal 1.20 V bandgap reference
that can be easily disabled and overridden by an external refer­ence. REFIO serves as either an input or output depending on
whether the internal or an external reference is selected. If
REFLO is tied to ACOM, as shown in Figure 40, the internal
reference is activated and REFIO provides a 1.20 V output. In
this case, the internal reference must be compensated externally
with a ceramic chip capacitor of 0.1 µF or greater from REFIO
to REFLO. Also, REFIO should be buffered with an external
amplifier having an input bias current less than 100 nA if any
additional loading is required.

+5V

50pF

0.1␮F

COMP1

CURRENT

AVDD

SOURCE

ARRAY

ADDITIONAL

LOAD

OPTIONAL
EXTERNAL

REF BUFFER

0.1␮F

2k⍀

REFLO

+1.2V REF

REFIO

FS ADJ

AD9760

Figure 40. Internal Reference Configuration

The internal reference can be disabled by connecting REFLO to
AVDD. In this case, an external reference may be applied to
REFIO as shown in Figure 41. The external reference may
provide either a fixed reference voltage to enhance accuracy and
drift performance or a varying reference voltage for gain control.
Note that the 0.1 µF compensation capacitor is not required
since the internal reference is disabled, and the high input im­pedance (i.e., 1 MΩ) of REFIO minimizes any loading of the
external reference.

REFERENCE CONTROL AMPLIFIER

The AD9760 also contains an internal control amplifier that is
used to regulate the DAC’s full-scale output current, I

OUTFS

.
The control amplifier is configured as a V-I converter as shown
in Figure 41, so that its current output, I
the ratio of the V
in Equation 4. I

and an external resistor, R

REFIO

is copied over to the segmented current

REF

sources with the proper scaling factor to set I

, is determined by

REF

SET

OUTFS

, as stated

as stated in

Equation 3.

AVDD

0.1␮F

AVDD

EXTERNAL

REF

REFLO

+1.2V REF

V

REFIO

R

SET

I

REF

V

REFIO/RSET

REFIO

FS ADJ

=

AD9760

50pF

REFERENCE
CONTROL
AMPLIFIER

COMP1

CURRENT

SOURCE

AVDD

ARRAY

Figure 41. External Reference Configuration

The control amplifier allows a wide (10:1) adjustment span of
I

over a 2 mA to 20 mA range by setting IREF between

OUTFS

62.5 µA and 625 µA. The wide adjustment span of I

OUTFS

pro­vides several application benefits. The first benefit relates
directly to the power dissipation of the AD9760, which is
proportional to I

(refer to the Power Dissipation section).

OUTFS

The second benefit relates to the 20 dB adjustment, which is
useful for system gain control purposes.

The small signal bandwidth of the reference control amplifier is
approximately 1.4 MHz and can be reduced by connecting an
external capacitor between COMP1 and AVDD. The output of
the control amplifier, COMP1, is internally compensated via a
50 pF capacitor that limits the control amplifier small-signal
bandwidth and reduces its output impedance. Any additional
external capacitance further limits the bandwidth and acts as a
filter to reduce the noise contribution from the reference ampli­fier. Figure 42 shows the relationship between the external
capacitor and the small signal –3 dB bandwidth of the refer­ence amplifier. Since the –3 dB bandwidth corresponds to the
dominant pole, and hence the time constant, the settling time of
the control amplifier to a stepped reference input response can
be approximated.

1000

10

BANDWIDTH – kHz

0.1

0.1 10001
COMP1 CAPACITOR – nF

10 100

Figure 42. External COMP1 Capacitor vs. –3 dB Bandwidth

–12–

REV. B

AVDD

AD9760

AVDD

1.2V

AD1580

R

OUT1

OUT2

AGND

FB

AD7524

V

DD

V

DB7–DB0

REF

0.1V TO 1.2V

R

SET

I

REF

V

REF/RSET

Figure 43. Single-Supply Gain Control Circuit

The optimum distortion performance for any reconstructed
waveform is obtained with a 0.1 µF external capacitor installed.
Thus, if I

is fixed for an application, a 0.1 µF ceramic chip

REF

capacitor is recommended. Also, since the control amplifier is
optimized for low power operation, multiplying applications
requiring large signal swings should consider using an external
control amplifier to enhance the application’s overall large signal
multiplying bandwidth and/or distortion performance.

There are two methods in which I

. The first method is suitable for a single-supply system in

R

SET

can be varied for a fixed

REF

which the internal reference is disabled, and the common-mode
voltage of REFIO is varied over its compliance range of 1.25 V
to 0.10 V. REFIO can be driven by a single-supply amplifier or
DAC, allowing I

to be varied for a fixed R

REF

. Since the

SET

input impedance of REFIO is approximately 1 MΩ, a simple,
low cost R-2R ladder DAC configured in the voltage mode
topology may be used to control the gain. This circuit is shown
in Figure 43 using the AD7524 and an external 1.2 V reference,
the AD1580.

The second method may be used in a dual-supply system in
which the common-mode voltage of REFIO is fixed and I
varied by an external voltage, V

, applied to R

GC

via an ampli-

SET

REF

is

fier. An example of this method is shown in Figure 44 where
the internal reference is used to set the common-mode voltage
of the control amplifier to 1.20 V. The external voltage, V

GC

, is
referenced to ACOM and should not exceed 1.2 V. The value
of R

SET

is such that I

REFMAX

and I

do not exceed 62.5 µA

REFMIN

and 625 µA, respectively. The associated equations in Figure 44
can be used to determine the value of R

BANDLIMITING

REFLO

+1.2V REF

REFIO

1␮F

V

R

SET

GC

FS ADJ

I

AD9760

REF

I

= (1.2 – VGC)/R

REF

WITH VGC < V

REFIO

.

SET

OPTIONAL

CAPACITOR

50pF

SET

AND 62.5␮A I

COMP1

CURRENT

SOURCE

REF

AVDD

AVDD

ARRAY

625A

Figure 44. Dual-Supply Gain Control Circuit

OPTIONAL

BANDLIMITING

CAPACITOR

REFLO

+1.2V REF

REFIO

FS ADJ

=

AD9760

50pF

COMP1

CURRENT

AVDD

SOURCE

ARRAY

In some applications, the user may elect to use an external con­trol amplifier to enhance the multiplying bandwidth, distortion
performance and/or settling time. External amplifiers capable of
driving a 50 pF load such as the AD817 are suitable for this
purpose. It is configured in such a way that it is in parallel with
the weaker internal reference amplifier as shown in Figure 45.
In this case, the external amplifier simply overdrives the weaker
reference control amplifier. Also, since the internal control
amplifier has a limited current output, it will sustain no damage
if overdriven.

EXTERNAL

CONTROL AMPLIFIER

V

REF

INPUT

R

SET

+1.2V REF

50pF

REFIO

FS ADJ

AD9760

COMP1

CURRENT

SOURCE

ARRAY

AVDD

AVDDREFLO

Figure 45. Configuring an External Reference Control
Amplifier

ANALOG OUTPUTS

The AD9760 produces two complementary current outputs,
I

and I

OUTA

differential operation. I
complementary single-ended voltage outputs, V
via a load resistor, R

, which may be configured for single-ended or

OUTB

and I

OUTA

, as described in the DAC Transfer

LOAD

can be converted into

OUTB

OUTA

and V

OUTB

,

Function section by Equations 5 through 8. The differential
voltage, V

, existing between V

DIFF

OUTA

and V

can also be

OUTB

converted to a single-ended voltage via a transformer or differ­ential amplifier configuration. The ac performance of the AD9760
is optimum and specified using a differential transformer
coupled output in which the voltage swing at I

OUTA

and I

OUTB

is

limited to ±0.5 V. If a single-ended unipolar output is desirable,

should be selected.

I

OUTA

The distortion and noise performance of the AD9760 can be
enhanced when the AD9760 is configured for differential opera­tion. The common-mode error sources of both I

OUTA

and I

OUTB

can be significantly reduced by the common-mode rejection of a
transformer or differential amplifier. These common-mode
error sources include even-order distortion products and noise.

REV. B

–13–

AD9760

The enhancement in distortion performance becomes more
significant as the frequency content of the reconstructed wave­form increases. This is due to the first order cancellation of
various dynamic common-mode distortion mechanisms, digi­tal feedthrough and noise.

Performing a differential-to-single-ended conversion via a
transformer also provides the ability to deliver twice the re­constructed signal power to the load (i.e., assuming no source
termination). Since the output currents of I

OUTA

and I

OUTB

are
complementary, they become additive when processed differ­entially. A properly selected transformer will allow the AD9760
to provide the required power and voltage levels to different
loads. Refer to Applying the AD9760 section for examples of
various output configurations.

The output impedance of I

OUTA

and I

is determined by the

OUTB

equivalent parallel combination of the PMOS switches associ­ated with the current sources and is typically 100 kΩ in parallel
with 5 pF. It is also slightly dependent on the output voltage
(i.e., V
As a result, maintaining I

OUTA

and V

) due to the nature of a PMOS device.

OUTB

OUTA

and/or I

at a virtual ground

OUTB

via an I-V op amp configuration will result in the optimum dc
linearity. Note the INL/DNL specifications for the AD9760 are
measured with I

maintained at a virtual ground via an

OUTA

op amp.

I

OUTA

and I

also have a negative and positive voltage com-

OUTB

pliance range that must be adhered to in order to achieve opti­mum performance. The negative output compliance range of
–1.0 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a break­down of the output stage and affect the reliability of the AD9760.

The positive output compliance range is slightly dependent on
the full-scale output current, I
its nominal 1.25 V for an I
I

= 2 mA. The optimum distortion performance for a

OUTFS

OUTFS

. It degrades slightly from

OUTFS

= 20 mA to 1.00 V for an

single-ended or differential output is achieved when the maximum
full-scale signal at I

OUTA

and I

plications requiring the AD9760’s output (i.e., V

) to extend its output compliance range should size R

V

OUTB

does not exceed 0.5 V. Ap-

OUTB

OUTA

and/or

LOAD

accordingly. Operation beyond this compliance range will ad­versely affect the AD9760’s linearity performance and subse­quently degrade its distortion performance.

DIGITAL INPUTS

The AD9760’s digital input consists of 10 data input pins and a
clock input pin. The 10-bit parallel data inputs follow standard
positive binary coding where DB9 is the most significant bit
(MSB) and DB0 is the least significant bit (LSB). I

OUTA

pro­duces a full-scale output current when all data bits are at
Logic 1. I

produces a complementary output with the full-

OUTB

scale current split between the two outputs as a function of the
input code.

The digital interface is implemented using an edge-triggered
master slave latch. The DAC output is updated following the
rising edge of the clock as shown in Figure 1 and is designed to
support a clock rate as high as 125 MSPS. The clock can be
operated at any duty cycle that meets the specified latch pulse­width. The setup and hold times can also be varied within the

clock cycle as long as the specified minimum times are met
although the location of these transition edges may affect digital
feedthrough and distortion performance. Best performance is

typically achieved when the input data transitions on the falling edge
of a 50% duty cycle clock.

The digital inputs are CMOS compatible with logic thresholds,
V

THRESHOLD

set to approximately half the digital positive supply

(DVDD) or

V

THRESHOLD

= DVDD/2 (±20%)

The internal digital circuitry of the AD9760 is capable of oper­ating over a digital supply range of 2.7 V to 5.5 V. As a result,
the digital inputs can also accommodate TTL levels when
DVDD is set to accommodate the maximum high level voltage
V

. A DVDD of 3 V to 3.3 V will typically ensure proper

OH(MAX)

compatibility with most TTL logic families. Figure 46 shows the
equivalent digital input circuit for the data and clock inputs.
The sleep mode input is similar with the exception that it con­tains an active pull-down circuit, ensuring that the AD9760
remains enabled if this input is left disconnected.

DVDD

DIGITAL

INPUT

Figure 46. Equivalent Digital Input

Since the AD9760 is capable of being updated up to 125 MSPS,
the quality of the clock and data input signals are important in
achieving the optimum performance. The drivers of the digital
data interface circuitry should be specified to meet the mini­mum setup and hold times of the AD9760 as well as its required
min/max input logic level thresholds. Typically, the selection of
the slowest logic family that satisfies the above conditions will
result in the lowest data feedthrough and noise.

Digital signal paths should be kept short and run lengths
matched to avoid propagation delay mismatch. The insertion of
a low value resistor network (i.e., 20 Ω to 100 Ω) between the
AD9760 digital inputs and driver outputs may be helpful in
reducing any overshooting and ringing at the digital inputs that
contribute to data feedthrough. For longer run lengths and high
data update rates, strip line techniques with proper termination
resistors should be considered to maintain “clean” digital in­puts. Also, operating the AD9760 with reduced logic swings and
a corresponding digital supply (DVDD) will also reduce data
feedthrough.

The external clock driver circuitry should provide the AD9760
with a low jitter clock input meeting the min/max logic levels
while providing fast edges. Fast clock edges will help minimize
any jitter that will manifest itself as phase noise on a recon­structed waveform. Thus, the clock input should be driven by
the fastest logic family suitable for the application.

–14–

REV. B

AD9760

Note, the clock input could also be driven via a sine wave that is
centered around the digital threshold (i.e., DVDD/2), and
meets the min/max logic threshold. This will typically result in a
slight degradation in the phase noise, that becomes more notice­able at higher sampling rates and output frequencies. Also, at
higher sampling rates, the 20% tolerance of the digital logic
threshold should be considered since it will affect the effective
clock duty cycle and subsequently cut into the required data
setup and hold times.

SLEEP MODE OPERATION

The AD9760 has a power-down function that turns off the out­put current and reduces the supply current to less than 8.5 mA
over the specified supply range of 2.7 V to 5.5 V and tempera­ture range. This mode can be activated by applying a logic level
“1” to the SLEEP pin. This digital input also contains an active
pull-down circuit that ensures that the AD9760 remains enabled
if this input is left disconnected. The SLEEP input with active
pull-down requires <40 µA of drive current.

The power-up and power-down characteristics of the AD9760
are dependent upon the value of the compensation capacitor
connected to COMP1. With a nominal value of 0.1 µF, the
AD9760 takes less than 5 µs to power down and approximately

3.25 ms to power back up. Note, the SLEEP MODE should not
be used when the external control amplifier is used as shown in
Figure 45.

Conversely, I
form, f

CLOCK

show I

DVDD

(f

OUT/fCLOCK

DVDD = 3 V, respectively. Note how I

is dependent on both the digital input wave-

DVDD

, and digital supply DVDD. Figures 48 and 49

as a function of full-scale sine wave output ratios

) for various update rates with DVDD = 5 V and

is reduced by more

DVDD

than a factor of 2 when DVDD is reduced from 5 V to 3 V.

18

16

14

12

10

– mA

8

DVDD

I

6

4

2

0

0.01 10.1

Figure 48. I

8

RATIO (f

vs. Ratio @ DVDD = 5 V

DVDD

OUT/fCLK

125MSPS

100MSPS

50MSPS

25MSPS

5MSPS

)

125MSPS

POWER DISSIPATION

The power dissipation, PD, of the AD9760 is dependent on
several factors that include: (1) AVDD and DVDD, the power
supply voltages; (2) I

, the update rate; (4) and the reconstructed digital input

f

CLOCK

, the full-scale current output; (3)

OUTFS

waveform. The power dissipation is directly proportional to the
analog supply current, I

. I

I

DVDD

is directly proportional to I

AVDD

ure 47 and is insensitive to f

30

25

20

– mA

15

AVDD

I

10

5

0

2204 6 8 10 12141618

Figure 47. I

, and the digital supply current,

AVDD

CLOCK

I

OUTFS

AVDD

.

– mA

vs. I

as shown in Fig-

OUTFS

OUTFS

6

– mA

4

DVDD

I

2

0

0.01 10.1

Figure 49. I

RATIO (f

vs. Ratio @ DVDD = 3 V

DVDD

OUT/fCLK

100MSPS

50MSPS

25MSPS

5MSPS

)

REV. B

–15–

AD9760

APPLYING THE AD9760

OUTPUT CONFIGURATIONS

The following sections illustrate some typical output configura­tions for the AD9760. Unless otherwise noted, it is assumed
that I

is set to a nominal 20 mA. For applications requir-

OUTFS

ing the optimum dynamic performance, a differential output
configuration is suggested. A differential output configuration
may consist of either an RF transformer or a differential op amp
configuration. The transformer configuration provides the opti­mum high frequency performance and is recommended for any
application allowing for ac coupling. The differential op amp
configuration is suitable for applications requiring dc coupling, a
bipolar output, signal gain and/or level shifting.

A single-ended output is suitable for applications requiring a
unipolar voltage output. A positive unipolar output voltage will
result if I
sized load resistor, R

OUTA

and/or I

LOAD

is connected to an appropriately

OUTB

, referred to ACOM. This configura­tion may be more suitable for a single-supply system requiring
a dc coupled, ground referred output voltage. Alternatively, an
amplifier could be configured as an I-V converter, thus convert­ing I
figuration provides the best dc linearity since I
maintained at a virtual ground. Note that I
better performance than I

OUTA

or I

into a negative unipolar voltage. This con-

OUTB

OUTB

.

OUTA

or I

OUTA

provides slightly

OUTB

is

DIFFERENTIAL COUPLING USING A TRANSFORMER

An RF transformer can be used to perform a differential-to­single-ended signal conversion as shown in Figure 50. A
differentially coupled transformer output provides the optimum
distortion performance for output signals whose spectral content
lies within the transformer’s passband. An RF transformer such
as the Mini-Circuits T1-1T provides excellent rejection of com­mon-mode distortion (i.e., even-order harmonics) and noise
over a wide frequency range. It also provides electrical isolation
and the ability to deliver twice the power to the load. Trans­formers with different impedance ratios may also be used for
impedance matching purposes. Note that the transformer
provides ac coupling only.

MINI-CIRCUITS

I

OUTA

AD9760

I

OUTB

22

21

T1-1T

OPTIONAL R

DIFF

R

LOAD

Figure 50. Differential Output Using a Transformer

The center tap on the primary side of the transformer must be
connected to ACOM to provide the necessary dc current path
for both I
ing at I

OUTA

OUTA

and I

and I

. The complementary voltages appear-

OUTB

OUTB

(i.e., V

OUTA

and V

) swing symmetri-

OUTB

cally around ACOM and should be maintained with the specified
output compliance range of the AD9760. A differential resistor,

, may be inserted in applications where the output of the

R

DIFF

transformer is connected to the load, R
construction filter or cable. R

is determined by the

DIFF

, via a passive re-

LOAD

transformer’s impedance ratio and provides the proper source
termination that results in a low VSWR. Note that approxi­mately half the signal power will be dissipated across R

DIFF

.

DIFFERENTIAL USING AN OP AMP

An op amp can also be used to perform a differential to single­ended conversion as shown in Figure 51. The AD9760 is con­figured with two equal load resistors, R
differential voltage developed across I

, of 25 Ω. The

LOAD

and I

OUTA

OUTB

is con­verted to a single-ended signal via the differential op amp con­figuration. An optional capacitor can be installed across I
and I

, forming a real pole in a low-pass filter. The addition

OUTB

OUTA

of this capacitor also enhances the op amps distortion perfor­mance by preventing the DACs high slewing output from over­loading the op amp’s input.

500⍀

AD9760

I

OUTA

I

OUTB

22

21

C

OPT

225⍀

225⍀

25⍀25⍀

AD8047

500⍀

Figure 51. DC Differential Coupling Using an Op Amp

The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the differ­ential op amp circuit using the AD8047 is configured to provide
some additional signal gain. The op amp must operate off of a
dual supply since its output is approximately ±1.0 V. A high
speed amplifier capable of preserving the differential perfor­mance of the AD9760 while meeting other system level objec­tives (i.e., cost, power) should be selected. The op amps
differential gain, its gain setting resistor values, and full-scale
output swing capabilities should all be considered when opti­mizing this circuit.

The differential circuit shown in Figure 52 provides the neces­sary level-shifting required in a single supply system. In this
case, AVDD which is the positive analog supply for both the
AD9760 and the op amp is also used to level-shift the differ­ential output of the AD9760 to midsupply (i.e., AVDD/2). The
AD8041 is a suitable op amp for this application.

500⍀

AD9760

I

OUTA

I

OUTB

22

21

C

OPT

225⍀

1k⍀

AD8041

1k⍀

AVDD

225⍀

25⍀25⍀

Figure 52. Single-Supply DC Differential Coupled Circuit

SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT

Figure 53 shows the AD9760 configured to provide a unipolar
output range of approximately 0 V to +0.5 V for a doubly termi­nated 50 Ω cable since the nominal full-scale current, I
20 mA flows through the equivalent R
R

represents the equivalent load resistance seen by I

LOAD

I

. The unused output (I

OUTB

OUTA

or I

to ACOM directly or via a matching R

of 25 Ω. In this case,

LOAD

) can be connected

OUTB

. Different values of

LOAD

OUTFS

OUTA

, of

or

–16–

REV. B

AD9760

I

OUTFS

and R

can be selected as long as the positive compli-

LOAD

ance range is adhered to. One additional consideration in this
mode is the integral nonlinearity (INL) as discussed in the Ana­log Output section of this data sheet. For optimum INL perfor­mance, the single-ended, buffered voltage output configuration
is suggested.

AD9760

I

OUTA

I

OUTB

I

= 20mA

OUTFS

22

50⍀

21

25⍀

V

OUTA

= 0 TO +0.5V

50⍀

Figure 53. 0 V to +0.5 V Unbuffered Voltage Output

SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
CONFIGURATION

Figure 54 shows a buffered single-ended output configuration
in which the op amp U1 performs an I-V conversion on the
AD9760 output current. U1 maintains I

OUTA

(or I

OUTB

) at a
virtual ground, thus minimizing the nonlinear output impedance
effect on the DAC’s INL performance as discussed in the Ana­log Output section. Although this single-ended configuration
typically provides the best dc linearity performance, its ac distor­tion performance at higher DAC update rates may be limited by
U1’s slewing capabilities. U1 provides a negative unipolar out­put voltage and its full-scale output voltage is simply the product

and I

of R

FB

U1’s voltage output swing capabilities by scaling I
R

. An improvement in ac distortion performance may result

FB

with a reduced I

. The full-scale output should be set within

OUTFS

OUTFS

since the signal current U1 will be required

OUTFS

and/or

to sink will be subsequently reduced.

C

OPT

R

FB

200⍀

U1

V

= I

OUTFS

ⴛ R

FB

OUT

AD9760

I

OUTA

I

OUTB

I

= 10mA

OUTFS

22

21

200⍀

Figure 54. Unipolar Buffered Voltage Output

POWER AND GROUNDING CONSIDERATIONS

In systems seeking to simultaneously achieve high speed and
high performance, the implementation and construction of the
printed circuit board design is often as important as the circuit
design. Proper RF techniques must be used in device selection,
placement and routing, and supply bypassing and grounding.
The evaluation board for the AD9760, which uses a four-layer
PC board, serves as a good example for the above-mentioned
considerations. Figures 60–65 illustrate the recommended
printed circuit board ground, power and signal plane layouts
that are implemented on the AD9760 evaluation board.

Proper grounding and decoupling should be a primary objective
in any high speed, high resolution system. The AD9760 features
separate analog and digital supply and ground pins to optimize

the management of analog and digital ground currents in a
system. In general, AVDD, the analog supply, should be de­coupled to ACOM, the analog common, as close to the chip as
physically possible. Similarly, DVDD, the digital supply, should
be decoupled to DCOM as close as physically possible.

For those applications that require a single +5 V or +3 V supply
for both the analog and digital supply, a clean analog supply
may be generated using the circuit shown in Figure 55. The
circuit consists of a differential LC filter with separate power
supply and return lines. Lower noise can be attained using low
ESR type electrolytic and tantalum capacitors.

FERRITE

BEADS

TTL/CMOS

LOGIC

CIRCUITS

+5V OR +3V

POWER SUPPLY

100␮F
ELECT.

10-22␮F
TANT.

0.1␮F
CER.

AVDD

ACOM

Figure 55. Differential LC Filter for Single +5 V or +3 V
Applications

Maintaining low noise on power supplies and ground is critical
to obtain optimum results from the AD9760. If properly imple­mented, ground planes can perform a host of functions on high
speed circuit boards: bypassing, shielding, current transport,
etc. In mixed signal design, the analog and digital portions of
the board should be distinct from each other, with the analog
ground plane confined to the areas covering the analog signal
traces, and the digital ground plane confined areas covering the
digital interconnects.

All analog ground pins of the DAC, reference and other analog
components should be tied directly to the analog ground plane.
The two ground planes should be connected by a path 1/8 to
1/4 inch wide underneath or within 1/2 inch of the DAC to
maintain optimum performance. Care should be taken to ensure
that the ground plane is uninterrupted over crucial signal paths.
On the digital side, this includes the digital input lines running
to the DAC as well as any clock signals. On the analog side, this
includes the DAC output signal, reference signal and the supply
feeders.

The use of wide runs or planes in the routing of power lines is
also recommended. This serves the dual role of providing a low
series impedance power supply to the part and providing some
“free” capacitive decoupling to the appropriate ground plane. It
is essential that care be taken in the layout of signal and power
ground interconnects to avoid inducing extraneous voltage
drops in the signal ground paths. It is recommended that all
connections be short, direct and as physically close to the pack­age as possible to minimize the sharing of conduction paths
between different currents. When runs exceed an inch in length,
strip line techniques with proper termination resistor should be
considered. The necessity and value of this resistor will be de­pendent upon the logic family used.

For a more detailed discussion of the implementation and con­struction of high speed, mixed signal printed circuit boards,
refer to Analog Devices’ application notes AN-280 and AN-333.

REV. B

–17–

AD9760

APPLICATIONS
Using the AD9760 for QAM Modulation

QAM is one of the most widely used digital modulation schemes
in digital communication systems. This modulation technique
can be found in both FDM spreadspectrum (i.e., CDMA) based
systems. A QAM signal is a carrier frequency that is both
modulated in amplitude (i.e., AM modulation) and in phase
(i.e., PM modulation). It can be generated by independently
modulating two carriers of identical frequency but with a 90°
phase difference. This results in an in-phase (I) carrier compo­nent and a quadrature (Q) carrier component at a 90° phase
shift with respect to the I component. The I and Q components
are then summed to provide a QAM signal at the specified car­rier frequency.

A common and traditional implementation of a QAM modu­lator is shown in Figure 56. The modulation is performed in the
analog domain in which two DACs are used to generate the
baseband I and Q components, respectively. Each component is
then typically applied to a Nyquist filter before being applied to
a quadrature mixer. The matching Nyquist filters shape and
limit each component’s spectral envelope while minimizing
intersymbol interference. The DAC is typically updated at the
QAM symbol rate or possibly a multiple of it if an interpolating
filter precedes the DAC. The use of an interpolating filter typi­cally eases the implementation and complexity of the analog
filter, which can be a significant contributor to mismatches in
gain and phase between the two baseband channels. A quadra­ture mixer modulates the I and Q components with in-phase
and quadrature phase carrier frequency and sums the two out­puts to provide the QAM signal.

10

AD9760

DSP

OR

ASIC

10

AD9760

CARRIER

FREQUENCY

NYQUIST
FILTERS

Figure 56. Typical Analog QAM Architecture

In this implementation, it is much more difficult to maintain
proper gain and phase matching between the I and Q channels.
The circuit implementation shown in Figure 57 helps improve
on the matching and temperature stability characteristics be­tween the I and Q channels. Using a single voltage reference
derived from U1 to set the gain for both the I and Q channels
will improve the gain matching and stability. Further enhance­ments in gain matching and stability are achieved by using sepa­rate matching resistor networks for both R
Additional trim capability via R

CAL1

compensate for any initial mismatch in gain between the two
channels. This may be attributed to any mismatch between U1
and U2’s gain setting resistor (R

), and/or voltage offset of each DAC’s control amplifier.

(R

LOAD

SET

The differential voltage outputs of U1 and U2 are fed into their
respective differential inputs of a quadrature mixer via matching
50 Ω filter networks.

It is also possible to generate a QAM signal completely in the
digital domain via a DSP or ASIC, in which case only a single
DAC of sufficient resolution and performance is required to
reconstruct the QAM signal. Also available from several vendors

and R

0

90

QUADRATURE

MODULATOR

and R

SET

can be added to

CAL2

TO

Σ

MIXER

.

LOAD

), effective load resistance,

R
2k⍀*

R

CAL1

0.1␮F

R

2k⍀*

R

CAL2

100⍀

SET

50⍀

SET

REFLO

REFIO

FS ADJ

CLOCK

REFIO

FS ADJ

* OHMTEK ORNA1001F
** OHMTEK TOMC1603-50F

U1

I-CHANNEL

CLOCK

AVDD

CLOCK

REFLO

U2

Q-CHANNEL

I

OUTA

I

OUTB

I

OUTA

I

OUTB

50⍀**
R

LOAD

50⍀**
R

LOAD

50⍀**
R

LOAD

50⍀**
R

LOAD

TO
NYQUIST
FILTER
AND MIXER

TO
NYQUIST
FILTER
AND MIXER

Figure 57. Baseband QAM Implementation Using Two
AD9760s

are Digital ASICs which implement other digital modulation
schemes such as PSK and FSK. This digital implementation has
the benefit of generating perfectly matched I and Q components
in terms of gain and phase, which is essential in maintaining
optimum performance in a communication system. In this
implementation, the reconstruction DAC must be operating at a
sufficiently high clock rate to accommodate the highest specified
QAM carrier frequency. Figure 58 shows a block diagram of
such an implementation using the AD9760.

QAM

12

NCO

COS

CLOCK

10

AD9760

LPF

50⍀

50⍀

TO
MIXER

I DATA

Q DATA

CARRIER

FREQUENCY

12

12

12

STEL-1130

12

SIN

STEL-1177

Figure 58. Digital QAM Architecture

AD9760 EVALUATION BOARD
General Description

The AD9760-EB is an evaluation board for the AD9760 10-bit
D/A converter. Careful attention to layout and circuit design,
combined with a prototyping area, allow the user to easily and
effectively evaluate the AD9760 in any application where high
resolution, high speed conversion is required.

This board allows the user the flexibility to operate the AD9760
in various configurations. Possible output configurations include
transformer coupled, resistor terminated, inverting/noninverting
and differential amplifier outputs. The digital inputs are designed
to be driven directly from various word generators with the on­board option to add a resistor network for proper load termina­tion. Provisions are also made to operate the AD9760 with
either the internal or external reference or to exercise the power­down feature.

Refer to the application note AN-420, “Using the AD9760/
AD9760/AD9764-EB Evaluation Board,” for a thorough
description and operating instructions for the AD9760 evalua­tion board.

–18–

REV. B

AD9760

REV. B

Figure 59. Evaluation Board Schematic

–19–

AD9760

Figure 60. Silkscreen Layer—Top

Figure 61. Component Side PCB Layout (Layer 1)

–20–

REV. B

AD9760

Figure 62. Ground Plane PCB Layout (Layer 2)

REV. B

Figure 63. Power Plane PCB Layout (Layer 3)

–21–

AD9760

Figure 64. Solder Side PCB Layout (Layer 4)

Figure 65. Silkscreen Layer—Bottom

–22–

REV. B

28

15

14

1

0.386 (9.80)

0.378 (9.60)

0.256 (6.50)

0.246 (6.25)

0.177 (4.50)

0.169 (4.30)

PIN 1

SEATING

PLANE

0.006 (0.15)

0.002 (0.05)

0.0118 (0.30)

0.0075 (0.19)

0.0256 (0.65)
BSC

0.0433
(1.10)

MAX

0.0079 (0.20)

0.0035 (0.090)

0.028 (0.70)

0.020 (0.50)

8ⴗ
0ⴗ

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

28-Lead, 300 Mil SOIC

(R-28)

0.7125 (18.10)

0.6969 (17.70)

AD9760

28 15

PIN 1

0.0500

0.0118 (0.30)

0.0040 (0.10)

(1.27)

BSC

0.0192 (0.49)

0.0138 (0.35)

141

0.1043 (2.65)

0.0926 (2.35)

SEATING

PLANE

0.2992 (7.60)

0.2914 (7.40)

0.4193 (10.65)

0.3937 (10.00)

0.0125 (0.32)

0.0091 (0.23)

0.0291 (0.74)

0.0098 (0.25)

0.0500 (1.27)

8ⴗ
0ⴗ

0.0157 (0.40)

28-Lead Thin Shrink Small Outline Package (TSSOP)

(RU-28)

C2200b–1–3/00 (rev. B)

ⴛ 45ⴗ

REV. B

PRINTED IN U.S.A.

–23–