Analog Devices AD9754 Datasheet

a

150pF

+1.20V REF

AVDD

ACOM

REFLO

ICOMP

CURRENT

SOURCE

ARRAY

+5V

SEGMENTED

SWITCHES

LSB

SWITCHES

REFIO
FS ADJ

DVDD
DCOM

CLOCK

+5V

R

SET

0.1mF

CLOCK

IOUTA
IOUTB

0.1mF

LATCHES

AD9754

SLEEP

DIGITAL DATA INPUTS (DB13–DB0)

14-Bit, 125 MSPS High Performance

®

TxDAC

D/A Converter

AD9754*

FEATURES
High Performance Member of Pin-Compatible

TxDAC Product Family
125 MSPS Update Rate
14-Bit Resolution
Excellent Spurious Free Dynamic Range Performance
SFDR to Nyquist @ 5 MHz Output: 83 dBc
Differential Current Outputs: 2 mA to 20 mA
Power Dissipation: 185 mW @ 5 V
Power-Down Mode: 20 mW @ 5 V
On-Chip 1.20 V Reference
CMOS-Compatible +2.7 V to +5.5 V Digital Interface
Package: 28-Lead SOIC, TSSOP Packages
Edge-Triggered Latches

APPLICATIONS
Wideband Communication Transmit Channel:

Direct IF

Basestations

Wireless Local Loop

Digital Radio Link
Direct Digital Synthesis (DDS)
Instrumentation

PRODUCT DESCRIPTION

The AD9754 is a 14-bit resolution, wideband, second genera­tion member of the TxDAC series of high performance, low
power CMOS digital-to-analog-converters (DACs). The
TxDAC

family, which consists of pin compatible 8-, 10-, 12­and 14-bit DACs, is specifically optimized for the transmit
signal path of communication systems. All of the devices share
the same interface options, small outline package and pinout,
providing an upward or downward component selection path
based on performance, resolution and cost. The AD9754 offers
exceptional ac and dc performance while supporting update
rates up to 125 MSPS.

The AD9754’s flexible single-supply operating range of +4.5 V to
+5.5 V and low power dissipation are well suited for portable and
low power applications. Its power dissipation can be further reduc­ed to a mere 65 mW with a slight degradation in performance by
lowering the full-scale current output. Also, a power-down mode
reduces the standby power dissipation to approximately 20 mW.

The AD9754 is manufactured on an advanced CMOS process.
A segmented current source architecture is combined with a
proprietary switching technique to reduce spurious components
and enhance dynamic performance. Edge-triggered input latches
and a 1.2 V temperature compensated bandgap reference have
been integrated to provide a complete monolithic DAC solution.
The digital inputs support +2.7 V and +5 V CMOS logic families.

TxDAC is a registered trademark of Analog Devices, Inc.
*Protected by U.S. Patents Numbers 5450084, 5568145, 5689257, 5612697 and

5703519. Other patents pending.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

FUNCTIONAL BLOCK DIAGRAM

The AD9754 is a current-output DAC with a nominal full-scale

output current of 20 mA and > 100 kΩ output impedance.

Differential current outputs are provided to support single­ended or differential applications. Matching between the two
current outputs ensures enhanced dynamic performance in a
differential output configuration. The current outputs may be
tied directly to an output resistor to provide two complemen­tary, single-ended voltage outputs or fed directly into a trans­former. The output voltage compliance range is 1.25 V.

The on-chip reference and control amplifier are configured for
maximum accuracy and flexibility. The AD9754 can be driven
by the on-chip reference or by a variety of external reference
voltages. The internal control amplifier, which provides a wide
(>10:1) adjustment span, allows the AD9754 full-scale current
to be adjusted over a 2 mA to 20 mA range while maintaining
excellent dynamic performance. Thus, the AD9754 may operate
at reduced power levels or be adjusted over a 20 dB range to
provide additional gain ranging capabilities.

The AD9754 is available in 28-lead SOIC and TSSOP packages.
It is specified for operation over the industrial temperature range.

PRODUCT HIGHLIGHTS

1. The AD9754 is a member of the wideband TxDAC high per­formance product family that provides an upward or downward
component selection path based on resolution (8 to 14 bits),
performance and cost. The entire family of TxDACs is avail­able in industry standard pinouts.

2. Manufactured on a CMOS process, the AD9754 uses a
proprietary switching technique that enhances dynamic per­formance beyond that previously attainable by higher power/
cost bipolar or BiCMOS devices.

3. On-chip, edge-triggered input CMOS latches readily inter­face to +2.7 V to +5 V CMOS logic families. The AD9754
can support update rates up to 125 MSPS.

4. A flexible single-supply operating range of +4.5 V to +5.5 V,
and a wide full-scale current adjustment span of 2 mA to
20 mA, allows the AD9754 to operate at reduced power levels.

5. The current output(s) of the AD9754 can be easily config­ured for various single-ended or differential circuit topologies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106,U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

AD9754–SPECIFICATIONS

(T

to T

DC SPECIFICATIONS

MIN

, AVDD = +5 V, DVDD = +5 V, I

MAX

Parameter Min Typ Max Units

RESOLUTION 14 Bits

DC ACCURACY

1

Integral Linearity Error (INL)

= +25°C –3.0 ±1.5 +3.0 LSB

T

A

Differential Nonlinearity (DNL)

T

= +25°C –2.0 ±0.75 +2.0 LSB

A

ANALOG OUTPUT

Offset Error –0.02 +0.02 % of FSR
Gain Error
Gain Error
Full-Scale Output Current

(Without Internal Reference) –2 ±0.5 +2 % of FSR
(With Internal Reference) –5 ±1.5 +5 % of FSR

2

2.0 20.0 mA

Output Compliance Range –1.0 1.25 V

Output Resistance 100 kΩ

Output Capacitance 5 pF

REFERENCE OUTPUT

Reference Voltage 1.14 1.20 1.26 V
Reference Output Current

3

REFERENCE INPUT

Input Compliance Range 0.1 1.25 V

Reference Input Resistance 1 MΩ

Small Signal Bandwidth 0.5 MHz

TEMPERATURE COEFFICIENTS

Offset Drift 0 ppm of FSR/°C

Gain Drift
Gain Drift

(Without Internal Reference) ±50 ppm of FSR/°C
(With Internal Reference) ±100 ppm of FSR/°C

Reference Voltage Drift ±50 ppm/°C

POWER SUPPLY

Supply Voltages

AVDD 4.5 5.0 5.5 V

DVDD 2.7 5.0 5.5 V
Analog Supply Current (I
Digital Supply Current (I
Supply Current Sleep Mode (I
Power Dissipation

5

(5 V, I

Power Supply Rejection Ratio

4

)

AVDD

5

)

DVDD

OUTFS

6

)

AVDD

= 20 mA) 185 220 mW

7

—AVDD –0.4 +0.4 % of FSR/V

Power Supply Rejection Ratio7—DVDD –0.025 +0.025 % of FSR/V

OPERATING RANGE –40 +85 °C

NOTES

1

Measured at IOUTA, driving a virtual ground.

2

Nominal full-scale current, I

3

Use an external buffer amplifier to drive any external load.

4

Requires +5 V supply.

5

Measured at f

6

Logic level for SLEEP pin must be referenced to AVDD. Min VIH = 3.5 V.

7

±5% Power supply variation.

Specifications subject to change without notice.

= 25 MSPS and I

CLOCK

, is 32 × the I

OUTFS

current.

REF

= static full scale (20 mA).

OUT

= 20 mA, unless otherwise noted)

OUTFS

100 nA

34 39 mA

3.0 5 mA

4.0 8 mA

–2–

REV. A

AD9754

(T

to T

, AVDD = +5 V, DVDD = +5 V, I

MAX

DYNAMIC SPECIFICATIONS

MIN

50 ⍀ Doubly Terminated, unless otherwise noted)

Parameter Min Typ Max Units

DYNAMIC PERFORMANCE

Maximum Output Update Rate (f
Output Settling Time (t
Output Propagation Delay (t

) (to 0.1%)

ST

)1ns

PD

Glitch Impulse 5 pV-s
Output Rise Time (10% to 90%)
Output Fall Time (10% to 90%)
Output Noise (I
Output Noise (I

= 20 mA) 50 pA/√Hz

OUTFS

= 2 mA) 30 pA/√Hz

OUTFS

) 125 MSPS

CLOCK

1

1

1

AC LINEARITY

Spurious-Free Dynamic Range to Nyquist

f

= 25 MSPS; f

CLOCK

= 1.00 MHz

OUT

0 dBFS Output

= +25°C 75 86 dBc

T

A

–6 dBFS Output 86 dBc
–12 dBFS Output 78 dBc

= 50 MSPS; f

f

CLOCK

= 50 MSPS; f

f

CLOCK

= 50 MSPS; f

f

CLOCK

= 50 MSPS; f

f

CLOCK

= 100 MSPS; f

f

CLOCK

= 1.00 MHz 82 dBc

OUT

= 2.51 MHz 81 dBc

OUT

= 5.02 MHz 77 dBc

OUT

= 20.2 MHz 63 dBc

OUT

= 10 MHz 68 73 dBc

OUT

Spurious-Free Dynamic Range within a Window

= 25 MSPS; f

f

CLOCK

= 50 MSPS; f

f

CLOCK

= 100 MSPS; f

f

CLOCK

= 1.00 MHz; 2 MHz Span 84 93 dBc

OUT

= 5.02 MHz; 2 MHz Span 86 dBc

OUT

= 5.04 MHz; 4 MHz Span 86 dBc

OUT

Total Harmonic Distortion

= 25 MSPS; f

f

CLOCK

= +25°C –83 –75 dBc

T

A

= 50 MHz; f

f

CLOCK

= 100 MHz; f

f

CLOCK

= 1.00 MHz

OUT

= 2.00 MHz –78 dBc

OUT

= 2.00 MHz –78 dBc

OUT

Multitone Power Ratio (8 Tones at 110 kHz Spacing)

= 20 MSPS; f

f

CLOCK

= 2.00 MHz to 2.99 MHz

OUT

0 dBFS Output 85 dBc
–6 dBFS Output 84 dBc
–12 dBFS Output 87 dBc
–18 dBFS Output 88 dBc

NOTES

1

Measured single-ended into 50 Ω load.

Specifications subject to change without notice.

= 20 mA, Differential Transformer Coupled Output,

OUTFS

35 ns

2.5 ns

2.5 ns

REV. A

–3–

AD9754

WARNING!

ESD SENSITIVE DEVICE

(T

to T

DIGITAL SPECIFICATIONS

MIN

, AVDD = +5 V, DVDD = +5 V, I

MAX

Parameter Min Typ Max Units

DIGITAL INPUTS

Logic “1” Voltage @ DVDD = +5 V
Logic “1” Voltage @ DVDD = +3 V 2.1 3 V
Logic “0” Voltage @ DVDD = +5 V

1

1

3.5 5 V

Logic “0” Voltage @ DVDD = +3 V 0 0.9 V

Logic “1” Current –10 +10 µA
Logic “0” Current –10 +10 µA

Input Capacitance 5 pF
Input Setup Time (t
Input Hold Time (t
Latch Pulsewidth (t

NOTES

1

When DVDD = +5 V and Logic 1 voltage ≈3.5 V and Logic 0 voltage ≈1.3 V, IVDD can increase by up to 10 mA depending on f

Specifications subject to change without notice.

) 2.0 ns

S

) 1.5 ns

H

) 3.5 ns

LPW

DB0–DB11

t

S

CLOCK

IOUTA

OR

IOUTB

t

PD

0.1%

t

LPW

t

ST

= 20 mA unless otherwise noted)

OUTFS

0 1.3 V

t

H

0.1%

CLOCK

.

Figure 1. Timing Diagram

ABSOLUTE MAXIMUM RATINGS*

With

Parameter Respect to Min Max Units

AVDD ACOM –0.3 +6.5 V
DVDD DCOM –0.3 +6.5 V
ACOM DCOM –0.3 +0.3 V
AVDD DVDD –6.5 +6.5 V
CLOCK, SLEEP DCOM –0.3 DVDD + 0.3 V

Model Range Descriptions Options*

AD9754AR –40°C to +85°C 28-Lead 300 Mil SOIC R-28
AD9754ARU –40°C to +85°C 28-Lead TSSOP RU-28

AD9754-EB Evaluation Board

*R = Small Outline IC; RU = Thin Shrink Small Outline Package.

Temperature Package Package

Digital Inputs DCOM –0.3 DVDD + 0.3 V
IOUTA, IOUTB ACOM –1.0 AVDD + 0.3 V
ICOMP ACOM –0.3 AVDD + 0.3 V
REFIO, FSADJ ACOM –0.3 AVDD + 0.3 V
REFLO ACOM –0.3 AVDD +0.3 V

Junction Temperature +150 °C
Storage Temperature –65 +150 °C

Lead Temperature

(10 sec) +300 °C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.

THERMAL CHARACTERISTICS
Thermal Resistance

28-Lead 300 Mil SOIC

= 71.4°C/W

θ

JA

= 23°C/W

θ

JC

28-Lead TSSOP

= 97.9°C/W

θ

JA

= 14.0°C/W

θ

JC

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9754 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–4–

ORDERING GUIDE

REV. A

PIN CONFIGURATION

AD9754

(MSB) DB13

DB12
DB11
DB10

DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1

(LSB) DB0

1
2

3
4

5

AD9754

6

TOP VIEW

(Not to Scale)

7
8

9
10
11

12
13

14
NC = NO CONNECT

28
27

26
25

24
23

22
21

20
19
18

17
16

15

CLOCK
DVDD
DCOM
NC
AVDD
ICOMP
IOUTA
IOUTB
ACOM
NC
FS ADJ
REFIO
REFLO
SLEEP

PIN FUNCTION DESCRIPTIONS

Pin No. Name Description

1 DB13 Most Significant Data Bit (MSB).
2–13 DB12–DB1 Data Bits 1–12.
14 DB0 Least Significant Data Bit (LSB).
15 SLEEP Power-Down Control Input. Active High. Contains active pull-down circuit; it may be left unterminated if

not used.
16 REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference.
17 REFIO Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to

AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM).

Requires 0.1 µF capacitor to ACOM when internal reference activated.

18 FS ADJ Full-Scale Current Output Adjust.
19, 25 NC No Connect.
20 ACOM Analog Common.
21 IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s.
22 IOUTA DAC Current Output. Full-scale current when all data bits are 1s.

23 ICOMP Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 µF capacitor.

24 AVDD Analog Supply Voltage (+4.5 V to +5.5 V).
26 DCOM Digital Common.
27 DVDD Digital Supply Voltage (+2.7 V to +5.5 V).
28 CLOCK Clock Input. Data latched on positive edge of clock.

REV. A

–5–

AD9754

DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)

Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.

Differential Nonlinearity (or DNL)

DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input
code.

Offset Error

The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when
the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.

Gain Error

The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.

Output Compliance Range

The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.

Temperature Drift

Temperature drift is specified as the maximum change from the

ambient (+25°C) value to the value at either T

MIN

or T

MAX

. For

offset and gain drift, the drift is reported in ppm of full-scale

range (FSR) per °C. For reference drift, the drift is reported
in ppm per °C.

Power Supply Rejection

The maximum change in the full-scale output as the supplies
are varied over a specified range.

Settling Time

The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.

Glitch Impulse

Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.

Spurious-Free Dynamic Range

The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.

Total Harmonic Distortion

THD is the ratio of the sum of the rms value of the first six
harmonic components to the rms value of the measured output
signal. It is expressed as a percentage or in decibels (dB).

Multitone Power Ratio

The spurious-free dynamic range for an output containing mul­tiple carrier tones of equal amplitude. It is measured as the
difference between the rms amplitude of a carrier tone to the
peak spurious signal in the region of a removed tone.

DVDD

DCOM

0.1mF

R

SET

2kV

50V

RETIMED

CLOCK

OUTPUT*

LECROY 9210

PULSE GENERATOR

+5V

+5V

REFIO

FS ADJ

DVDD
DCOM

CLOCK

SLEEP

REFLO

+1.20V REF

SEGMENTED SWITCHES

FOR DB13–DB5

CLOCK

OUTPUT

150pF

LATCHES

DIGITAL

DATA

TEKTRONIX AWG-2021

w/OPTION 4

AVDD ACOM

PMOS

CURRENT SOURCE

ARRAY

LSB

SWITCHES

AD9754

Figure 2. Basic AC Characterization Test Setup

ICOMP

IOUTA
IOUTB

50V

0.1mF
MINI-CIRCUITS

T1-1T

100V

50V

20pF

20pF

* AWG2021 CLOCK RETIMED
SUCH THAT DIGITAL DATA
TRANSITIONS ON FALLING EDGE
OF 50% DUTY CYCLE CLOCK.

TO HP3589A
SPECTRUM/
NETWORK
ANALYZER
50V INPUT

–6–

REV. A

Typical AC Characterization Curves

FREQUENCY – MHz

SFDR – dB

90

95

02

46810

80
75
70

60
55

65

0dBFS

–6dBFS

–12dBFS

50
45

85

80

10mA FS

f

OUT

– MHz

SFDR – dBc

90

40

0

212

46810

60

50

70

20mA FS

5mA FS

f

CLOCK

– MSPS

SNR– dB

85

60

0 40 14060 80 100 120

80

70

75

65

20

20mA FS

5mA FS

10mA FS

(AVDD = +5 V, DVDD = +3 V, I
otherwise noted)

= 20 mA, 50 ⍀ Doubly Terminated Load, Differential Output, TA = +25ⴗC, SFDR up to Nyquist, unless

OUTFS

AD9754

90

5MSPS

80

70

60

SFDR – dB

50

40

0.1 100110

Figure 3. SFDR vs. f

90

80

–6dBFS

70

60

SFDR – dBc

50

25MSPS

f

– MHz

OUT

65MSPS

50MSPS

@ 0 dBFS

OUT

–12dBFS

0dBFS

125MSPS

90
85
80
75
70
65
60

SFDR – dB

55
50
45

40

0.0 2.00.4 0.8 1.2 1.6

Figure 4. SFDR vs. f

90

80

70

60

SFDR – dBc

50

0dBFS

–12dBFS

0dBFS

–12dBFS

–6dBFS

FREQUENCY – MHz

OUT

–6dBFS

@ 5 MSPS

Figure 5. SFDR vs. f

@ 25 MSPS

OUT

40

05 30

Figure 6. SFDR vs. f

90
85
80

75
70

65
60

SFDR – dB

55
50

45
40

–30 –25 0

Figure 9. Single-Tone SFDR vs. A
@ f

= f

OUT

REV. A

10 15 20

f

OUT

@5MSPS

–20 –15 –10 –5

A

OUT

/11

CLOCK

– MHz

@ 65 MSPS

OUT

455kHz

59.1MHz
@65MSPS

– dBFS

25

2.27MHz

@25MSPS

11.37MHz

@125MSPS

OUT

40

010 50

Figure 7. SFDR vs. f

100

90

80

70

SFDR – dB

60

50

40

–30 –25 0

20 30 40

f

OUT

@5MSPS

5MHz

@25MSPS

13MHz

@65MSPS

–20 –15 –10 –5

A

OUT

– MHz

OUT

1MHz

– dBFS

@125 MSPS

25MHz

@125MSPS

Figure 10. Single-Tone SFDR vs.
A

@ f

OUT

OUT

= f

CLOCK

/5

–7–

60

Figure 8. SFDR vs. f
I

@ 25 MSPS and 0 dBFS

OUTFS

Figure 11. SNR vs. f
@ f

= 2 MHz and 0 dBFS

OUT

OUT

CLOCK

and

and I

OUTFS

AD9754

1.0

0.5

0

–0.5

ERROR – LSB

–1.0

–1.5

–2.0

0

4k 8k 12k

CODE

Figure 12. Typical INL

16k

1.0

0.5

0

ERROR – LSB

–0.5

–1.0

4k 8k 12k

0

CODE

Figure 13. Typical DNL

16k

90

80

70

SFDR – dBc

60

50

–55 –5 95

Figure 14. SFDR vs. Temperature @
125 MSPS, 0 dBFS

0
–10
–20
–30
–40
–50
–60
–70
–80

SINGLE AMPLITUDE – dBm

–90

–100

030

f

= 65MSPS

CLOCK

f

= 6.25MHz

OUT1

f

= 6.75MHz

OUT2

f

= 7.25MHz

OUT3

f

= 7.75MHz

OUT4

SFDR > 70dBc
AMPLITUDE = 0dBFS

FREQUENCY – MHz

252015105

Figure 15. Four-Tone SFDR

f

OUT

f

= 10MHz

OUT

f

OUT

f

= 40MHz

OUT

TEMPERATURE – C

= 4MHz

= 29MHz

45

–8–

REV. A