Analog Devices AD9752 Datasheet

12-Bit, 125 MSPS High Performance

a

FEATURES
High Performance Member of Pin-Compatible

TxDAC Product Family
125 MSPS Update Rate
12-Bit Resolution
Excellent Spurious Free Dynamic Range Performance
SFDR to Nyquist @ 5 MHz Output: 79 dBc
Differential Current Outputs: 2 mA to 20 mA
Power Dissipation: 185 mW @ 5 V
Power-Down Mode: 20 mW @ 5 V
On-Chip 1.20 V Reference
CMOS-Compatible +2.7 V to +5.5 V Digital Interface
Package: 28-Lead SOIC and TSSOP
Edge-Triggered Latches

APPLICATIONS
Wideband Communication Transmit Channel:

Direct IF

Basestations

Wireless Local Loop

Digital Radio Link
Direct Digital Synthesis (DDS)
Instrumentation

PRODUCT DESCRIPTION

The AD9752 is a 12-bit resolution, wideband, second generation
member of the TxDAC series of high performance, low power
CMOS digital-to-analog-converters (DACs). The TxDAC
which consists of pin compatible 8-, 10-, 12-, and 14-bit DACs, is
specifically optimized for the transmit signal path of communica­tion systems. All of the devices share the same interface options,
small outline package and pinout, thus providing an upward or
downward component selection path based on performance,
resolution and cost. The AD9752 offers exceptional ac and dc
performance while supporting update rates up to 125 MSPS.

The AD9752’s flexible single-supply operating range of 4.5 V to

5.5 V and low power dissipation are well suited for portable and
low power applications. Its power dissipation can be further
reduced to a mere 65 mW, without a significant degradation in
performance, by lowering the full-scale current output. Also, a
power-down mode reduces the standby power dissipation to
approximately 20 mW.

The AD9752 is manufactured on an advanced CMOS process.
A segmented current source architecture is combined with a
proprietary switching technique to reduce spurious components
and enhance dynamic performance. Edge-triggered input latches
and a 1.2 V temperature compensated bandgap reference have
been integrated to provide a complete monolithic DAC solution.
The digital inputs support +2.7 V to +5 V CMOS logic families.

TxDAC is a registered trademark of Analog Devices, Inc.
*Protected by U.S. Patents Numbers 5450084, 5568145, 5689257, 5612697 and

5703519. Other patents pending.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

family,

TxDAC® D/A Converter

AD9752*

FUNCTIONAL BLOCK DIAGRAM

+5V

R

SET

CLOCK

0.1mF

+5V

REFLO

+1.20V REF
REFIO
FS ADJ

DVDD
DCOM

CLOCK

SLEEP

DIGITAL DATA INPUTS (DB11–DB0)

150pF

SEGMENTED

SWITCHES

LATCHES

The AD9752 is a current-output DAC with a nominal full-scale

output current of 20 mA and > 100 kΩ output impedance.

Differential current outputs are provided to support single­ended or differential applications. Matching between the two
current outputs ensures enhanced dynamic performance in a
differential output configuration. The current outputs may be
tied directly to an output resistor to provide two complemen­tary, single-ended voltage outputs or fed directly into a trans­former. The output voltage compliance range is 1.25 V.

The on-chip reference and control amplifier are configured for
maximum accuracy and flexibility. The AD9752 can be driven
by the on-chip reference or by a variety of external reference
voltages. The internal control amplifier, which provides a wide
(>10:1) adjustment span, allows the AD9752 full-scale current
to be adjusted over a 2 mA to 20 mA range while maintaining
excellent dynamic performance. Thus, the AD9752 may oper­ate at reduced power levels or be adjusted over a 20 dB range to
provide additional gain ranging capabilities.

The AD9752 is available in 28-lead SOIC and TSSOP packages.
It is specified for operation over the industrial temperature range.

PRODUCT HIGHLIGHTS

1. The AD9752 is a member of the wideband TxDAC product
family that provides an upward or downward component selec­tion path based on resolution (8 to 14 bits), performance and
cost. The entire family of TxDACs is available in industry
standard pinouts.

2. Manufactured on a CMOS process, the AD9752 uses a
proprietary switching technique that enhances dynamic
performance beyond that previously attainable by higher
power/cost bipolar or BiCMOS devices.

3. On-chip, edge-triggered input CMOS latches interface readily
to +2.7 V to +5 V CMOS logic families. The AD9752 can
support update rates up to 125 MSPS.

4. A flexible single-supply operating range of 4.5 V to 5.5 V and
a wide full-scale current adjustment span of 2 mA to 20 mA
allow the AD9752 to operate at reduced power levels.

5. The current output(s) of the AD9752 can be easily config­ured for various single-ended or differential circuit topologies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

CURRENT

SOURCE

ARRAY

LSB

SWITCHES

AVDD ACOM

AD9752

ICOMP

IOUTA
IOUTB

0.1mF

AD9752–SPECIFICATIONS

DC SPECIFICATIONS

(T

to T

MIN

, AVDD = +5 V, DVDD = +5 V, I

MAX

= 20 mA, unless otherwise noted)

OUTFS

Parameter Min Typ Max Units

RESOLUTION 12 Bits

DC ACCURACY

1

Integral Linearity Error (INL)

T

= +25°C –1.5 ±0.5 +1.5 LSB

A

to T

T

MIN

MAX

–2.0 +2.0 LSB

Differential Nonlinearity (DNL)

T

= +25°C –0.75 ±0.25 +0.75 LSB

A

T

MIN

to T

MAX

–1.0 +1.0 LSB

ANALOG OUTPUT

Offset Error –0.02 +0.02 % of FSR
Gain Error
Gain Error
Full-Scale Output Current

(Without Internal Reference) –2 ±0.5 +2 % of FSR
(With Internal Reference) –5 ±1.5 +5 % of FSR

2

2.0 20.0 mA

Output Compliance Range –1.0 1.25 V

Output Resistance 100 kΩ

Output Capacitance 5 pF

REFERENCE OUTPUT

Reference Voltage 1.14 1.20 1.26 V
Reference Output Current

3

100 nA

REFERENCE INPUT

Input Compliance Range 0.1 1.25 V

Reference Input Resistance 1 MΩ

Small Signal Bandwidth 0.5 MHz

TEMPERATURE COEFFICIENTS

Offset Drift 0 ppm of FSR/°C

Gain Drift
Gain Drift

(Without Internal Reference) ±50 ppm of FSR/°C
(With Internal Reference) ±100 ppm of FSR/°C

Reference Voltage Drift ±50 ppm/°C

POWER SUPPLY

Supply Voltages

AVDD 4.5 5.0 5.5 V

DVDD 2.7 5.0 5.5 V
Analog Supply Current (I
Digital Supply Current (I
Supply Current Sleep Mode (I
Power Dissipation

5

(5 V, I

Power Supply Rejection Ratio

4

)

AVDD

5

)

DVDD

OUTFS

6

)

AVDD

= 20 mA) 185 220 mW

7

—AVDD –0.4 +0.4 % of FSR/V

34 39 mA
35mA
48mA

Power Supply Rejection Ratio7—DVDD –0.025 +0.025 % of FSR/V

OPERATING RANGE –40 +85 °C

NOTES

1

Measured at IOUTA, driving a virtual ground.

2

Nominal full-scale current, I

3

Use an external buffer amplifier to drive any external load.

4

Requires +5 V supply.

5

Measured at f

6

Logic level for SLEEP pin must be referenced to AVDD. Min VIH = 3.5 V.

7

±5% Power supply variation.

Specifications subject to change without notice.

= 25 MSPS and I

CLOCK

, is 32 × the I

OUTFS

current.

REF

= static full scale (20 mA).

OUT

–2–

REV. 0

AD9752

(T

to T

, AVDD = +5 V, DVDD = +5 V, I

MAX

DYNAMIC SPECIFICATIONS

MIN

50 ⍀ Doubly Terminated, unless otherwise noted)

Parameter Min Typ Max Units

DYNAMIC PERFORMANCE

Maximum Output Update Rate (f
Output Settling Time (t
Output Propagation Delay (t

) (to 0.1%)

ST

)1ns

PD

Glitch Impulse 5 pV-s
Output Rise Time (10% to 90%)
Output Fall Time (10% to 90%)
Output Noise (I
Output Noise (I

= 20 mA) 50 pA/√Hz

OUTFS

= 2 mA) 30 pA/√Hz

OUTFS

) 125 MSPS

CLOCK

1

1

1

AC LINEARITY

Spurious-Free Dynamic Range to Nyquist

f

= 25 MSPS; f

CLOCK

= 1.00 MHz

OUT

0 dBFS Output

= +25°C 75 84 dBc

T

A

–6 dBFS Output 76 dBc
–12 dBFS Output 81 dBc

= 50 MSPS; f

f

CLOCK

f

= 50 MSPS; f

CLOCK

f

= 50 MSPS; f

CLOCK

= 50 MSPS; f

f

CLOCK

f

= 50 MSPS; f

CLOCK

f

= 100 MSPS; f

CLOCK

= 100 MSPS; f

f

CLOCK

f

= 100 MSPS; f

CLOCK

= 100 MSPS; f

f

CLOCK

= 1.00 MHz 81 dBc

OUT

= 2.51 MHz 81 dBc

OUT

= 5.02 MHz 76 dBc

OUT

= 14.02 MHz 62 dBc

OUT

= 20.2 MHz 60 dBc

OUT

= 2.5 MHz 78 dBc

OUT

= 5 MHz 76 dBc

OUT

= 20 MHz 63 dBc

OUT

= 40 MHz 55 dBc

OUT

Spurious-Free Dynamic Range within a Window

f

= 25 MSPS; f

CLOCK

= 50 MSPS; f

f

CLOCK

f

= 100 MSPS; f

CLOCK

= 1.00 MHz 84 93 dBc

OUT

= 5.02 MHz; 2 MHz Span 86 dBc

OUT

= 5.04 MHz; 4 MHz Span 86 dBc

OUT

Total Harmonic Distortion

= 25 MSPS; f

f

CLOCK

T

= +25°C –82 –74 dBc

A

f

= 50 MHz; f

CLOCK

= 100 MHz; f

f

CLOCK

= 1.00 MHz

OUT

= 2.00 MHz –76 dBc

OUT

= 2.00 MHz –76 dBc

OUT

Multitone Power Ratio (8 Tones at 110 kHz Spacing)

f

= 20 MSPS; f

CLOCK

= 2.00 MHz to 2.99 MHz

OUT

0 dBFS Output 81 dBc
–6 dBFS Output 81 dBc
–12 dBFS Output 85 dBc
–18 dBFS Output 86 dBc

NOTES

1

Measured single ended into 50 Ω load.

Specifications subject to change without notice.

= 20 mA, Differential Transformer Coupled Output,

OUTFS

35 ns

2.5 ns

2.5 ns

REV. 0 –3–

AD9752

WARNING!

ESD SENSITIVE DEVICE

DIGITAL SPECIFICATIONS

(T

to T

MIN

, AVDD = +5 V, DVDD = +5 V, I

MAX

= 20 mA, unless otherwise noted)

OUTFS

Parameter Min Typ Max Units

DIGITAL INPUTS

Logic “1” Voltage @ DVDD = +5 V
Logic “1” Voltage @ DVDD = +3 V 2.1 3 V
Logic “0” Voltage @ DVDD = +5 V

1

1

3.5 5 V

0 1.3 V

Logic “0” Voltage @ DVDD = +3 V 0 0.9 V

Logic “1” Current –10 +10 µA
Logic “0” Current –10 +10 µA

Input Capacitance 5 pF
Input Setup Time (t
Input Hold Time (t
Latch Pulsewidth (t

NOTES

1

When DVDD = +5 V and Logic 1 voltage ≈3.5 V and Logic 0 voltage ≈1.3 V. IVDD can increase by up to 10 mA, depending on f

Specifications subject to change without notice.

) 2.0 ns

S

) 1.5 ns

H

) 3.5 ns

LPW

.

CLOCK

DB0–DB11

CLOCK

IOUTA

OR

IOUTB

t

S

t

PD

0.1%

t

H

t

LPW

t

ST

0.1%

Figure 1. Timing Diagram

ABSOLUTE MAXIMUM RATINGS*

With

Parameter Respect to Min Max Units

AVDD ACOM –0.3 +6.5 V
DVDD DCOM –0.3 +6.5 V
ACOM DCOM –0.3 +0.3 V
AVDD DVDD –6.5 +6.5 V
CLOCK, SLEEP DCOM –0.3 DVDD + 0.3 V
Digital Inputs DCOM –0.3 DVDD + 0.3 V
IOUTA, IOUTB ACOM –1.0 AVDD + 0.3 V
ICOMP ACOM –0.3 AVDD + 0.3 V
REFIO, FSADJ ACOM –0.3 AVDD + 0.3 V
REFLO ACOM –0.3 +0.3 V

Junction Temperature +150 °C
Storage Temperature –65 +150 °C

Lead Temperature

(10 sec) +300 °C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may effect device reliability.

Model Range Description Options*

AD9752AR –40°C to +85°C 28-Lead 300 Mil SOIC R-28
AD9752ARU –40°C to +85°C 28-Lead TSSOP RU-28

AD9752-EB Evaluation Board

*R = Small Outline IC; RU = Thin Shrink Small Outline Package.

THERMAL CHARACTERISTICS
Thermal Resistance

28-Lead 300 Mil SOIC

θ

= 71.4°C/W

JA

= 23°C/W

θ

JC

28-Lead TSSOP

θ

= 97.9°C/W

JA

= 14.0°C/W

θ

JC

ORDERING GUIDE

Temperature Package Package

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9752 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–4–

REV. 0

AD9752

14

13

12

11

17
16
15

20
19
18

10

9

8

1
2
3
4

7

6

5

TOP VIEW

(Not to Scale)

28
27
26
25
24
23
22
21

AD9752

NC = NO CONNECT

(MSB) DB11

DB10

DB9
DB8

DB7
DB6

DB5
DB4

DB3
DB2
DB1
DB0

NC
NC

CLOCK
DVDD
DCOM
NC
AVDD
ICOMP
IOUTA
IOUTB
ACOM
NC
FS ADJ
REFIO
REFLO
SLEEP

PIN CONFIGURATION

PIN FUNCTION DESCRIPTIONS

Pin No. Name Description

1 DB11 Most Significant Data Bit (MSB).

2–11 DB10–DB1 Data Bits 1–10.

12 DB0 Least Significant Data Bit (LSB).

13, 14,

19, 25 NC No Internal Connection.

15 SLEEP Power-Down Control Input. Active High. Contains active pull-down circuit, thus may be left unterminated

if not used.
16 REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference.
17 REFIO Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to

AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM).

Requires 0.1 µF capacitor to ACOM when internal reference activated.

18 FS ADJ Full-Scale Current Output Adjust.
19 NC No Connect.
20 ACOM Analog Common.
21 IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s.
22 IOUTA DAC Current Output. Full-scale current when all data bits are 1s.

23 ICOMP Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 µF capacitor.

24 AVDD Analog Supply Voltage (+4.5 V to +5.5 V).
26 DCOM Digital Common.
27 DVDD Digital Supply Voltage (+2.7 V to +5.5 V).

28 CLOCK Clock Input. Data latched on positive edge of clock.

REV. 0

–5–

AD9752

DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)

Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.

Differential Nonlinearity (or DNL)

DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.

Monotonicity

A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.

Offset Error

The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when
the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.

Gain Error

The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.

Output Compliance Range

The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown resulting in
nonlinear performance.

Temperature Drift

Temperature drift is specified as the maximum change from the

ambient (+25°C) value to the value at either T

MIN

or T

MAX

. For

offset and gain drift, the drift is reported in ppm of full-scale

range (FSR) per °C. For reference drift, the drift is reported
in ppm per °C.

Power Supply Rejection

The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.

Settling Time

The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.

Glitch Impulse

Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.

Spurious-Free Dynamic Range

The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.

Total Harmonic Distortion

THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal. It is
expressed as a percentage or in decibels (dB).

Multitone Power Ratio

The spurious-free dynamic range for an output containing mul­tiple carrier tones of equal amplitude. It is measured as the
difference between the rms amplitude of a carrier tone to the
peak spurious signal in the region of a removed tone.

DVDD

DCOM

R

SET

2kV

RETIMED

CLOCK

OUTPUT*

LECROY 9210

PULSE GENERATOR

0.1mF

+5V

50V

+5V

+1.20V REF

REFIO
FS ADJ

DVDD
DCOM

CLOCK

SLEEP

REFLO

CLOCK

OUTPUT

150pF

SEGMENTED SWITCHES

FOR DB11–DB3

LATCHES

DIGITAL

DATA

TEKTRONIX

AWG-2021

W/OPTION 4

AVDD ACOM

PMOS

CURRENT SOURCE

ARRAY

LSB

SWITCHES

AD9752

Figure 2. Basic AC Characterization Test Setup

ICOMP

IOUTA
IOUTB

50V

0.1mF
MINI-CIRCUITS

100V

50V

20pF

20pF

* AWG2021 CLOCK RETIMED
SUCH THAT DIGITAL DATA
TRANSITIONS ON FALLING EDGE
OF 50% DUTY CYCLE CLOCK.

T1-1T

TO HP3589A
SPECTRUM/
NETWORK
ANALYZER
50V INPUT

–6–

REV. 0

Typical AC Characterization Curves @ +5 V Supplies

(AVDD = +5 V, DVDD = +5 V, I

= 20 mA, 50 ⍀ Doubly Terminated Load, Differential Output, TA = +25ⴗC, SFDR up to Nyquist, unless otherwise noted)

OUTFS

AD9752

90

25MSPS

80

70

SFDR – dB

60

50

40

0

65MSPS

1 100

f

OUT

Figure 3. SFDR vs. f

90

80

70

60

SFDR – dBc

50

–6dBFS

0dBFS

50MSPS

– MHz

OUT

125MSPS

10

@ 0 dBFS

–12dBFS

90

80

70

SFDR – dB

60

50

40

0

–12dBFS

46810

214

f

OUT

Figure 4. SFDR vs. f

90

80

70

60

SFDR – dB

50

–6dBFS

0dBFS

–12dBFS

– MHz

@ 25 MSPS

OUT

–6dBFS

0dBFS

90

80

70

60

SFDR – dBc

50

40

12

05 25

Figure 5. SFDR vs. f

90

80

70

SFDR – dBc

60

20mA FS

0dBFS

5mA FS

–6dBFS

–12dBFS

10

f

OUT

10mA FS

15 20

– MHz

@ 50 MSPS

OUT

40

0

10 15 25

530

f

OUT

Figure 6. SFDR vs. f

90

2.27MHz@25MSPS

80

70

60

SFDR – dB

50

40

–30 –25

11.36MHz@125MSPS

–20 –15 –5

A

OUT

20

– MHz

@ 65 MSPS

OUT

4.55MHz@50MSPS

5.91MHz@65MSPS

–10

– dBFS

Figure 9. Single-Tone SFDR vs. A
@ f

OUT

= f

CLOCK

/11

0

OUT

40

0

10 60

20 30 50

f

OUT

Figure 7. SFDR vs. f

90

80

5MHz@25MSPS

70

SFDR – dB

60

50

25MHz@125MSPS

40

–30 –25

–20 –15 –5

A

OUT

– MHz

OUT

– dBFS

10MHz@50MSPS

40

@ 125 MSPS

13MHz@65MSPS

–10

Figure 10. Single-Tone SFDR vs.
A

@ f

OUT

OUT

= f

CLOCK

/5

50

0

212

Figure 8. SFDR vs. f
@ 25 MSPS and 0 dBFS

80

70

5mA FS

SNR – dB

60

50

0

0

20 120

Figure 11. SNR vs. f
@ f

= 2 MHz and 0 dBFS

OUT

– MHz

OUT

– MSPS

CLOCK

8

and I

20mA FS

80

and I

OUTFS

OUTFS

46 10

f

OUT

10mA FS

40 60 100

f

CLOCK

REV. 0

–7–