Analog Devices AD974 a Datasheet

4-Channel, 16-Bit, 200 kSPS

CONTROL LOGIC

&

CALIBRATION CIRCUITRY

PWRD

V1A
V1B

BIP

CAP

REF

V

DIGVANA

EXT/INT
DATACLK

R/C

CS

SYNC

DGND

BUSY

WR2

WR1

A1A0

AGND2AGND1

REF

BUFF

2.5V

REFERENCE

AD974

4 TO 1

MUX

+

LATCH

EN

V2A
V2B

V3A
V3B

V4A
V4B

SWITCHED

CAP ADC

SERIAL

INTERFACE

16

DATA

RESISTIVE
NETWORK

RESISTIVE
NETWORK

RESISTIVE
NETWORK

RESISTIVE
NETWORK

CLOCK

a

FEATURES
Fast 16-Bit ADC with 200 kSPS Throughput
Four Single-Ended Analog Input Channels
Single +5 V Supply Operation
Input Ranges: 0 V to +4 V, 0 V to +5 V and ⴞ10 V
120 mW Max Power Dissipation
Power-Down Mode 50 ␮W
Choice of External or Internal 2.5 V Reference
On-Chip Clock
Power-Down Mode

GENERAL DESCRIPTION

The AD974 is a four-channel, data acquisition system with a
serial interface. The part contains an input multiplexer, a high­speed 16-bit sampling ADC and a +2.5 V reference. All of this
operates from a single +5 V power supply that also has a power­down mode. The part will accommodate 0 V to +4 V, 0 V to

+5 V or ±10 V analog input ranges.

The interface is designed for an efficient transfer of data while
requiring a low number of interconnects.

The AD974 is comprehensively tested for ac parameters such as
SNR and THD, as well as the more traditional parameters of
offset, gain and linearity.

The AD974 is fabricated on Analog Devices’ BiCMOS process,
which has high performance bipolar devices along with CMOS
transistors.

The AD974 is available in 28-lead DIP, SOIC and SSOP
packages.

Data Acquisition System

AD974

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

1. The AD974 is a complete data acquisition system combining
a four-channel multiplexer, a 16-bit sampling ADC and a
+2.5 V reference on a single chip.

2. The part operates from a single +5 V supply and also has a
power-down feature.

3. Interfacing to the AD974 is simple with a low number of
interconnect signals.

4. The AD974 is comprehensively specified for ac parameters
such as SNR and THD, as well as dc parameters such as
linearity and offset and gain errors.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

AD974–SPECIFICATIONS

(–40ⴗC to +85ⴗC, fS = 200 kHz, V

DIG

= V

= +5 V, unless otherwise noted)

ANA

A Grade B Grade

Parameter Conditions Min Typ Max Min Typ Max Units

RESOLUTION 16 16 Bits

ANALOG INPUT

Voltage Range ±10 V, 0 V to +4 V, 0 V to +5 V (See Table I)

Impedance Channel On or Off (See Table I)
Sampling Capacitance 40 40 pF

THROUGHPUT SPEED

Complete Cycle

(Acquire and Convert) 5 5 µs

Throughput Rate 200 200 kHz

DC ACCURACY

Integral Linearity Error ±3 ±2.0 LSB

Differential Linearity Error –2 +3 –1 +1.75 LSB
No Missing Codes 15 16 Bits
Transition Noise
Full-Scale Error

2

3

Internal Reference ±0.5 ±0.25 %

1.0 1.0 LSB

Full-Scale Error Drift Internal Reference ±7 ±7 ppm/°C
Full-Scale Error Ext. REF = +2.5 V ±0.5 ±0.25 %
Full-Scale Error Drift Ext. REF = +2.5 V ±2 ±2 ppm/°C
Bipolar Zero Error Bipolar Range ±10 ±10 mV
Bipolar Zero Error Drift Bipolar Range ±2 ±2 ppm/°C
Unipolar Zero Error Unipolar Ranges ±10 ±10 mV
Unipolar Zero Error Drift Unipolar Ranges ±2 ±2 ppm/°C
Channel-to-Channel Matching ±0.1 ±0.05 % FSR

Recovery to Rated Accuracy

After Power-Down

4

2.2 µF to CAP 1 1 ms

Power Supply Sensitivity

V

= V

ANA

DIG

= V

D

AC ACCURACY

Spurious Free Dynamic Range f

V

= 5 V ± 5% ±8 ±8 LSB

D

= 20 kHz 90 96 dB

IN

5

Total Harmonic Distortion fIN = 20 kHz –90 –96 dB
Signal-to-(Noise+Distortion) f

= 20 kHz 83 85 dB

IN

–60 dB Input 27 28 dB
Signal-to-Noise f
Channel-to-Channel Isolation f
Full Power Bandwidth

6

= 20 kHz 83 85 dB

IN

= 20 kHz –110 –100 –110 –100 dB

IN

1 1 MHz

–3 dB Input Bandwidth 2.7 2.7 MHz

SAMPLING DYNAMICS

Aperture Delay 40 40 ns

Transient Response Full-Scale Step 1 1 µs

Overvoltage Recovery

7

150 150 ns

REFERENCE

Internal Reference Voltage 2.48 2.5 2.52 2.48 2.5 2.52 V

Internal Reference Source Current 1 1 µA

External Reference Voltage Range

for Specified Linearity 2.3 2.5 2.7 2.3 2.5 2.7 V

External Reference Current Drain Ext. REF = +2.5 V 100 100 µA

DIGITAL INPUTS

Logic Levels

V

IL

V

IH

I

IL

I

IH

–0.3 +0.8 –0.3 +0.8 V
+2.0 V

+ 0.3 +2.0 V

DIG

+ 0.3 V

DIG

±10 ±10 µA
±10 ±10 µA

1

REV. A–2–

AD974

A Grade B Grade

Parameter Conditions Min Typ Max Min Typ Max Units

DIGITAL OUTPUTS

Data Format Serial 16 Bits
Data Coding Straight Binary

I

V

OL

V

OH

Output Capacitance High-Z State 15 15 pF
Leakage Current High-Z State

POWER SUPPLIES

Specified Performance

V

DIG

V

ANA

I

DIG

I

ANA

Power Dissipation

PWRD LOW 120 120 mW

PWRD HIGH 50 50 µW

TEMPERATURE RANGE

Specified Performance T

NOTES

1

LSB means Least Significant Bit. With a ±10 V input, one LSB is 305 µV.

2

Typical rms noise at worst case transitions and temperatures.

3

Full-Scale Error is expressed as the % difference between the actual full-scale code transition voltage and the ideal full-scale transition voltage, and includes the effect
of offset error. For bipolar input, the Full-Scale Error is the worst case of either the –Full-Scale or +Full-Scale code transition voltage errors. For unipolar input
ranges, Full-Scale Error is with respect to the +Full-Scale code transition voltage.

4

External 2.5 V reference connected to REF.

5

All specifications in dB are referred to a full-scale ±10 V input.

6

Full-Power Bandwidth is defined as full-scale input frequency at which Signal-to-(Noise + Distortion) degrades to 60 dB, or 10 bits of accuracy.

7

Recovers to specified performance after a 2 × FS input overvoltage.

Specifications subject to change without notice.

= 1.6 mA +0.4 +0.4 V

SINK

I

= 500 µA+4 +4 V

SOURCE

V

= 0 V to V

OUT

DIG

±5 ±5 µA

+4.75 +5 +5.25 +4.75 +5 +5.25 V
+4.75 +5 +5.25 +4.75 +5 +5.25 V

4.5 4.5 mA
14 14 mA

MIN

to T

MAX

–40 +85 –40 +85 °C

TIMING SPECIFICATIONS

(fS = 200 kHz, V

DIG

= V

= +5 V, –40ⴗC to +85ⴗC)

ANA

Parameter Symbol Min Typ Max Units

Convert Pulsewidth t
R/C, CS to BUSY Delay t

BUSY LOW Time t
BUSY Delay after End of Conversion t

Aperture Delay t
Conversion Time t
Acquisition Time t
Throughput Time t
R/C Low to DATACLK Delay t
DATACLK Period t
DATA Valid Setup Time t
DATA Valid Hold Time t
EXT. DATACLK Period t
EXT. DATACLK HIGH t
EXT. DATACLK LOW t
R/C, CS to EXT. DATACLK Setup Time t
R/C to CS Setup Time t
EXT. DATACLK to SYNC Delay t
EXT. DATACLK to DATA Valid Delay t
CS to EXT. DATACLK Rising Edge Delay t
Previous DATA Valid after CS, R/C Low t
BUSY to EXT. DATACLK Setup Time t
Final EXT. DATACLK to BUSY Rising Edge t
A0, A1 to WR1, WR2 Setup Time t
A0, A1 to WR1, WR2 Hold Time t
WR1, WR2 Pulsewidth t

Specifications subject to change without notic e.

1

2

3

4

5

6

7

+ t

6

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

7

50 ns

100 ns

4.0 µs

50 ns
40 ns

3.8 4.0 µs

1.0 µs
5 µs

220 ns

220 ns
50 ns
20 ns
66 ns
20 ns
30 ns
20 t12 + 5 ns
10 ns
15 66 ns
25 66 ns
10 ns

3.5 µs

5ns

1.7 µs

10 ns
10 ns
50 ns

REV. A –3–

AD974

WARNING!

ESD SENSITIVE DEVICE

TOP VIEW

(Not to Scale)

28
27
26
25
24
23
22
21
20
19
18
17
16
15

1
2
3
4
5
6
7
8

9
10
11
12
13
14

AD974

DGND

EXT/INT

PWRD

V

DIG

R/C

AGND2

REF

AGND1

V3A
V3B
V4A

CAP

BIP

V4B

SYNC

DATACLK

DATA

WR2

WR1

CS

BUSY

V2B
V2A
V1B
V1A

A1

A0

V

ANA

TO OUTPUT

PIN

C

L

100pF

I

OL

+1.4V

I

OH

1.6mA

500mA

ABSOLUTE MAXIMUM RATINGS

1

Analog Inputs

VxA, VxB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V

CAP . . . . . . . . . . . . . . . . +V

+ 0.3 V to AGND2 – 0.3 V

ANA

REF . . . . . . . . . . . . . . . . . . . . Indefinite Short to AGND2,

Momentary Short to V

ANA

Ground Voltage Differences

DGND, AGND1, AGND2 . . . . . . . . . . . . . . . . . . . ±0.3 V

Supply␣ Voltages

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V

V

ANA

to V

V

DIG

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V

V

DIG

Digital Inputs . . . . . . . . . . . . . . . . . . . –0.3 V to V

Internal␣ Power␣ Dissipation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±7 V

ANA

2

DIG

+ 0.3 V

PDIP (N), SOIC (R), SSOP (RS) . . . . . . . . . . . . . 700 mW

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

Storage Temperature Range N, R . . . . . . . . –65°C to +150°C

Lead Temperature Range

(Soldering␣ 10␣ sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+300°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Specification is for device in free air:

28-Lead PDIP: θJA = 100°C/W, θJC = 31°C/W
28-Lead SOIC: θJA = 75°C/W, θJC = 24°C/W
28-Lead SSOP: θJA = 109°C/W, θJC = 39°C/W

PIN CONFIGURATION

SOIC, DIP AND SSOP

Figure 1. Load Circuit for Digital Interface Timing

ORDERING GUIDE

Temperature Package Package

Model Range Max INL Min S/(N+D) Description Options

AD974AN –40°C to +85°C ±3.0 LSB 83 dB 28-Lead Plastic DIP N-28B
AD974BN –40°C to +85°C ±2.0 LSB 85 dB 28-Lead Plastic DIP N-28B
AD974AR –40°C to +85°C ±3.0 LSB 83 dB 28-Lead SOIC R-28
AD974BR –40°C to +85°C ±2.0 LSB 85 dB 28-Lead SOIC R-28
AD974ARS –40°C to +85°C ±3.0 LSB 83 dB 28-Lead SSOP RS-28
AD974BRS –40°C to +85°C ±2.0 LSB 85 dB 28-Lead SSOP RS-28

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD974 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–4–

REV. A

AD974

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Description

1 AGND1 Analog Ground. Used as the ground reference point for the REF pin.
2–5, 25–28 VxA, VxB Analog Input. Refer to Table I for input range configuration.
6 BIP Bipolar Offset. Connect VxA inputs to provide Bipolar input range.

7 CAP Reference Buffer Output. Connect a 2.2 µF tantalum capacitor between CAP and Analog

Ground.

8 REF Reference Input/Output. The internal +2.5 V reference is available at this pin. Alternatively an

external reference can be used to override the internal reference. In either case, connect a 2.2 µF

tantalum capacitor between REF and Analog Ground.

9 AGND2 Analog Ground.
10 R/C Read/Convert Input. Used to control the conversion and read modes. With CS LOW, a falling

edge on R/C holds the analog input signal internally and starts a conversion; a rising edge enables

the transmission of the conversion result.
11 V
12 PWRD Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions

13 EXT/INT Digital select input for choosing the internal or an external data clock. With EXT/INT tied LOW,

14 DGND Digital Ground.
15 SYNC Digital output frame synchronization for use with an external data clock (EXT/INT = Logic

16 DATACLK Serial data clock input or output, dependent upon the logic state of the EXT/INT pin. When

17 DATA The serial data output is synchronized to DATACLK. Conversion results are stored in an on-

18, 19 WR1, WR2 Multiplexer Write Inputs. These inputs are internally ORed to generate the mux latch inputs.

20 CS Chip Select Input. With R/C LOW, a falling edge on CS will initiate a conversion. With R/C

21 BUSY Busy Output. Goes LOW when a conversion is started, and remains LOW until the conversion is

22, 23 A1, A0 Address multiplexer inputs latched with the WR1, WR2 inputs.

DIG

Digital Power Supply. Nominally +5 V.

are inhibited. The conversion result from the previous conversion is stored in the onboard shift

register.

after initiating a conversion, 16 DATACLK pulses transmit the previous conversion result as

shown in Figure 3. With EXT/INT set to a Logic HIGH, output data is synchronized to an

external clock signal connected to the DATACLK input. Data is output as indicated in Figure 4

through Figure 9.

HIGH). When a read sequence is initiated, a pulse one DATACLK period wide is output

synchronous to the external data clock.

using the internal data clock (EXT/INT = Logic LOW), a conversion start sequence will initiate

transmission of 16 DATACLK periods. Output data is synchronous to this clock and is valid on

both its rising and falling edges (Figure 3). When using an external data clock (EXT/INT = Logic

HIGH), the CS and R/C signals control how conversion data is accessed.

chip register. The AD974 provides the conversion result, MSB first, from its internal shift regis-

ter. When using the internal data clock (EXT/INT = Logic LOW), DATA is valid on both the

rising and falling edges of DATACLK. Using an external data clock (EXT/INT = Logic HIGH)

allows previous conversion data to be accessed during a conversion (Figures 5, 7 and 9) or the

conversion result can be accessed after the completion of a conversion (Figures 4, 6 and 8).

The latch is transparent when WR1 and WR2 are tied low.

HIGH, a falling edge on CS will enable the serial data output sequence.

completed and the data is latched into the on-chip shift register.

24 V

REV. A

ANA

A1 A0 Data Available from Channel

00AIN 1
01AIN 2
10AIN 3
11AIN 4

Analog Power Supply. Nominally +5 V.

–5–

AD974

DEFINITION OF SPECIFICATIONS

INTEGRAL NONLINEARITY ERROR (INL)

Linearity error refers to the deviation of each individual code
from a line drawn from “negative full scale” through “positive
full scale.” The point used as “negative full scale” occurs 1/2 LSB
before the first code transition. “Positive full scale” is defined as
a level 1 1/2 LSB beyond the last code transition. The deviation
is measured from the middle of each particular code to the true
straight line.

DIFFERENTIAL NONLINEARITY ERROR (DNL)

In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.

FULL-SCALE ERROR

The last + transition (from 011 . . . 10 to 011 . . . 11) should
occur for an analog voltage 1 1/2 LSB below the nominal full

scale (9.9995422 V for a ±10 V range). The full-scale error is

the deviation of the actual level of the last transition from the
ideal level.

BIPOLAR ZERO ERROR

Bipolar zero error is the difference between the ideal midscale
input voltage (0 V) and the actual voltage producing the mid­scale output code.

UNIPOLAR ZERO ERROR

In unipolar mode, the first transition should occur at a level
1/2 LSB above analog ground. Unipolar zero error is the devia­tion of the actual transition from that point.

SPURIOUS FREE DYNAMIC RANGE

The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.

TOTAL HARMONIC DISTORTION (THD)

THD is the ratio of the rms sum of the first six harmonic com­ponents to the rms value of a full-scale input signal and is ex­pressed in decibels.

SIGNAL TO (NOISE AND DISTORTION) (S/[N+D]) RATIO

S/(N+D) is the ratio of the rms value of the measured input
signal to the rms sum of all other spectral components below
the Nyquist frequency, including harmonics but excluding dc.
The value for S/(N+D) is expressed in decibels.

FULL POWER BANDWIDTH

The full power bandwidth is defined as the full-scale input fre­quency at which the S/(N+D) degrades to 60 dB, 10 bits of
accuracy.

APERTURE DELAY

Aperture delay is a measure of the acquisition performance, and
is measured from the falling edge of the R/C input to when the
input signal is held for a conversion.

TRANSIENT RESPONSE

The time required for the AD974 to achieve its rated accuracy
after a full-scale step function is applied to its input.

OVERVOLTAGE RECOVERY

The time required for the ADC to recover to full accuracy after
an analog input signal 150% of full-scale is reduced to 50% of
the full-scale value.

–6–

REV. A