ANALOG DEVICES AD9748 Service Manual
8-Bit, 210 MSPS TxDAC® D/A Converter
FEATURES
High performance member of pin-compatible
TxDAC product family
Linearity
0.1 LSB DNL
0.1 LSB INL
Twos complement or straight binary data format
Differential current outputs: 2 mA to 20 mA
Power dissipation: 135 mW @ 3.3 V
Power-down mode: 15 mW @ 3.3 V
On-chip 1.20 V reference
CMOS-compatible digital interface
32-lead LFCSP
Edge-triggered latches
Fast settling: 11 ns to 0.1% full-scale
GENERAL DESCRIPTION
The AD97481 is an 8-bit resolution, wideband, third generation
member of the TxDAC series of high performance, low power
CMOS digital-to-analog converters (DACs). The TxDAC
family, consisting of pin-compatible 8-, 10-, 12-, and 14-bit
DACs, is specifically optimized for the transmit signal path of
communication systems. All of the devices share the same
interface options, small outline package, and pinout, providing
an upward or downward component selection path based on
performance, resolution, and cost. The AD9748 offers
exceptional ac and dc performance while supporting update
rates up to 210 MSPS.
The AD9748’s low power dissipation makes it well suited for
portable and low power applications. Its power dissipation can
be further reduced to 60 mW with a slight degradation in
performance by lowering the full-scale current output. In
addition, a power-down mode reduces the standby power
dissipation to approximately 15 mW. A segmented current
source architecture is combined with a proprietary switching
technique to reduce spurious components and enhance
dynamic performance.
AD9748
APPLICATIONS
Communications
Direct digital synthesis (DSS)
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
3.3V
150pF
SEGMENTED
SWITCHES
Figure 1.
LATCHES
R
SET
CLK+
CLK–
0.1μF
REFIO
FS ADJ
DVDD
3.3V
DCOM
3.3V CLKVDD
CLKCOM
SLEEP
1.2V REF
DIGITAL DATA INPUTS (DB7–DB0)
Edge-triggered input latches and a 1.2 V temperaturecompensated band gap reference have been integrated to
provide a complete monolithic DAC solution. The digital inputs
support 3 V CMOS logic families.
PRODUCT HIGHLIGHTS
1. 32-lead LFCSP.
2. The AD9748 is the 8-bit member of the pin-compatible
TxDAC family, which offers excellent INL and DNL
performance.
3. Differential or single-ended clock input (LVPECL or
CMOS), supports 210 MSPS conversion rate.
4. Data input supports twos complement or straight binary
data coding.
5. Low power: Complete CMOS DAC function operates on
135 mW from a 2.7 V to 3.6 V single supply. The DAC fullscale current can be reduced for lower power operation,
and a sleep mode is provided for low power idle periods.
6. On-chip voltage reference: The AD9748 includes a 1.2 V
temperature-compensated band gap voltage reference.
1
Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519.
AVDD ACOM
CURRENT
SOURCE
ARRAY
LSB
SWITCHES
AD9748
IOUTA
IOUTB
MODE
CMODE
03211-001
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
AD9748
TABLE OF CONTENTS
Features .............................................................................................. 1
Applying the AD9748 ................................................................ 15
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
Dynamic Specifications ............................................................... 4
Digital Specifications ................................................................... 5
Absolute Maximum Ratings............................................................ 6
Thermal Characteristics .............................................................. 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Te r mi n ol o g y ...................................................................................... 8
Typical Performance Characteristics ............................................. 9
Functional Description ..................................................................11
Reference Operation ..................................................................11
Reference Control Amplifier .................................................... 11
DAC Transfer Function ............................................................. 12
Analog Outputs........................................................................... 12
Digital Inputs ..............................................................................13
Clock Input.................................................................................. 13
DAC Timing................................................................................ 14
Power Dissipation....................................................................... 14
Differential Coupling Using a Transformer............................... 15
Differential Coupling Using an Op Amp................................ 16
Single-Ended, Unbuffered Voltage Output............................. 16
Single-Ended, Buffered Voltage Output Configuration........ 16
Power and Grounding Considerations, Power Supply
Rejection...................................................................................... 17
Evaluation Board ............................................................................ 18
General Description................................................................... 18
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
12/05—Rev. 0 to Rev. A
Updated Format.................................................................. Universal
Changes to General Description and Product Highlights...........1
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................4
Changes to Table 4.............................................................................6
Inserted Figure 7; Renumbered Sequentially.................................9
Changes to Figure 8 and Figure 9....................................................9
Changes to Functional Description, Reference Operation, and
Reference Control Amplifier Sections......................................... 11
Inserted Figure 16; Renumbered Sequentially ........................... 11
Changes to DAC Transfer Function Section............................... 12
Changes to Digital Inputs Section................................................ 13
Changes to Figure 22, Figure 23, and Figure 24......................... 14
Changes to Figure 25...................................................................... 15
Changes to Figure 26, Figure 27, Figure 28, and Figure 29....... 16
Updated Outline Dimensions....................................................... 24
Changes to Ordering Guide.......................................................... 24
2/03—Revision 0: Initial Version
Rev. A | Page 2 of 24
AD9748
SPECIFICATIONS
DC SPECIFICATIONS
T
to T
MIN
Table 1.
Parameter Min Typ Max Unit
RESOLUTION 8 Bits
DC ACCURACY1
Integral Linearity Error (INL) ±0.25 ±0.1 +0.25 LSB
Differential Nonlinearity (DNL) ±0.25 ±0.1 +0.25 LSB
ANALOG OUTPUT
Offset Error −0.02 +0.02 % of FSR
Gain Error (Without Internal Reference) −0.5 ±0.1 +0.5 % of FSR
Gain Error (With Internal Reference) −0.5 ±0.1 +0.5 % of FSR
Full-Scale Output Current2 2.0 20.0 mA
Output Compliance Range −1.0 +1.25 V
Output Resistance 100 kΩ
Output Capacitance 5 pF
REFERENCE OUTPUT
Reference Voltage 1.14 1.20 1.26 V
Reference Output Current3 100 nA
REFERENCE INPUT
Input Compliance Range 0.1 1.25 V
Reference Input Resistance (External Reference) 7 kΩ
Small Signal Bandwidth 0.5 MHz
TEMPERATURE COEFFICIENTS
Offset Drift 0 ppm of FSR/°C
Gain Drift (Without Internal Reference) ±50 ppm of FSR/°C
Gain Drift (With Internal Reference) ±100 ppm of FSR/°C
Reference Voltage Drift ±50 ppm/°C
POWER SUPPLY
Supply Voltages
Analog Supply Current (I
Digital Supply Current (I
Clock Supply Current (I
Supply Current Sleep Mode (I
Power Dissipation
Power Dissipation5 145 mW
Power Supply Rejection Ratio—AVDD6 −1 +1 % of FSR/V
Power Supply Rejection Ratio—DVDD
OPERATING RANGE −40 +85 °C
1
Measured at IOUTA, driving a virtual ground.
2
Nominal full-scale current, I
3
An external buffer amplifier with input bias current <100 nA should be used to drive any external load.
4
Measured at f
5
Measured as unbuffered voltage output with I
6
±5% power supply variation.
, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I
MAX
= 20 mA, unless otherwise noted.
OUTFS
AVDD 2.7 3.3 3.6 V
DVDD 2.7 3.3 3.6 V
CLKVDD 2.7 3.3 3.6 V
) 33 36 mA
AVDD
)4 8 9 mA
DVDD
) 5 7 mA
CLKVDD
) 5 6 mA
4
= 100 MSPS and f
CLOCK
AVDD
, is 32 times the I
OUTFS
OUT
= 1 MHz.
6
current.
REF
= 20 mA, 50 Ω R
OUTFS
at IOUTA and IOUTB, f
LOAD
135 145 mW
−0.04 +0.04 % of FSR/V
= 100 MSPS, and f
CLOCK
= 40 MHz.
OUT
Rev. A | Page 3 of 24
AD9748
DYNAMIC SPECIFICATIONS
T
to T
MIN
terminated, unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit
DYNAMIC PERFORMANCE
Maximum Output Update Rate (f
Output Settling Time (tST) (to 0.1%)1 11 ns
Output Propagation Delay (tPD) 1 ns
Glitch Impulse 5 pV-s
Output Rise Time (10% to 90%)
Output Fall Time (10% to 90%)
Output Noise (I
Output Noise (I
AC LINEARITY
Signal-to-Noise and Distortion Ratio
Total Harmonic Distortion
Spurious-Free Dynamic Range to Nyquist
1
Measured single-ended into 50 Ω load.
2
Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only.
, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I
MAX
= 20 mA, differential transformer coupled output, 50 Ω doubly
OUTFS
) 210 MSPS
CLOCK
f
= 50 MSPS; f
CLOCK
f
= 50 MSPS; f
CLOCK
f
= 100 MSPS; f
CLOCK
f
= 100 MSPS; f
CLOCK
f
= 165 MSPS; f
CLOCK
f
= 165 MSPS; f
CLOCK
f
= 210 MSPS; f
CLOCK
f
= 210 MSPS; f
CLOCK
f
= 25 MSPS; f
CLOCK
f
= 50 MSPS; f
CLOCK
f
= 100 MSPS; f
CLOCK
f
= 165 MSPS; f
CLOCK
f
= 210 MSPS; f
CLOCK
f
= 25 MSPS; f
CLOCK
1
1
= 20 mA)2 50 pA/√Hz
OUTFS
OUTFS
= 2 mA)
2
= 5 MHz 50 dB
OUT
= 19 MHz 48 dB
OUT
= 5 MHz 50 dB
OUT
= 39 MHz 46 dB
OUT
= 5 MHz 50 dB
OUT
= 49 MHz 47 dB
OUT
= 9 MHz 50 dB
OUT
= 68 MHz 46 dB
OUT
= 1 MHz −72 −61 dBc
OUT
= 12.5 MHz −65 dBc
OUT
= 25 MHz −60 dBc
OUT
= 41.3 MHz −58 dBc
OUT
= 68 MHz −65 dBc
OUT
= 1 MHz
OUT
2.5 ns
2.5 ns
30 pA/√Hz
0 dBFS Output 61 72 dBc
f
= 65 MSPS; f
CLOCK
f
= 65 MSPS; f
CLOCK
f
= 100 MSPS; f
CLOCK
f
= 100 MSPS; f
CLOCK
f
= 165 MSPS; f
CLOCK
f
= 165 MSPS; f
CLOCK
f
= 210 MSPS; f
CLOCK
f
= 210 MSPS; f
CLOCK
= 5 MHz 69 dBc
OUT
= 19 MHz 65 dBc
OUT
= 5 MHz 68 dBc
OUT
= 39 MHz 62 dBc
OUT
= 5 MHz 68 dBc
OUT
= 49 MHz 54 dBc
OUT
= 5 MHz 67 dBc
OUT
= 68 MHz 60 dBc
OUT
Rev. A | Page 4 of 24
AD9748
DIGITAL SPECIFICATIONS
T
to T
MIN
Table 3.
Parameter Min Typ Max Unit
DIGITAL INPUTS
Logic 1 Voltage 2.1 3 V
Logic 0 Voltage 0 0.9 V
Logic 1 Current −10 +10 μA
Logic 0 Current −10 +10 μA
Input Capacitance 5 pF
Input Setup Time (tS) 2.0 ns
Input Hold Time (tH) 1.5 ns
Latch Pulse Width (t
CLK INPUTS1
Input Voltage Range 0 3 V
Common-Mode Voltage 0.75 1.5 2.25 V
Differential Voltage 0.5 1.5 V
1
Applicable to CLK+ and CLK− inputs when configured for differential or PECL clock input mode.
, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I
MAX
) 1.5 ns
LPW
= 20 mA, unless otherwise noted.
OUTFS
DB0–DB7
CLOCK
IOUTA
OR
IOUTB
t
S
t
PD
0.1%
t
H
t
LPW
t
ST
0.1%
03211-002
Figure 2. Timing Diagram
Rev. A | Page 5 of 24
AD9748
ABSOLUTE MAXIMUM RATINGS
Table 4.
With
Respect
Parameter
AVDD ACOM −0.3 +3.9 V
DVDD DCOM −0.3 +3.9 V
CLKVDD CLKCOM −0.3 +3.9 V
ACOM DCOM −0.3 +0.3 V
ACOM CLKCOM −0.3 +0.3 V
DCOM CLKCOM −0.3 +0.3 V
AVDD DVDD −3.9 +3.9 V
AVDD CLKVDD −3.9 +3.9 V
DVDD CLKVDD −3.9 +3.9 V
CLK+, CLK−, SLEEP DCOM −0.3 DVDD + 0.3 V
Digital Inputs, MODE DCOM −0.3 DVDD + 0.3 V
IOUTA, IOUTB ACOM −1.0 AVDD + 0.3 V
REFIO, FS ADJ ACOM −0.3 AVDD + 0.3 V
CLK+, CLK−, MODE CLKCOM −0.3 CLKVDD + 0.3 V
Junction Temperature 150 °C
Storage Temperature
Range
Lead Temperature
(10 sec)
to
−65 +150 °C
300 °C
Min Max Unit
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum ratings for extended periods may effect
device reliability.
THERMAL CHARACTERISTICS
Thermal Resistance
32-Lead LFCSP
= 32.5°C/W
θ
JA
1
Thermal impedance measurements were taken on a 4-layer board in still air,
in accordance with EIA/JESD51-7.
1
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 6 of 24
AD9748
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
B6
D
DB2
DB3
31
32
DB7 (MSB)
DB4
DB5
DCOM
SLEEP
29
28
27
26
30
25
1DB1
PIN 1
2(LSB) DB0
INDICATOR
3DVDD
4NC
5NC
6NC
7NC
8NC
AD9748
TOP VIEW
(Not to Scale)
9
10
M
NC
DCO
NC = NO CONNECT
11
12
13
14
CLK–
CLK+
CLKVDD
CLKCOM
15
CMODE
16
MODE
24 FS ADJ
23 REFIO
22 ACOM
21 IOUTA
20 IOUTB
19 ACOM
18 AVDD
17 AVDD
03211-003
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
27 DB7 (MSB) Most Significant Data Bit (MSB).
28 to 32, 1 DB6 to DB1 Data Bits 6 to 1.
2 DB0 (LSB) Least Significant Data Bit (LSB).
3 DVDD Digital Supply Voltage (3.3 V).
4 to 9 NC No Internal Connection.
10, 26 DCOM Digital Common.
11 CLKVDD Clock Supply Voltage (3.3 V).
12 CLK+ Differential Clock Input.
13 CLK− Differential Clock Input.
14 CLKCOM Clock Common.
15 CMODE
Clock Mode Selection. Connect to CLKCOM for single-ended clock receiver (drive CLK+ and float
CLK–). Connect to CLKVDD for differential receiver. Float for PECL receiver (terminations on-chip).
16 MODE Selects Input Data Format. Connect to DCOM for straight binary, DVDD for twos complement.
17, 18 AVDD Analog Supply Voltage (3.3 V).
19, 22 ACOM Analog Common.
20 IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s.
21 IOUTA DAC Current Output. Full-scale current when all data bits are 1s.
23 REFIO Reference Input/Output. Requires 0.1 μF capacitor to ACOM.
24 FS ADJ Full-Scale Current Output Adjust.
25 SLEEP
Power-Down Control Input. Active high. Contains active pull-down circuit; it can be left unterminated
if not used.
Rev. A | Page 7 of 24
AD9748
TERMINOLOGY
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A DAC is monotonic if the output increases or remains constant
as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called the offset error. For IOUTA, 0 mA output is expected
when the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current output
DAC. Operation beyond the maximum compliance limits can
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Tem p er at u re Dr i ft
Temperature drift is specified as the maximum change from the
ambient (25°C) value to the value at either T
MIN
or T
. For offset
MAX
and gain drift, the drift is reported in ppm of full-scale range (FSR)
per °C. For reference drift, the drift is reported in ppm per °C.
3.3V
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified
bandwidth.
Total Harmonic Distortion (THD)
T
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal. It is
expressed as a percentage or in decibels (dB).
Multitone Power Ratio
The spurious-free dynamic range containing multiple carrier
tones of equal amplitude. It is measured as the difference
between the rms amplitude of a carrier tone to the peak
spurious signal in the region of a removed tone.
*AWG2021 CLOCK
RETIMED SO THAT
THE DIGITAL DATA
TRANSITIONS ON
FALLING EDGE OF
50% DUTY CYCLE
CLOCK.
DVDD
DCOM
RETIMED
CLOCK
OUTPUT*
R
SET
50Ω
LECROY 9210
PULSE GENERATOR
0.1μF
3.3V
CLK+
CLK–
3.3V
1.2V REF
REFIO
FS ADJ
DVDD
DCOM
CLKVDD
CLKCOM
SLEEP
CLOCK
OUTPUT
150pF
SEGMENTED
SWITCHES
LATCHES
DIGITAL DATA INPUTS (DB7–DB0)
DIGITAL
DATA
TEKTRONIX AWG-2021
WITH OPTION 4
AVDD ACOM
CURRENT
SOURCE
ARRAY
LSB
SWITCHES
AD9748
IOUTA
IOUTB
MODE
CMODE
50Ω
Figure 4. Basic AC Characterization Test Setup (SOIC/TSSOP Packages)
Rev. A | Page 8 of 24
20pF
50Ω
100Ω
20pF
MINI-CIRCUITS
T1-1T
ROHDE & SCHWARZ
FSEA30
SPECTRUM
ANALYZER
03211-004
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