Analog Devices AD9748 Datasheet
8-Bit, 165 MSPS
TxDAC® D/A Converter
FEATURES
High Performance Member of Pin Compatible
TxDAC Product Family
Linearity:
0.1 LSB DNL
0.1 LSB INL
Twos Complement or Straight Binary Data Format
Differential Current Outputs: 2 mA to 20 mA
SINAD @ 5 MHz Output: 50 dB
Power Dissipation: 135 mW @ 3.3 V
Power-Down Mode: 15 mW @ 3.3 V
On-Chip 1.20 V Reference
CMOS Compatible Digital Interface
32-Lead LFCSP
Edge-Triggered Latches
Fast Settling: 11 ns to 0.1% Full Scale
APPLICATIONS
Communications
Direct Digital Synthesis (DDS)
Instrumentation
GENERAL DESCRIPTION
The AD9748 is an 8-bit resolution, wideband, third generation
member of the TxDAC series of high performance, low power
CMOS digital-to-analog converters (DACs). The TxDAC family,
consisting of pin compatible 8-, 10-, 12-, and 14-bit DACs, is
specifically optimized for the transmit signal path of communication systems. All of the devices share the same interface options,
small outline package, and pinout, providing an upward or
downward component selection path based on performance,
resolution, and cost. The AD9748 offers exceptional ac and
dc performance while supporting update rates up to 165 MSPS.
The AD9748’s low power dissipation makes it well suited for
portable and low power applications. Its power dissipation can be
further reduced to a mere 60 mW with a slight degradation in
performance by lowering the full-scale current output. Also, a
power-down mode reduces the standby power dissipation to
approximately 15 mW. A segmented current source architecture
is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. Edge-triggered
AD9748
*
FUNCTIONAL BLOCK DIAGRAM
3.3V
AVDD ACOM
CURRENT
SOURCE
ARRAY
LSB
SWITCHES
AD9748
IOUTA
IOUTB
MODE
CMODE
R
SET
CLK
CLK
0.1F
3.3V
3.3V
+1.20V REF
REFIO
FS ADJ
DVDD
DCOM
CLKVDD
CLKCOM
SLEEP DIGITAL DATA INPUTS (DB7–DB0)
150pF
SEGMENTED
SWITCHES
LATCHES
input latches and a 1.2 V temperature compensated band gap
reference have been integrated to provide a complete monolithic
DAC solution. The digital inputs support 3 V CMOS logic families.
PRODUCT HIGHLIGHTS
1. 32-lead LFCSP package.
2. The AD9748 is the 8-bit member of the pin compatible TxDAC
family, which offers excellent INL and DNL performance.
3. Differential or single-ended clock input (LVPECL or CMOS),
supports 165 MSPS conversion rate.
4. Data input supports twos complement or straight binary data
coding.
5. Low power: Complete CMOS DAC function operates on
135 mW from a 2.7 V to 3.6 V single supply. The DAC
full-scale current can be reduced for lower power operation,
and a sleep mode is provided for low power idle periods.
6. On-chip voltage reference: The AD9748 includes a 1.2 V
temperature-compensated band gap voltage reference.
*Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
AD9748–SPECIFICATIONS
DC SPECIFICATIONS
(T
MIN to TMAX,
AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I
= 20 mA, unless otherwise noted.)
OUTFS
Parameter Min Typ Max Unit
RESOLUTION 8 Bits
DC ACCURACY
1
Integral Linearity Error (INL) ± 0.25 ± 0.1 ± 0.25 LSB
Differential Nonlinearity (DNL) ± 0.25 ± 0.1 ± 0.25 LSB
ANALOG OUTPUT
Offset Error –0.02 +0.02 % of FSR
Gain Error (Without Internal Reference) –0.5 ± 0.1 +0.5 % of FSR
Gain Error (With Internal Reference) –0.5 ± 0.1 +0.5 % of FSR
Full-Scale Output Current
2
2.0 20.0 mA
Output Compliance Range –1.0 +1.25 V
Output Resistance 100 kW
Output Capacitance 5 pF
REFERENCE OUTPUT
Reference Voltage 1.14 1.20 1.26 V
Reference Output Current
3
100 nA
REFERENCE INPUT
Input Compliance Range 0.1 1.25 V
Reference Input Resistance (External Reference) 1 MW
Small Signal Bandwidth 0.5 MHz
TEMPERATURE COEFFICIENTS
Offset Drift 0 ppm of FSR/∞C
Gain Drift (Without Internal Reference) ± 50 ppm of FSR/∞C
Gain Drift (With Internal Reference) ± 100 ppm of FSR/∞C
Reference Voltage Drift ± 50 ppm/∞C
POWER SUPPLY
Supply Voltages
AVDD 2.7 3.3 3.6 V
DVDD 2.7 3.3 3.6 V
CLKVDD 2.7 3.3 3.6 V
Analog Supply Current (I
Digital Supply Current (I
Clock Supply Current (I
Supply Current Sleep Mode (I
Power Dissipation
Power Dissipation
4
5
Power Supply Rejection Ratio—AVDD
Power Supply Rejection Ratio—DVDD
)3336mA
AVDD
4
)
DVDD
CLKDVDD
AVDD
)57mA
)56mA
89 mA
135 145 mW
6
6
–1+1% of FSR/V
–0.04 +0.04 % of FSR/V
145 mW
OPERATING RANGE –40 +85 ∞C
NOTES
1
Measured at IOUTA, driving a virtual ground.
2
Nominal full-scale current, I
3
An external buffer amplifier with an input bias current <100 nA should be used to drive any external load.
4
Measured at f
5
Measured as unbuffered voltage output with I
6
± 5% power supply variation.
Specifications subject to change without notice.
= 100 MSPS and f
CLOCK
, is 32 times the I
OUTFS
OUT
REF
= 1 MHz.
= 20 mA and 50 W R
OUTFS
current.
at IOUTA and IOUTB, f
LOAD
= 100 MSPS and f
CLOCK
= 40 MHz.
OUT
REV. 0–2–
AD9748
(T
to T
, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I
MAX
DYNAMIC SPECIFICATIONS
MIN
Single-Ended Output, 50 Doubly Terminated, unless otherwise noted.)
Parameter Min Typ Max Unit
DYNAMIC PERFORMANCE
Maximum Output Update Rate (f
Output Settling Time (t
Output Propagation Delay (t
) (to 0.1%)
ST
)1ns
PD
Glitch Impulse 5 pV-s
Output Rise Time (10% to 90%)
Output Fall Time (10% to 90%)
Output Noise (I
Output Noise (I
OUTFS
OUTFS
= 20 mA)
= 2 mA)
2
CLOCK
1
1
2
) 165 MSPS
1
11 ns
2.5 ns
2.5 ns
50 pA/÷Hz
30 pA/÷Hz
AC LINEARITY
Signal-to-Noise and Distortion Ratio
= 50 MSPS; f
f
CLOCK
= 50 MSPS; f
f
CLOCK
= 100 MSPS; f
f
CLOCK
f
= 100 MSPS; f
CLOCK
= 165 MSPS; f
f
CLOCK
= 165 MSPS; f
f
CLOCK
= 5 MHz 50 dB
OUT
= 19 MHz 47 dB
OUT
= 5 MHz 50 dB
OUT
= 39 MHz 46 dB
OUT
= 5 MHz 50 dB
OUT
= 49 MHz 47 dB
OUT
Total Harmonic Distortion
= 25 MSPS; f
f
CLOCK
= 50 MSPS; f
f
CLOCK
f
= 100 MSPS; f
CLOCK
= 165 MSPS; f
f
CLOCK
= 1 MHz –72 –61 dBc
OUT
= 12.5 MHz –65 dBc
OUT
= 25 MHz –60 dBc
OUT
= 41.3 MHz –58 dBc
OUT
Spurious-Free Dynamic Range to Nyquist
= 25 MSPS; f
f
CLOCK
= 1 MHz
OUT
0 dBFS Output 61 72 dBc
f
f
f
f
f
f
NOTES
1
Measured single-ended into 50 W load.
2
Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only.
Specifications subject to change without notice.
= 65 MSPS; f
CLOCK
= 65 MSPS; f
CLOCK
= 100 MSPS; f
CLOCK
= 100 MSPS; f
CLOCK
= 165 MSPS; f
CLOCK
= 165 MSPS; f
CLOCK
= 5 MHz 69 dBc
OUT
= 19 MHz 65 dBc
OUT
= 5 MHz 68 dBc
OUT
= 39 MHz 62 dBc
OUT
= 5 MHz 68 dBc
OUT
= 49 MHz 54 dBc
OUT
= 20 mA, Differential
OUTFS
DIGITAL SPECIFICATIONS
(T
to T
MIN
, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I
MAX
= 20 mA, unless otherwise noted.)
OUTFS
Parameter Min Typ Max Unit
DIGITAL INPUTS
Logic 1 Voltage 2.1 3 V
Logic 0 Voltage 0 0.9 V
Logic 1 Current –10 +10 mA
Logic 0 Current –10 +10 mA
Input Capacitance 5 pF
Input Setup Time (t
Input Hold Time (t
Latch Pulsewidth (t
) 2.0 ns
S
) 1.5 ns
H
) 1.5 ns
LPW
CLK INPUTS*
Input Voltage Range 0 3 V
Common-Mode Voltage 0.75 1.5 2.25 V
Differential Voltage 0.5 1.5 V
*Applicable to CLK+ and CLK– inputs when configured for differential or PECL clock input mode.
Specifications subject to change without notice.
REV. 0
–3–
AD9748
ABSOLUTE MAXIMUM RATINGS*
With
Parameter Respect to Min Max Unit
AVDD ACOM –0.3 +3.9 V
DVDD DCOM –0.3 +3.9 V
CLKVDD CLKCOM –0.3 +3.9 V
ACOM DCOM –0.3 +0.3 V
ACOM CLKCOM –0.3 +0.3 V
DCOM CLKCOM –0.3 +0.3 V
AVDD DVDD –3.9 +3.9 V
AVDD CLKVDD –3.9 +3.9 V
DVDD CLKVDD –3.9 +3.9 V
CLOCK, SLEEP DCOM –0.3 DVDD + 0.3 V
Digital Inputs, MODE DCOM –0.3 DVDD + 0.3 V
IOUTA, IOUTB ACOM –1.0 AVDD + 0.3 V
REFIO, REFLO, FSADJ ACOM –0.3 AVDD + 0.3 V
CLK+, CLK–, CMODE CLKCOM –0.3 CLKVDD + 0.3 V
Junction Temperature 150 ∞C
Storage Temperature –65 +150 ∞C
Lead Temperature (10 sec) 300 ∞C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may effect device reliability.
DB0–DB11
CLOCK
IOUTA
OR
IOUTB
t
S
t
PD
0.1%
t
H
t
LPW
t
ST
0.1%
Figure 1. Timing Diagram
ORDERING GUIDE
Temperature Package Package
Model Range Description Options*
AD9748ACP –40∞C to +85∞C 32-Lead LFCSP CP-32
AD9748ACP-PCB Evaluation Board
*CP = Lead Frame Chip Scale Package
THERMAL CHARACTERISTICS
Thermal Resistance
32-Lead LFCSP
= 32.5∞C/W
JA
Thermal impedance measurements were taken on a 4-layer board
in still air, in accordance with EIA/JESD51-7.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9748 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. 0–4–
PIN CONFIGURATION
32 DB2
31 DB3
30 DB4
29 DB5
27 DB7 (MSB)
26 DCOM
25 SLEEP
28 DB6
AD9748
DB1 1
(LSB) DB0 2
DVDD 3
NC 4
NC 5
NC 6
NC 7
NC 8
PIN 1
INDICATOR
AD9748
TOP VIEW
NC 9
CLK 12
CLK 13
DCOM 10
CLKVDD 11
NC = NO CONNECT
MODE 16
CMODE 15
CLKCOM 14
24 FSADJ
23 REFIO
22 ACOM
21 IOUTA
20 IOUTB
19 ACOM
18 AVDD
17 AVDD
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Description
27 DB7 Most Significant Data Bit (MSB)
28–32, 1 DB6–DB1 Data Bits 6–1
2 DB0 Least Significant Data Bit (LSB)
3 DVDD Digital Supply Voltage (3.3 V)
4–9NCNo Internal Connection
10, 26 DCOM Digital Common
11 CLKVDD Clock Supply Voltage (3.3 V)
12 CLK+ Differential Clock Input
13 CLK– Differential Clock Input
14 CLKCOM Clock Common
15 CMODE
Clock Mode Selection. Connect to CLKCOM for single-ended clock receiver (drive CLK+ and float CLK–).
Connect to CLKVDD for differential receiver. Float for PECL receiver (terminations on-chip).
16 MODE Selects Input Data Format. Connect to CLKCOM for straight binary, CLKVDD for twos complement.
17, 18 AVDD Analog Supply Voltage (3.3 V)
19, 22 ACOM Analog Common
20 IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s.
21 IOUTA DAC Current Output. Full-scale current when all data bits are 1s.
23 REFIO Reference Input/Output. Requires 0.1 mF capacitor to ACOM.
24 FSADJ Full-Scale Current Output Adjust
25 SLEEP Power-Down Control Input. Active high. Contains active pull-down circuit; it may be left unterminated
if not used.
REV. 0
–5–
AD9748
DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the actual
analog output from the ideal output, determined by a straight
line drawn from zero to full scale.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is called
the offset error. For IOUTA, 0 mA output is expected when the
inputs are all 0s. For IOUTB, 0 mA output is expected when all
inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set to
1s minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (25∞C) value to the value at either T
MIN
or T
MAX
. For
offset and gain drift, the drift is reported in ppm of full-scale range
(FSR) per ∞C. For reference drift, the drift is reported in ppm per ∞C.
Power Supply Rejection
The maximum change in the full-scale output as the supplies are
varied from nominal to minimum and maximum specified voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the start
of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. It is expressed
as a percentage or in decibels (dB).
Multitone Power Ratio
The spurious free dynamic range containing multiple carrier tones
of equal amplitude. It is measured as the difference between the
rms amplitude of a carrier tone to the peak spurious signal in
the region of a removed tone.
*AWG2021 CLOCK
RETIMED SO THAT
THE DIGITAL DATA
TRANSITIONS ON
FALLING EDGE OF
50% DUTY CYCLE
CLOCK.
DVDD
DCOM
RETIMED
CLOCK
OUTPUT*
PULSE GENERATOR
R
SET
50
LECROY 9210
0.1F
3.3V
CLK
CLK
3.3V
+1.20V REF
REFIO
FS ADJ
DVDD
DCOM
CLKVDD
CLKCOM
SLEEP DIGITAL DATA INPUTS (DB7–DB0)
CLOCK
OUTPUT
150pF
SEGMENTED
SWITCHES
TEKTRONIX AWG-2021
WITH OPTION 4
Figure 2. Basic AC Characterization Test Setup
CURRENT
LATCHES
DIGITAL
DATA
3.3V
AVDD ACOM
SOURCE
ARRAY
LSB
SWITCHES
AD9748
IOUTA
IOUTB
MODE
CMODE
50
20pF
50
100
20pF
MINI-CIRCUITS
T1–1T
ROHDE &
SCHWARZ
FSEA30
SPECTRUM
ANALYZER
REV. 0–6–
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