a
14-Bit, 165 MSPS
TxDAC
®
D/A Converter
FEATURES
High-Performance Member of Pin-Compatible
TxDAC Product Family
Excellent Spurious-Free Dynamic Range Performance
SFDR to Nyquist:
83 dBc @ 5 MHz Output
80 dBc @ 10 MHz Output
73 dBc @ 20 MHz Output
SNR @ 5 MHz Output, 125 MSPS: 77 dB
Two’s Complement or Straight Binary Data Format
Differential Current Outputs: 2 mA to 20 mA
Power Dissipation: 135 mW @ 3.3 V
Power-Down Mode: 15 mW @ 3.3 V
On-Chip 1.20 V Reference
CMOS-Compatible Digital Interface
Package: 28-Lead SOIC and TSSOP Packages
Edge-Triggered Latches
APPLICATIONS
Wideband Communication Transmit Channel:
Direct IF
Base Stations
Wireless Local Loop
Digital Radio Link
Direct Digital Synthesis (DDS)
Instrumentation
R
SET
CLOCK
FUNCTIONAL BLOCK DIAGRAM
0.1F
3.3V
REFLO
+1.20V REF
REFIO
FS ADJ
DVDD
DCOM
CLOCK
DIGITAL DATA INPUTS (DB13–DB0)
SLEEP
150pF
SEGMENTED
SWITCHES
LATCHES
CURRENT
SOURCE
ARRAY
SWITCHES
AD9744
3.3V
AVDD
ACOM
AD9744
LSB
IOUTA
IOUTB
*
MODE
PRODUCT DESCRIPTION
The AD9744 is a 14-bit resolution, wideband, third generation
member of the TxDAC series of high-performance, low power
CMOS digital-to-analog converters (DACs). The TxDAC family,
consisting of pin-compatible 8-, 10-, 12-, and 14-bit DACs, is
specifically optimized for the transmit signal path of communication systems. All of the devices share the same interface options,
small outline package, and pinout, providing an upward or downward component selection path based on performance, resolution,
and cost. The AD9744 offers exceptional ac and dc performance
while supporting update rates up to 165 MSPS.
The AD9744’s low power dissipation makes it well suited for
portable and low power applications. Its power dissipation can be
further reduced to a mere 60 mW with a slight degradation in
performance by lowering the full-scale current output. Also, a
power-down mode reduces the standby power dissipation to
approximately 15 mW. A segmented current source architecture
is combined with a proprietary switching technique to reduce
spurious components and enhance dynamic performance. Edgetriggered input latches and a 1.2 V temperature compensated
TxDAC is a registered trademark of Analog Devices, Inc.
*Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519.
REV.0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
band gap reference have been integrated to provide a complete
monolithic DAC solution. The digital inputs support 3 V
CMOS logic families.
PRODUCT HIGHLIGHTS
1. The AD9744 is the 14-bit member of the pin-compatible
TxDAC family that offers excellent INL and DNL
performance.
2. Data input supports two’s complement or straight binary
data coding.
3. High-speed, single-ended CMOS clock input supports
165 MSPS conversion rate.
4. Low power: Complete CMOS DAC function operates on
135 mW from a 3.0 V to 3.6 V single supply. The DAC
full-scale current can be reduced for lower power operation,
and a sleep mode is provided for low power idle periods.
5. On-chip voltage reference: The AD9744 includes a 1.2 V
temperature-compensated band gap voltage reference.
6. Industry standard 28-lead SOIC and TSSOP packages.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
AD9744
DC SPECIFICATIONS
-SPECIFICATIONS
(T
to T
MIN
, AVDD = 3.3 V, DVDD = 3.3 V, I
MAX
= 20 mA, unless otherwise noted.)
OUTFS
Parameter Min Typ Max Unit
RESOLUTION 14 Bits
DC ACCURACY
1
Integral Linearity Error (INL) –5 ±0.8 +5 LSB
Differential Nonlinearity (DNL) –3 ±0.5 +3 LSB
ANALOG OUTPUT
Offset Error –0.02 +0.02 % of FSR
Gain Error (Without Internal Reference) –0.5 ± 0.1 +0.5 % of FSR
Gain Error (With Internal Reference) –0.5 ± 0.1 +0.5 % of FSR
Full-Scale Output Current
2
2.0 20.0 mA
Output Compliance Range –1.0 +1.25 V
Output Resistance 100 kW
Output Capacitance 5 pF
REFERENCE OUTPUT
Reference Voltage 1.14 1.20 1.26 V
Reference Output Current
3
100 nA
REFERENCE INPUT
Input Compliance Range 0.1 1.25 V
Reference Input Resistance (Ext. Ref) 1 MW
Small Signal Bandwidth 0.5 MHz
TEMPERATURE COEFFICIENTS
Offset Drift 0 ppm of FSR/∞C
Gain Drift (Without Internal Reference) ±50 ppm of FSR/∞C
Gain Drift (With Internal Reference) ±100 ppm of FSR/∞C
Reference Voltage Drift ±50 ppm/∞C
POWER SUPPLY
Supply Voltages
AVDD 3.0 3.3 3.6 V
DVDD 3.0 3.3 3.6 V
Analog Supply Current (I
Digital Supply Current (I
Supply Current Sleep Mode (I
Power Dissipation
Power Dissipation
4
5
Power Supply Rejection Ratio—AVDD
Power Supply Rejection Ratio—DVDD
)3336mA
AVDD
4
DVDD
)
)56mA
AVDD
89 mA
135 145 mW
6
6
–1 +1 % of FSR/V
–0.04 +0.04 % of FSR/V
145 mW
OPERATING RANGE –40 +85 ∞C
NOTES
1
Measured at IOUTA, driving a virtual ground.
2
Nominal full-scale current, I
3
An external buffer amplifier with input bias current <100 nA should be used to drive any external load.
4
Measured at f
5
Measured as unbuffered voltage output with I
6
±5% Power supply variation.
Specifications subject to change without notice.
= 25 MSPS and f
CLOCK
, is 32 times the I
OUTFS
OUT
= 1.0 MHz.
OUTFS
current.
REF
= 20 mA and 50 W R
at IOUTA and IOUTB, f
LOAD
= 100 MSPS and f
CLOCK
= 40 MHz.
OUT
–2–
REV. 0
(T
to T
DYNAMIC SPECIFICATIONS
MIN
, AVDD = 3.3 V, DVDD = 3.3 V, I
MAX
Output, 50 ⍀ Doubly Terminated, unless otherwise noted.)
= 20 mA, Differential Transformer Coupled
OUTFS
Parameter Min Typ Max Unit
DYNAMIC PERFORMANCE
Maximum Output Update Rate (f
Output Settling Time (t
Output Propagation Delay (t
) (to 0.1%)
ST
)1ns
PD
Glitch Impulse 5 pV-s
Output Rise Time (10% to 90%)
Output Fall Time (10% to 90%)
Output Noise (I
Output Noise (I
Noise Spectral Density
OUTFS
OUTFS
= 20 mA)
= 2 mA)
3
2
) 165 MSPS
CLOCK
1
1
1
2
11 ns
2.5 ns
2.5 ns
50 pA/÷Hz
30 pA/÷Hz
–154 dBm/Hz
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
= 25 MSPS; f
f
CLOCK
= 1.00 MHz
OUT
0 dBFS Output 77 90 dBc
–6 dBFS Output 87 dBc
–12 dBFS Output 82 dBc
–18 dBFS Output 82 dBc
= 65 MSPS; f
f
CLOCK
= 65 MSPS; f
f
CLOCK
f
= 65 MSPS; f
CLOCK
f
= 65 MSPS; f
CLOCK
= 65 MSPS; f
f
CLOCK
f
= 165 MSPS; f
CLOCK
f
= 165 MSPS; f
CLOCK
= 1.00 MHz 85 dBc
OUT
= 2.51 MHz 84 dBc
OUT
= 10 MHz 80 dBc
OUT
= 15 MHz 75 dBc
OUT
= 25 MHz 74 dBc
OUT
= 21 MHz 73 dBc
OUT
= 41 MHz 60 dBc
OUT
Spurious-Free Dynamic Range within a Window
= 25 MSPS; f
f
CLOCK
f
= 50 MSPS; f
CLOCK
= 65 MSPS; f
f
CLOCK
f
= 125 MSPS; f
CLOCK
= 1.00 MHz; 2 MHz Span 84 90 dBc
OUT
= 5.02 MHz; 2 MHz Span 90 dBc
OUT
= 5.03 MHz; 2.5 MHz Span 87 dBc
OUT
= 5.04 MHz; 4 MHz Span 87 dBc
OUT
Total Harmonic Distortion
= 25 MSPS; f
f
CLOCK
f
= 50 MSPS; f
CLOCK
f
= 65 MSPS; f
CLOCK
= 125 MSPS; f
f
CLOCK
= 1.00 MHz –86 –77 dBc
OUT
= 2.00 MHz –77 dBc
OUT
= 2.00 MHz –77 dBc
OUT
= 2.00 MHz –77 dBc
OUT
Signal-to-Noise Ratio
f
= 65 MSPS; f
CLOCK
= 65 MSPS; f
f
CLOCK
f
= 125 MSPS; f
CLOCK
f
= 125 MSPS; f
CLOCK
= 165 MSPS; f
f
CLOCK
f
= 165 MSPS; f
CLOCK
= 5 MHz; I
OUT
= 5 MHz; I
OUT
= 5 MHz; I
OUT
= 5 MHz; I
OUT
= 5 MHz; I
OUT
= 5 MHz; I
OUT
= 20 mA 82 dB
OUTFS
= 5 mA 88 dB
OUTFS
= 20 mA 77 dB
OUTFS
= 5 mA 78 dB
OUTFS
= 20 mA 70 dB
OUTFS
= 5 mA 70 dB
OUTFS
Multitone Power Ratio (8 Tones at 400 kHz Spacing)
= 78 MSPS; f
f
CLOCK
= 15.0 MHz to 18.2 MHz
OUT
0 dBFS Output 66 dBc
–6 dBFS Output 68 dBc
–12 dBFS Output 62 dBc
–18 dBFS Output 61 dBc
NOTES
1
Measured single-ended into 50 W load.
2
Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only.
3
Noise spectral density is the average noise power normalized to a 1 Hz bandwidth, with the DAC converting and producing an output tone.
Specifications subject to change without notice.
AD9744
REV. 0
–3–
AD9744
WARNING!
ESD SENSITIVE DEVICE
(T
to T
DIGITAL SPECIFICATIONS
MIN
, AVDD = 3.3 V, DVDD = 3.3 V, I
MAX
Parameter Min Typ Max Unit
DIGITAL INPUTS
Logic “1” Voltage 2.1 3 V
Logic “0” Voltage 0 0.9 V
Logic “1” Current –10 +10 mA
Logic “0” Current –10 +10 mA
Input Capacitance 5 pF
Input Setup Time (t
Input Hold Time (t
Latch Pulsewidth (t
) 2.0 ns
S
) 1.5 ns
H
) 1.5 ns
LPW
DB0–DB11
CLOCK
IOUTA
OR
IOUTB
t
S
t
PD
0.1%
t
t
LPW
t
ST
= 20 mA, unless otherwise noted.)
OUTFS
H
0.1%
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS*
With
Parameter Respect to Min Max Unit
AVDD ACOM –0.3 +3.9 V
DVDD DCOM –0.3 +3.9 V
ACOM DCOM –0.3 +0.3 V
AVDD DVDD –3.9 +3.9 V
CLOCK, SLEEP DCOM –0.3 DVDD + 0.3 V
Digital Inputs DCOM –0.3 DVDD + 0.3 V
IOUTA, IOUTB ACOM –1.0 AVDD + 0.3 V
REFIO, REFLO, FSADJ ACOM –0.3 AVDD + 0.3 V
Junction Temperature 150 ∞C
Storage Temperature –65 +150 ∞C
Lead Temperature (10 sec) 300 ∞C
*Stresses above those listed under Absolute Maximum Ratings may cause perma
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
Model Range Description Options*
AD9744AR –40∞C to +85∞C 28-Lead 300 Mil SOIC R-28
AD9744ARU –40∞C to +85∞C 28-Lead TSSOP RU-28
AD9744-EB Evaluation Board
*R = Small Outline IC; RU = Thin Shrink Small Outline Package
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead 300-Mil SOIC
JA= 71.4∞C/W
28-Lead TSSOP
JA= 97.9∞C/W
ORDERING GUIDE
Temperature Package Package
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9744 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–4–
REV. 0
PIN CONFIGURATION
AD9744
(MSB) DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
(LSB) DB0
1
2
3
4
5
AD9744
6
TOP VIEW
(Not to Scale)
7
8
9
10
11
12
13
14
NC = NO CONNECT
CLOCK
28
DVDD
27
26
DCOM
25
MODE
AVDD
24
23
RESERVED
IOUTA
22
21
IOUTB
20
ACOM
19
NC
FS ADJ
18
REFIO
17
REFLO
16
SLEEP
15
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Description
1 DB13 Most Significant Data Bit (MSB)
2–13 DB12–DB1 Data Bits 12-1
14 DB0 Least Significant Data Bit (LSB)
15 SLEEP Power-Down Control Input. Active high. Contains active pull-down circuit; it may be left
unterminated if not used.
16 REFLO Reference Ground when internal 1.2 V reference used. Connect to AVDD to disable internal reference.
17 REFIO Reference Input/Output. Serves as reference input when internal reference disabled (i.e., tie REFLO to
AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., tie REFLO to AGND).
Requires 0.1 mF capacitor to AGND when internal reference activated.
18 FS ADJ Full-Scale Current Output Adjust
19 NC No Internal Connection
20 ACOM Analog Common
21 IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s.
22 IOUTA DAC Current Output. Full-scale current when all data bits are 1s.
23 RESERVED Reserved. Do Not Connect to Common or Supply.
24 AVDD Analog Supply Voltage (3.3 V)
25 MODE Selects Input Data Format. Connect to DGND for straight binary, DVDD for two’s complement
26 DCOM Digital Common
27 DVDD Digital Supply Voltage (3.3 V)
28 CLOCK Clock Input. Data latched on positive edge of clock.
REV. 0
–5–
AD9744
DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the actual
analog output from the ideal output, determined by a straight line
drawn from zero to full scale.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called the offset error. For IOUTA, 0 mA output is expected
when the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown resulting in
nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (25∞C) value to the value at either T
MIN
or T
MAX
. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per ∞C. For reference drift, the drift is reported in
ppm per ∞C.
Power Supply Rejection
The maximum change in the full-scale output as the supplies are
varied from nominal to minimum and maximum specified voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Total Harmonic Distortion
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal. It is
expressed as a percentage or in decibels (dB).
Multitone Power Ratio
The spurious free dynamic range containing multiple carrier
tones of equal amplitude. It is measures as the difference between
the rms amplitude of a carrier tone to the peak spurious signal
in the region of a removed tone.
DVDD
DCOM
R
SET
2k⍀
50⍀
RETIMED
CLOCK
OUTPUT*
LECROY 9210
PULSE GENERATOR
0.1F
3.3V
+1.20V REF
REFIO
FS ADJ
DVDD
DCOM
CLOCK
SLEEP
3.3V
REFLO
SEGMENTED SWITCHES
FOR DB13–DB5
CLOCK
OUTPUT
150pF
LATCHES
DIGITAL
DATA
TEKTRONIX AWG-2021
w/OPTION 4
AVDD ACOM
PMOS
CURRENT SOURCE
ARRAY
LSB
SWITCHES
AD9744
IOUTA
IOUTB
MODE
50⍀
Figure 2. Basic AC Characterization Test Set-Up
MINI-CIRCUITS
T1-1T
100⍀
50⍀
20pF
20pF
* AWG2021 CLOCK RETIMED
SUCH THAT DIGITAL DATA
TRANSITIONS ON FALLING EDGE
OF 50% DUTY CYCLE CLOCK.
RHODE & SCHWARZ
FSEA30
SPECTRUM
ANALYZER
–6–
REV. 0
Typical Performance Characteristics–AD9744
95
90
85
80
75
70
65
SFDR – dBc
60
55
50
45
110100
f
OUT
TPC 1. SFDR vs. f
95
90
85
80
75
70
65
SFDR – dBc
60
55
50
45
06010
f
OUT
– MHz
OUT
– MHz
65MSPS
125MSPS
165MSPS
@ 0 dBFS
–6dBFS
–12dBFS
0dBFS
403020 50
95
90
85
80
75
70
65
SFDR – dBc
60
55
50
45
05 2510 15 20
TPC 2. SFDR vs. f
95
90
20mA
85
80
75
70
65
SFDR – dBc
60
55
50
45
05 2510 15 20
f
f
OUT
OUT
0dBFS
– MHz
OUT
– MHz
–6dBFS
–12dBFS
@ 65 MSPS
10mA
5mA
95
90
85
80
75
70
65
SFDR – dBc
60
55
50
45
05 4510 15 35
f
OUT
TPC 3. SFDR vs. f
95
90
85
80
75
70
65
SFDR – dBc
60
55
50
45
A
OUT
–6dBFS
–12dBFS
0dBFS
– MHz
@ 125 MSPS
OUT
65MSPS
125MSPS
165MSPS
– dBFS
403020 25
0–5–25 –10–15–20
TPC 4. SFDR vs. f
95
90
85
80
75
70
65
SFDR – dBc
60
55
50
45
–20 –15–25 –10 –5
A
OUT
OUT
165MSPS
– dBFS
@ 165 MSPS
65MSPS
125MSPS
TPC 7. Single-Tone SFDR vs.
@ f
A
OUT
OUT
= f
CLOCK
/5
TPC 5. SFDR vs. f
OUT
and I
OUTFS
@ 65 MSPS and 0 dBFS
90
85
80
75
SNR – dB
70
65
0
60
TPC 8. SNR vs. f
I
OUTFS
5mA
10mA
20mA
50
90 11070 130 150
f
CLOCK
@ f
= 5 MHz and 0 dBFS
OUT
– MSPS
CLOCK
and
170
TPC 6. Single-Tone SFDR vs.
A
OUT
95
65MSPS (8.3,10.3)
90
85
80
75
70
125MSPS (16.9, 18.9)
65
SFDR – dBc
60
55
50
45
@ f
= f
OUT
78MSPS (10.1, 12.1)
A
OUT
/11
CLOCK
165MSPS (22.6, 24.6)
– dBFS
TPC 9. Dual-Tone IMD vs. A
@ f
OUT
= f
CLOCK
/7
0–5–25 –10–15–20
OUT
REV. 0
–7–
AD9744
1.5
1.0
0.5
0
ERROR – LSB
–0.5
–1.0
–1.5
4096 8192 12288 16384
0
CODE
TPC 10. Typical INL
0
–10
–20
–30
–40
–50
–60
–70
MAGNITUDE – dBm
–80
–90
–100
16 2611 16 21
f
CLOCK
f
= 15.0MHz
OUT
SFDR = 79dBc
AMPLITUDE = 0dBFS
FREQUENCY – MHz
TPC 13. Single-Tone SFDR
= 78MSPS
1.0
0.8
0.6
0.4
0.2
0
–0.2
ERROR – LSB
–0.4
–0.6
–0.8
–1.0
0 4096
TPC 11. Typical DNL
8192 12288 16384
CODE
95
90
85
80
75
70
65
SFDR – dBc
34MHz
60
55
50
45
–40 –20 6002040
4MHz
19MHz
49MHz
80
TEMPERATURE – ⴗC
TPC 12. SFDR vs. Temperature @
165 MSPS, 0 dBFS
0
–10
–20
–30
–40
–50
–60
–70
MAGNITUDE – dBm
–80
–90
31
36
–100
16 2611 16 21
f
= 78MSPS
CLOCK
f
= 15.0MHz
OUT1
f
= 15.4MHz
OUT2
SFDR = 77dBc
AMPLITUDE = 0dBFS
FREQUENCY – MHz
31
36
TPC 14. Dual-Tone SFDR
0
–10
–20
–30
–40
–50
–60
–70
MAGNITUDE – dBm
–80
–90
–100
16 2611 16 21
f
CLOCK
f
OUT1
f
OUT2
f
OUT3
f
OUT4
SFDR = 75dBc
AMPLITUDE = 0dBFS
FREQUENCY – MHz
TPC 15. Four-Tone SFDR
= 78MSPS
= 15.0MHz
= 15.4MHz
= 15.8MHz
= 16.2MHz
31
36
–20
–30
–40
–50
–60
–70
–80
–90
MAGNITUDE – dBm
C12
–100
–110
–120
CENTER 33.22MHz
C12
C0
C11
C11
3MHz SPAN 30MHz
C0
CU1
TPC 16. Two-Carrier UMTS
Spectrum (ACLR = 64 dB)
–39.01dBm
29.38000000MHz
CH PWR –19.26dBm
ACP U P –64.98dB
ACP L OW +0.55dB
ALT1 UP –66.26dB
ALT1 LOW –64.23dB
CU1
CU2
CU2
–8–
REV. 0
)
3.3V
AD9744
0.1F
V
REFIO
R
CLOCK
SET
2k⍀
I
3.3V
REF
REFIO
FS ADJ
DVDD
DCOM
CLOCK
SLEEP
REFLO
+1.20V REF
SEGMENTED SWITCHES
150pF
CURRENT SOURCE
FOR DB13–DB5
LATCHES
DIGITAL DATA INPUTS (DB13–DB0
Figure 3. Simplified Block Diagram
FUNCTIONAL DESCRIPTION
Figure 3 shows a simplified block diagram of the AD9744. The
AD9744 consists of a DAC, digital control logic, and full-scale
output current control. The DAC contains a PMOS current
source array capable of providing up to 20 mA of full-scale
current (I
). The array is divided into 31 equal currents
OUTFS
that make up the five most significant bits (MSBs). The next
four bits, or middle bits, consist of 15 equal current sources
whose value is 1/16th of an MSB current source. The remaining
LSBs are binary weighted fractions of the middle bits current
sources. Implementing the middle and lower bits with current
sources, instead of an R-2R ladder, enhances its dynamic performance for multitone or low amplitude signals and helps maintain
the DAC’s high output impedance (i.e., >100 kW).
All of these current sources are switched to one or the other of
the two output nodes (i.e., IOUTA or IOUTB) via PMOS
differential current switches. The switches are based on the
architecture that was pioneered in the AD9764 family, with
further refinements to reduce distortion contributed by the
switching transient. This switch architecture also reduces various timing errors and provides matching complementary drive
signals to the inputs of the differential current switches.
The analog and digital sections of the AD9744 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 3.0 V to 3.6 V range. The digital section,
which is capable of operating up to a 165 MSPS clock rate,
consists of edge-triggered latches and segment decoding logic
circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.2 V band gap
voltage reference, and a reference control amplifier.
The DAC full-scale output current is regulated by the reference control amplifier and can be set from 2 mA to 20 mA via
an external resistor, R
, connected to the full-scale adjust
SET
(FSADJ) pin. The external resistor, in combination with both
the reference control amplifier and voltage reference V
sets the reference current I
, which is replicated to the
REF
REFIO
,
segmented current sources with the proper scaling factor. The
full-scale current, I
, is 32 times I
OUTFS
REF
.
AVDD ACOM
AD9744
PMOS
ARRAY
SWITCHES
LSB
IOUTA
IOUTB
IOUTB
MODE
IOUTA
V
= V
OUTB
LOAD
OUTA
– V
OUTB
V
OUTA
R
50⍀
LOAD
DIFF
V
R
50⍀
REFERENCE OPERATION
The AD9744 contains an internal 1.2 V band gap reference.
The internal reference can be disabled by raising REFLO to
AVDD. It can also be easily overridden by an external reference
with no effect on performance. REFIO serves as either an input
or output depending on whether the internal or an external
reference is used. To use the internal reference, simply decouple
the REFIO pin to ACOM with a 0.1 mF capacitor and connect
REFLO to ACOM via a resistance less than 5 W. The internal
reference voltage will be present at REFIO. If the voltage at
REFIO is to be used anywhere else in the circuit, an external
buffer amplifier with an input bias current of less than 100 nA
should be used. An example of the use of the internal reference is
given in Figure 4.
3.3V
AVDD
CURRENT
SOURCE
ARRAY
ADDITIONAL
LOAD
OPTIONAL
EXTERNAL
REF BUFFER
0.1F
2k⍀
+1.2V REF
REFIO
FS ADJ
AD9744
REFLO
150pF
Figure 4. Internal Reference Configuration
An external reference can be applied to REFIO as shown in
Figure 5. The external reference may provide either a fixed
reference voltage to enhance accuracy and drift performance or
a varying reference voltage for gain control. Note that the 0.1 mF
compensation capacitor is not required since the internal reference is overridden, and the relatively high input impedance of
REFIO minimizes any loading of the external reference.
3.3V
AVDD
EXTERNAL
REF
+1.2V REF
V
REFIO
R
SET
=
I
REF
V
REFIO/RSET
REFIO
FS ADJ
AD9744
150pF
REFERENCE
CONTROL
AMPLIFIER
AVDDREFLO
CURRENT
SOURCE
ARRAY
REV. 0
Figure 5. External Reference Configuration
–9–
AD9744
REFERENCE CONTROL AMPLIFIER
The AD9744 contains a control amplifier that is used to regulate the full-scale output current, I
. The control amplifier
OUTFS
is configured as a V-I converter as shown in Figure 4, so that its
current output, I
and an external resistor, R
, is determined by the ratio of the V
REF
, as stated in Equation 4. I
SET
REFIO
is
REF
copied to the segmented current sources with the proper scale
factor to set I
as stated in Equation 3.
OUTFS
The control amplifier allows a wide (10:1) adjustment span of
I
over a 2 mA to 20 mA range by setting I
OUTFS
62.5 mA and 625 mA. The wide adjustment span of I
between
REF
OUTFS
provides
several benefits. The first relates directly to the power dissipation of the AD9744, which is proportional to I
OUTFS
(refer to the
Power Dissipation section). The second relates to the 20 dB
adjustment, which is useful for system gain control purposes.
The small signal bandwidth of the reference control amplifier is
approximately 500 kHz and can be used for low-frequency small
signal multiplying applications.
DAC TRANSFER FUNCTION
Both DACs in the AD9744 provide complementary current
outputs, IOUTA and IOUTB. IOUTA will provide a near fullscale current output, I
, when all bits are high (i.e., DAC
OUTFS
CODE = 16383), while IOUTB, the complementary output,
provides no current. The current output appearing at IOUTA
and IOUTB is a function of both the input code and I
OUTFS
and
can be expressed as:
IOUTA DAC CODE I
IOUTB DAC CODE I
=¥(/)16384
OUTFS
=¥(– )/16383 16384
OUTFS
(1)
(2)
where DAC CODE = 0 to 16383 (i.e., decimal representation).
As mentioned previously, I
current I
V
REFIO
II
OUTFS REF
, which is nominally set by a reference voltage,
REF
, and external resistor, R
=¥32
is a function of the reference
OUTFS
. It can be expressed as:
SET
(3)
where
IV R
= /
REF REFIO SET
(4)
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, IOUTA
and IOUTB should be directly connected to matching resistive
loads, R
R
LOAD
, that are tied to analog common, ACOM. Note,
LOAD
may represent the equivalent load resistance seen by
IOUTA or IOUTB as would be the case in a doubly terminated
50 W or 75 W cable. The single-ended voltage output appearing
at the IOUTA and IOUTB nodes is simply:
V IOUTA R
=¥
OUTA LOAD
V IOUTB R
=¥
OUTB LOAD
(5)
(6)
Note the full-scale value of V
OUTA
and V
should not exceed
OUTB
the specified output compliance range to maintain specified
distortion and linearity performance.
V IOUTA IOUTB R
=¥(–)
DIFF LOAD
(7)
Substituting the values of IOUTA, IOUTB, I
REF
, and V
DIFF
can
be expressed as:
V DAC CODE
=¥
(–)/
2 16383 16384
{}
DIFF
RRV
¥
32
()
/
LOAD SET REFIO
¥
(8)
These last two equations highlight some of the advantages of
operating the AD9744 differentially. First, the differential
operation will help cancel common-mode error sources associated with IOUTA and IOUTB
such as noise, distortion,
,
and dc offsets. Second, the differential code dependent current
and subsequent voltage, V
ended voltage output (i.e., V
, is twice the value of the single-
DIFF
OUTA
or V
), thus providing
OUTB
twice the signal power to the load.
Note, the gain drift temperature performance for a single-ended
(V
OUTA
and V
) or differential output (V
OUTB
) of the AD9744
DIFF
can be enhanced by selecting temperature tracking resistors for
R
LOAD
and R
due to their ratiometric relationship as shown in
SET
Equation 8.
ANALOG OUTPUTS
The complementary current outputs in each DAC, IOUTA and
IOUTB, may be configured for single-ended or differential operation. IOUTA and IOUTB can be converted into complementary
single-ended voltage outputs, V
resistor, R
, as described in the DAC Transfer Function
LOAD
OUTA
and V
section by Equations 5 through 8. The differential voltage, V
existing between V
OUTA
and V
can also be converted to a
OUTB
, via a load
OUTB
DIFF
,
single-ended voltage via a transformer or differential amplifier
configuration. The ac performance of the AD9744 is optimum and
specified using a differential transformer coupled output in which
the voltage swing at IOUTA and IOUTB is limited to ±0.5 V.
The distortion and noise performance of the AD9744 can be
enhanced when it is configured for differential operation. The
common-mode error sources of both IOUTA and IOUTB can
be significantly reduced by the common-mode rejection of a
transformer or differential amplifier. These common-mode error
sources include even-order distortion products and noise. The
enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform
increases and/or its amplitude decreases. This is due to the first
order cancellation of various dynamic common-mode distortion
mechanisms, digital feedthrough, and noise.
Performing a differential-to-single-ended conversion via a transformer also provides the ability to deliver twice the reconstructed
signal power to the load (i.e., assuming no source termination).
Since the output currents of IOUTA and IOUTB are complementary, they become additive when processed differentially. A
properly selected transformer will allow the AD9744 to provide
the required power and voltage levels to different loads.
The output impedance of IOUTA and IOUTB is determined
by the equivalent parallel combination of the PMOS switches
associated with the current sources and is typically 100 kW in
parallel with 5 pF. It is also slightly dependent on the output
voltage (i.e., V
OUTA
and V
) due to the nature of a PMOS
OUTB
device. As a result, maintaining IOUTA and/or IOUTB at a
virtual ground via an I-V op amp configuration will result in
the optimum dc linearity. Note the INL/DNL specifications
for the AD9744 are measured with IOUTA maintained at a
virtual ground via an op amp.
–10–
REV. 0
AD9744
IOUTA and IOUTB also have a negative and positive voltage
compliance range that must be adhered to in order to achieve
optimum performance. The negative output compliance range of
–1.0 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a breakdown
of the output stage and affect the reliability of the AD9744.
The positive output compliance range is slightly dependent on the
full-scale output current, I
nominal 1.2 V for an I
OUTFS
. It degrades slightly from its
OUTFS
= 20 mA to 1.0 V for an I
OUTFS
= 2 mA.
The optimum distortion performance for a single-ended or differential output is achieved when the maximum full-scale signal at
IOUTA and IOUTB does not exceed 0.5 V.
DIGITAL INPUTS
The AD9744’s digital section consists of 14 input bit channel
and a clock input. The 14-bit parallel data inputs follow standard positive binary coding where DB13 is the most significant
bit (MSB) and DB0 is the least significant bit (LSB). IOUTA
produces a full-scale output current when all data bits are at
Logic 1. IOUTB produces a complementary output with the
full-scale current split between the two outputs as a function of
the input code.
DVDD
DIGITAL
INPUT
80
75
70
65
60
SFDR – dBc
55
50
45
40
–3 –2 2–1 0 1
TIME (ns) OF DATA CHANGE RELATIVE
TO RISING CLOCK EDGE
Figure 7. SFDR vs. Clock Placement @ f
f
= 20MHz
OUT
f
= 50MHz
OUT
= 20 MHz and
OUT
3
50 MHz
Sleep Mode Operation
The AD9744 has a power-down function that turns off the
output current and reduces the supply current to less than 4 mA
over the specified supply range of 3.0 V to 3.6 V and temperature range. This mode can be activated by applying a logic level
1 to the SLEEP pin. The SLEEP pin logic threshold is equal to
0.5 ¥ AVDD. This digital input also contains an active pulldown circuit that ensures the AD9744 remains enabled if this
input is left disconnected. The AD9744 takes less than 50 ns to
power down and approximately 5 ms to power back up.
Figure 6. Equivalent Digital Input
The digital interface is implemented using an edge-triggered
master/slave latch. The DAC output updates on the rising edge
of the clock and is designed to support a clock rate as high as
165 MSPS. The clock can be operated at any duty cycle that
meets the specified latch pulsewidth. The setup and hold times
can also be varied within the clock cycle as long as the specified
minimum times are met, although the location of these transition
edges may affect digital feedthrough and distortion performance.
Best performance is typically achieved when the input data transitions on the falling edge of a 50% duty cycle clock.
DAC TIMING
Input Clock and Data Timing Relationship
Dynamic performance in a DAC is dependent on the relationship between the position of the clock edges and the point in
time at which the input data changes. The AD9744 is rising
edge triggered, and so exhibits dynamic performance sensitivity
when the data transition is close to this edge. In general, the
goal when applying the AD9744 is to make the data transition
close to the falling clock edge. This becomes more important as
the sample rate increases. Figure 7 shows the relationship of
SFDR to clock placement with different sample rates. Note that
at the lower sample rates, more tolerance is allowed in clock
placement, while at higher rates, more care must be taken.
POWER DISSIPATION
The power dissipation, PD, of the AD9744 is dependent on
several factors that include:
•
The power supply voltages (AVDD and DVDD)
•
The full-scale current output I
•
The update rate f
•
The reconstructed digital input waveform
CLOCK
OUTFS
The power dissipation is directly proportional to the analog
supply current, I
I
is directly proportional to I
AVDD
and is insensitive to f
both the digital input waveform, f
DVDD. Figure 9 shows I
wave output ratios (f
, and the digital supply current, I
AVDD
CLOCK
OUT/fCLOCK
. Conversely, I
as a function of full-scale sine
DVDD
as shown in Figure 8
OUTFS
DVDD
, and digital supply
CLOCK
) for various update rates with
.
DVDD
is dependent on
DVDD = 3.3 V.
REV. 0
–11–
AD9744
35
30
25
– mA
20
AVD D
I
15
10
0
4681012 14 16 18 20
2
Figure 8. I
16
14
12
10
– mA
8
DVDD
I
6
4
2
0
0.01 10.1
Figure 9. I
DVDD
I
– mA
OUTFS
vs. I
AVDD
165MSPS
125MSPS
65MSPS
RATIO – f
OUTFS
OUT/fCLOCK
vs. Ratio @ DVDD = 3.3 V
APPLYING THE AD9744
Output Configurations
The following sections illustrate some typical output configurations for the AD9744. Unless otherwise noted, it is assumed
that I
is set to a nominal 20 mA. For applications requir-
OUTFS
ing the optimum dynamic performance, a differential output
configuration is suggested. A differential output configuration
may consist of either an RF transformer or a differential op amp
configuration. The transformer configuration provides the optimum high-frequency performance and is recommended for any
application that allows ac coupling. The differential op amp
configuration is suitable for applications requiring dc coupling, a
bipolar output, signal gain, and/or level shifting, within the
bandwidth of the chosen op amp.
A single-ended output is suitable for applications requiring a
unipolar voltage output. A positive unipolar output voltage will
result if IOUTA and/or IOUTB is connected to an appropriately
sized load resistor, R
, referred to ACOM. This configuration
LOAD
may be more suitable for a single-supply system requiring a
dc-coupled, ground referred output voltage. Alternatively, an
amplifier could be configured as an I-V converter, thus converting
IOUTA or IOUTB into a negative unipolar voltage. This
configuration provides the best dc linearity since IOUTA or
IOUTB is maintained at a virtual ground.
DIFFERENTIAL COUPLING USING A TRANSFORMER
An RF transformer can be used to perform a differential-to-singleended signal conversion as shown in Figure 10. A differentially
coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the
transformer’s passband. An RF transformer, such as the MiniCircuits T1–1T, provides excellent rejection of common-mode
distortion (i.e., even-order harmonics) and noise over a wide
frequency range. It also provides electrical isolation and the ability
to deliver twice the power to the load. Transformers with different
impedance ratios may also be used for impedance matching
purposes. Note that the transformer provides ac coupling only.
MINI-CIRCUITS
IOUTA
AD9744
IOUTB
22
21
T1-1T
OPTIONAL R
DIFF
R
LOAD
Figure 10. Differential Output Using a Transformer
The center tap on the primary side of the transformer must be
connected to ACOM to provide the necessary dc current path for
both IOUTA and IOUTB. The complementary voltages appearing
at IOUTA and IOUTB (i.e., V
OUTA
and V
) swing symmetri-
OUTB
cally around ACOM and should be maintained with the specified
output compliance range of the AD9744. A differential resistor,
, may be inserted in applications where the output of the
R
DIFF
transformer is connected to the load, R
struction filter or cable. R
is determined by the transformer’s
DIFF
, via a passive recon-
LOAD
impedance ratio and provides the proper source termination that
results in a low VSWR. Note that approximately half the signal
power will be dissipated across R
DIFF
.
DIFFERENTIAL COUPLING USING AN OP AMP
An op amp can also be used to perform a differential-to-single-ended
conversion as shown in Figure 11. The AD9744 is configured with
two equal load resistors, R
, of 25 W. The differential voltage
LOAD
developed across IOUTA and IOUTB is converted to a singleended signal via the differential op amp configuration. An optional
capacitor can be installed across IOUTA and IOUTB, forming a
real pole in a low-pass filter. The addition of this capacitor also
enhances the op amp’s distortion performance by preventing the
DACs high slewing output from overloading the op amp’s input.
500⍀
AD9744
IOUTA
IOUTB
22
21
C
OPT
225⍀
225⍀
25⍀25⍀
AD8047
500⍀
Figure 11. DC Differential Coupling Using an Op Amp
The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the differential op amp circuit using the AD8047 is configured to provide
some additional signal gain. The op amp must operate off of a
dual supply since its output is approximately ±1.0 V. A highspeed amplifier capable of preserving the differential performance
–12–
REV. 0
of the AD9744 while meeting other system level objectives (i.e.,
AD9744
22
IOUTA
IOUTB
21
C
OPT
200⍀
U1
V
OUT
= I
OUTFS
ⴛ R
FB
I
OUTFS
= 10mA
R
FB
200⍀
cost, power) should be selected. The op amp’s differential gain,
its gain setting resistor values, and full-scale output swing capabilities should all be considered when optimizing this circuit.
The differential circuit shown in Figure 12 provides the necessary level shifting required in a single-supply system. In this
case, AVDD, which is the positive analog supply for both the
AD9744 and the op amp, is also used to level-shift the differential output of the AD9744 to midsupply (i.e., AVDD/2). The
AD8041 is a suitable op amp for this application.
500⍀
AD9744
IOUTA
IOUTB
22
21
C
OPT
225⍀
1k⍀
AD8041
1k⍀
AVDD
225⍀
25⍀25⍀
Figure 12. Single Supply DC Differential Coupled Circuit
SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT
Figure 13 shows the AD9744 configured to provide a unipolar
output range of approximately 0 V to 0.5 V for a doubly terminated 50 W cable since the nominal full-scale current, I
20 mA flows through the equivalent R
represents the equivalent load resistance seen by IOUTA
R
LOAD
of 25 W. In this case,
LOAD
OUTFS
, of
or IOUTB. The unused output (IOUTA or IOUTB) can be
connected to ACOM directly or via a matching R
values of I
OUTFS
and R
can be selected as long as the positive
LOAD
LOAD
. Different
compliance range is adhered to. One additional consideration in
this mode is the integral nonlinearity (INL) as discussed in the
Analog Output section of this data sheet. For optimum INL
performance, the single-ended, buffered voltage output configuration is suggested.
AD9744
Figure 14. Unipolar Buffered Voltage Output
POWER AND GROUNDING CONSIDERATIONS, POWER SUPPLY REJECTION
Many applications seek high-speed and high-performance under
less than ideal operating conditions. In these application circuits,
the implementation and construction of the printed circuit board
is as important as the circuit design. Proper RF techniques must
be used for device selection, placement, and routing as well as
power supply bypassing and grounding to ensure optimum
performance. Figures 19 to 22 illustrate the recommended printed
circuit board ground, power, and signal plane layouts that are
implemented on the AD9744 evaluation board.
One factor that can measurably affect system performance is the
ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution.
This is referred to as the power supply rejection ratio. For dc
variations of the power supply, the resulting performance of the
DAC directly corresponds to a gain error associated with the
DAC’s full-scale current, I
common in applications where the power distribution is generated by a switching power supply. Typically, switching power
supply noise will occur over the spectrum from tens of kHz to
several MHz. The PSRR vs frequency of the AD9744 AVDD
supply over this frequency range is shown in Figure 15.
. AC noise on the dc supplies is
OUTFS
AD9744
IOUTA
IOUTB
I
= 20mA
OUTFS
22
50⍀
21
25⍀
V
OUTA
= 0V TO 0.5V
50⍀
Figure 13. 0 V to 0.5 V Unbuffered Voltage Output
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT CONFIGURATION
Figure 14 shows a buffered single-ended output configuration in
which the op amp U1 performs an I-V conversion on the AD9744
output current. U1 maintains IOUTA (or IOUTB) at a virtual
ground, minimizing the nonlinear output impedance effect on the
DAC’s INL performance as discussed in the Analog Output
section. Although this single-ended configuration typically provides
the best dc linearity performance, its ac distortion performance
at higher DAC update rates may be limited by U1’s slew rate
capabilities. U1 provides a negative unipolar output voltage and its
full-scale output voltage is simply the product of R
The full-scale output should be set within U1’s voltage output
swing capabilities by scaling I
in ac distortion performance may result with a reduced I
the signal current U1 will be required to sink less signal current.
REV. 0
and I
and/or RFB. An improvement
OUTFS
FB
OUTFS
OUTFS
since
85
80
75
70
65
60
PSRR – dB
55
50
45
40
24 810
FREQUENCY – MHz
Figure 15. Power Supply Rejection Ratio
Note that the units in Figure 15 are given in units of (amps out/
volts in). Noise on the analog power supply has the effect of
modulating the internal switches, and therefore the output
current. The voltage noise on AVDD, therefore, will be added
.
in a nonlinear manner to the desired IOUT. Due to the relative
different size of these switches, PSRR is very code dependent. This
can produce a mixing effect that can modulate low-frequency
power supply noise to higher frequencies. Worst-case PSRR for
–13–
1260
AD9744
either one of the differential DAC outputs will occur when the
full-scale current is directed toward that output. As a result, the
PSRR measurement in Figure 15 represents a worst-case condition
in which the digital inputs remain static and the full-scale output
current of 20 mA is directed to the DAC output being measured.
An example serves to illustrate the effect of supply noise on the
analog supply. Suppose a switching regulator with a switching
frequency of 250 kHz produces 10 mV of noise and, for simplicity sake (i.e., ignore harmonics), all of this noise is concentrated
at 250 kHz. To calculate how much of this undesired noise will
appear as current noise superimposed on the DAC’s full-scale
current, I
Figure 15 at 250 kHz. To calculate the PSRR for a given R
, one must determine the PSRR in dB using
OUTFS
LOAD
,
such that the units of PSRR are converted from A/V to V/V,
adjust the curve in Figure 15 by the scaling factor 20 ¥ log(R
For instance, if R
is 50 W, the PSRR is reduced by 34 dB (i.e.,
LOAD
LOAD
).
PSRR of the DAC at 250 kHz which is 85 dB in Figure 15 becomes
51 dB V
OUT/VIN
).
Proper grounding and decoupling should be a primary objective
in any high-speed, high resolution system. The AD9744 features
separate analog and digital supply and ground pins to optimize
the management of analog and digital ground currents in a
system. In general, AVDD, the analog supply, should be decoupled
to ACOM, the analog common, as close to the chip as physically
possible. Similarly, DVDD, the digital supply, should be decoupled
to DCOM as close to the chip as physically possible.
For those applications that require a single 3.3 V supply for both
the analog and digital supplies, a clean analog supply may be
generated using the circuit shown in Figure 16. The circuit
consists of a differential LC filter with separate power supply
and return lines. Lower noise can be attained by using low ESR
type electrolytic and tantalum capacitors.
FERRITE
BEADS
TTL/CMOS
LOGIC
CIRCUITS
POWER SUPPLY
3.3V
100F
ELECT.
10F–22F
TANT.
0.1F
CER.
AVDD
ACOM
Figure 16. Differential LC Filter for Single 3.3 V Applications
EVALUATION BOARD
General Description
The TxDAC Family Evaluation Board allows for easy set up
and testing of any TxDAC product in the 28-lead SOIC package. Careful attention to layout and circuit design combined
with a prototyping area allow the user to evaluate the AD9744
easily and effectively in any application where high resolution,
high-speed conversion is required.
This board allows the user the flexibility to operate the AD9744
in various configurations. Possible output configurations include
transformer coupled, resistor terminated, and single and differential outputs. The digital inputs are designed to be driven from
various word generators, with the on-board option to add a
resistor network for proper load termination. Provisions are also
made to operate the AD9744 with either the internal or external
reference or to exercise the power-down feature.
–14–
REV. 0
AD9744
J1
21
4
65
87
10 9
12 11
14 13
16 15
18 17
20 19
22 21
24 23
26 25
28 27
30 29
32 31
34 33
36 35
38 37
40 39
RIBBON
TB1 1
C7
0.1F
TB1 2
TB1 3
C9
0.1F
TB1 4
3
L2 10H
BLK
L3 10H
BLK
TP4
TP6
JP3
+
+
C4
10F
25V
C5
10F
25V
DB13X
DB12X
DB11X
DB10X
DB9X
DB8X
DB7X
DB6X
DB5X
DB4X
DB3X
DB2X
DB1X
DB0X
CKEXTX
RED
RED
TP2
TP5
C6
0.1F
C8
0.1F
DB13X
DB12X
DB11X
DB10X
DB9X
DB8X
DB7X
DB6X
DB5X
DB4X
DB3X
DB2X
DB1X
DB0X
CKEXTX
DVDD
BLK BLK
AVDD
BLK BLK
TP7
TP10
RCOM
2R13R24R35R46R57R68R79
1
1
2
3
4
R1
R3
R2
RCOM
TP8
TP9
RP5
R8
R9
50
10
RP3 22
RP3 22
RP3 22
3
RP3 22
4
RP3 22
5
RP3 22
6
RP3 22
7
RP3 22
8
RP4 22
1
RP4 22
2
RP4 22
3
RP4 22
4
RP4 22
5
RP4 22
6
RP4 22
7
RP4 22
8
5
6
9
8
7
10
RP6
R7
R8
R5
R4
R9
R6
50
RCOM
1
161
152
14
13
12
11
10
9
16
15
14
13
12
11
10
9
1
RCOM
2R13R24R35R46R57R68R79
2
3
5
6
4
R1
R2
7
R3
R5
R4
R6
RP1
R8
R9
50
10
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
CKEXT
9
8
10
RP2
R7
R8
R9
50
Figure 17. Evaluation Board: Power Supply and Digital Inputs
REV. 0
–15–
AD9744
AVDD
DVDD
CKEXT
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
AVDD
CLOCK
DVDD
AVDD
R3
10k⍀
CUT
UNDER DUT
JP6
R5
10k⍀
TP1
WHT
REF
R1
2k⍀
DVDD
R4
50⍀
TP3
WHT
C11
0.1F
CLOCK
AVDD
S5
C1
0.1F
R2
10k⍀
DVDD
JP2
MODE
C2
0.1F
JP10
IOUTA
OPT
S1
1
S2
R6
1
IX
IOUTB
IY
A
B
2
2
AB
JP11
C13
10pF
C12
10pF
3
R11
50⍀
JP8
T1
T1-1T
JP9
4
5
6
3
2
1
R10
50⍀
3
IOUT
S3
C14
+
+
1
2
3
4
5
6
7
8
9
10
11
12
13
14
10F
16V
C15
10F
16V
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
EXT
C16
0.1F
C18
0.1F
AD9744
2
AB
JP5
REF
JP4
RESERVED
U1
3
INT
C17
0.1F
C19
0.1F
CLOCK
DVDD
DCOM
MODE
AVDD
IOUTA
IOUTB
ACO M
FS ADJ
REFIO
REFLO
SLEEP
SLEEP
NC
TP11
WHT
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Figure 18. Evaluation Board: Output Signal Conditioning
–16–
REV. 0
AD9744
Figure 19. Primary Side
REV. 0
Figure 20. Secondary Side
–17–
AD9744
Figure 21. Ground Plane
Figure 22. Power Plane
–18–
REV. 0
AD9744
Figure 23. Assembly – Primary Side
REV. 0
Figure 24. Assembly – Secondary Side
–19–
AD9744
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm)
28-Lead Standard Small Outline Package (SOIC)
(R-28)
0.7125 (18.10)
0.6969 (17.70)
0.0118 (0.30)
0.0040 (0.10)
0.177 (4.50)
0.169 (4.30)
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
28
1
PIN 1
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
15
14
0.1043 (2.65)
0.0926 (2.35)
SEATING
PLANE
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
0.3937 (10.00)
0.0125 (0.32)
0.0091 (0.23)
0.0291 (0.74)
0.0098 (0.25)
0.0500 (1.27)
8ⴗ
0.0157 (0.40)
0ⴗ
28-Lead Thin Shrink SO Package (TSSOP)
(RU-28)
0.386 (9.80)
0.378 (9.60)
28
1
PIN 1
0.0256 (0.65)
BSC
0.0118 (0.30)
0.0075 (0.19)
15
14
0.256 (6.50)
0.246 (6.25)
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
8ⴗ
0ⴗ
C02913–0–5/02(0)
ⴛ 45ⴗ
0.028 (0.70)
0.020 (0.50)
–20–
PRINTED IN U.S.A.
REV. 0
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