ANALOG DEVICES AD9744 Service Manual
14-Bit, 210 MSPS
K
FEATURES
High performance member of pin-compatible
TxDAC product family
Excellent spurious-free dynamic range performance
SFDR to Nyquist
83 dBc @ 5 MHz output
80 dBc @ 10 MHz output
73 dBc @ 20 MHz output
SNR @ 5 MHz output, 125 MSPS: 77 dB
Twos complement or straight binary data format
Differential current outputs: 2 mA to 20 mA
Power dissipation: 135 mW @ 3.3 V
Power-down mode: 15 mW @ 3.3 V
On-chip 1.2 V reference
CMOS-compatible digital interface
28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP packages
Edge-triggered latches
TxDAC
®
D/A Converter
APPLICATIONS
Wideband communication transmit channel
Direct IFs
Base stations
Wireless local loops
Digital radio links
Direct digital synthesis (DDS)
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
3.3V
R
SET
CLOC
0.1µF
3.3V
1.2V REF
REFIO
FS ADJ
DVDD
DCOM
CLOCK
REFLO
SEGMENTED
SWITCHES
150pF
LATCHES
AVDD ACOM
CURRENT
SOURCE
ARRAY
LSB
SWITCHES
AD9744
AD9744
IOUTA
IOUTB
MODE
GENERAL DESCRIPTION
The AD97441 is a 14-bit resolution, wideband, third generation
member of the TxDAC series of high performance, low power
CMOS digital-to-analog converters (DACs). The TxDAC family, consisting of pin-compatible 8-, 10-, 12-, and 14-bit DACs,
is specifically optimized for the transmit signal path of communication systems. All of the devices share the same interface
options, small outline package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost. The AD9744 offers exceptional
ac and dc performance while supporting update rates up to
210 MSPS.
The AD9744’s low power dissipation makes it well suited for
portable and low power applications. Its power dissipation can
be further reduced to a mere 60 mW with a slight degradation
in performance by lowering the full-scale current output. Also,
a power-down mode reduces the standby power dissipation to
approximately 15 mW. A segmented current source architecture
is combined with a proprietary switching technique to reduce
spurious components and enhance dynamic performance.
SLEEP
DIGITAL DATA INPUTS (DB13–DB0)
Figure 1.
Edge-triggered input latches and a 1.2 V temperature compensated band gap reference have been integrated to provide a
complete monolithic DAC solution. The digital inputs support
3 V CMOS logic families.
PRODUCT HIGHLIGHTS
1. The AD9744 is the 14-bit member of the pin compatible TxDAC
family, which offers excellent INL and DNL performance.
2. Data input supports twos complement or straight binary data
coding.
3. High speed, single-ended CMOS clock input supports
210 MSPS conversion rate.
4. Low power: Complete CMOS DAC function operates on
135 mW from a 2.7 V to 3.6 V single supply. The DAC fullscale current can be reduced for lower power operation, and a
sleep mode is provided for low power idle periods.
5. On-chip voltage reference: The AD9744 includes a 1.2 V
temperature compensated band gap voltage reference.
6. Industry-standard 28-lead SOIC, 28-lead TSSOP, and 32-lead
LFCSP packages.
1
Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519.
02913-001
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113 ©2005 Analog Devices, Inc. All rights reserved.
www.analog.com
AD9744
TABLE OF CONTENTS
Specifications..................................................................................... 3
REVISION HISTORY
DC Specifications ......................................................................... 3
Dynamic Specifications ............................................................... 4
Digital Specifications ................................................................... 5
Absolute Maximum Ratings............................................................ 6
Thermal Characteristics .............................................................. 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Te r mi n ol o g y ...................................................................................... 8
Typical Performance Characteristics ............................................. 9
Functional Description .................................................................. 13
Reference Operation ..................................................................13
Reference Control Amplifier .................................................... 13
DAC Transfer Function ............................................................. 14
Analog Outputs........................................................................... 14
Digital Inputs ..............................................................................15
Clock Input.................................................................................. 15
DAC Timing................................................................................ 16
Power Dissipation....................................................................... 16
Applying the AD9744 ................................................................ 17
Differential Coupling Using a Transformer............................ 17
Differential Coupling Using an Op Amp................................ 17
Single-Ended Unbuffered Voltage Output .............................. 18
Single-Ended, Buffered Voltage Output Configuration........ 18
Power and Grounding Considerations, Power Supply
Rejection
Evaluation Board ............................................................................ 20
General Description................................................................... 20
Outline Dimensions ....................................................................... 30
...................................................................................... 18
4/05—Rev. A to Rev. B
Updated Format.................................................................. Universal
Changes to General Description .....................................................1
Changes to Product Highlights .......................................................1
Changes to DC Specifications..........................................................3
Changes to Dynamic Specifications................................................4
Changes to Pin Function Description ............................................7
Changes to Figure 6 and Figure 9....................................................9
Inserted New Figure 10; Renumbered Sequentially .....................9
Changes to Figure 12, Figure 13, Figure 14, and Figure 15....... 10
Changes to Figure 22 Caption ...................................................... 11
Inserted New Figure 23; Renumbered Sequentially .................. 11
Changes to Functional Description ............................................. 13
Changes to Reference Operation Section.................................... 13
Added Figure 25; Renumbered Sequentially.............................. 13
Changes to Digital Inputs Section................................................ 15
Changes to Figure 31 and Figure 32............................................. 16
Updated Outline Dimensions....................................................... 30
Changes to Ordering Guide.......................................................... 31
5/03—Rev. 0 to Rev. A
Added 32-Lead LFCSP Package .......................................Universal
Edits to Features.................................................................................1
Edits to Product Highlights..............................................................1
Edits to DC Specifications................................................................2
Edits to Dynamic Specifications......................................................3
Edits to Digital Specifications..........................................................4
Edits to Absolute Maximum Ratings..............................................5
Edits to Thermal Characteristics.....................................................5
Edits to Ordering Guide...................................................................5
Edits to Pin Configuration...............................................................6
Edits to Pin Function Descriptions.................................................6
Edits to Figure 2.................................................................................7
Replaced TPCs 1, 4, 7, and 8............................................................8
Edits to Figure 3.............................................................................. 10
Edits to Functional Description ................................................... 10
Added Clock Input Section........................................................... 12
Added Figure 7................................................................................ 12
Edits to DAC Timing Section ....................................................... 12
Edits to Sleep Mode Operation Section....................................... 13
Edits to Power Dissipation Section .............................................. 13
Renumbered Figures 8 to Figure 26............................................. 13
Added Figure 11 ............................................................................. 13
Added Figure 27 to Figure 35 ....................................................... 21
Updated Outline Dimensions....................................................... 26
Ordering Guide........................................................................... 31
Rev. B | Page 2 of 32
AD9744
SPECIFICATIONS
DC SPECIFICATIONS
T
to T
MIN
Table 1.
Parameter Min Typ Max Unit
RESOLUTION 14 Bits
DC ACCURACY1
Integral Linearity Error (INL) −5 ±0.8 +5 LSB
Differential Nonlinearity (DNL) −3 ±0.5 +3 LSB
ANALOG OUTPUT
Offset Error −0.02 +0.02 % of FSR
Gain Error (Without Internal Reference) −0.5 ±0.1 +0.5 % of FSR
Gain Error (With Internal Reference) −0.5 ±0.1 +0.5 % of FSR
Full-Scale Output Current2 2 20 mA
Output Compliance Range −1 +1.25 V
Output Resistance 100 kΩ
Output Capacitance 5 pF
REFERENCE OUTPUT
Reference Voltage 1.14 1.20 1.26 V
Reference Output Current3 100 nA
REFERENCE INPUT
Input Compliance Range 0.1 1.25 V
Reference Input Resistance (External Reference) 7 kΩ
Small Signal Bandwidth 0.5 MHz
TEMPERATURE COEFFICIENTS
Offset Drift 0 ppm of FSR/°C
Gain Drift (Without Internal Reference) ±50 ppm of FSR/°C
Gain Drift (With Internal Reference) ±100 ppm of FSR/°C
Reference Voltage Drift ±50 ppm/°C
POWER SUPPLY
Supply Voltages
Analog Supply Current (I
Digital Supply Current (I
Clock Supply Current (I
Supply Current Sleep Mode (I
Power Dissipation4 135 145 mW
Power Dissipation5 145 mW
Power Supply Rejection Ratio—AVDD6 −1 +1 % of FSR/V
Power Supply Rejection Ratio—DVDD6 −0.04 +0.04 % of FSR/V
OPERATING RANGE −40 +85 °C
1
Measured at IOUTA, driving a virtual ground.
2
Nominal full-scale current, I
3
An external buffer amplifier with input bias current <100 nA should be used to drive any external load.
4
Measured at f
5
Measured as unbuffered voltage output with I
6
±5% power supply variation.
, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I
MAX
= 20 mA, unless otherwise noted.
OUTFS
AVDD 2.7 3.3 3.6 V
DVDD 2.7 3.3 3.6 V
CLKVDD 2.7 3.3 3.6 V
) 33 36 mA
AVDD
)4 8 9 mA
DVDD
) 5 6 mA
CLKVDD
) 5 6 mA
AVDD
= 25 MSPS and f
CLOCK
, is 32 times the I
OUTFS
= 1 MHz.
OUT
current.
REF
= 20 mA and 50 Ω R
OUTFS
at IOUTA and IOUTB, f
LOAD
= 100 MSPS and f
CLOCK
= 40 MHz.
OUT
Rev. B | Page 3 of 32
AD9744
DYNAMIC SPECIFICATIONS
T
to T
MIN
terminated, unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit
DYNAMIC PERFORMANCE
Maximum Output Update Rate (f
Output Settling Time (tST) (to 0.1%)1 11 ns
Output Propagation Delay (tPD) 1 ns
Glitch Impulse 5 pV-s
Output Rise Time (10% to 90%)1 2.5 ns
Output Fall Time (10% to 90%)1 2.5 ns
Output Noise (I
Output Noise (I
Noise Spectral Density3 −155 dBm/Hz
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
Spurious-Free Dynamic Range Within a Window
Total Harmonic Distortion
Signal-to-Noise Ratio
, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I
MAX
) 210 MSPS
CLOCK
= 20 mA)2 50 pA/√Hz
OUTFS
= 2 mA)2 30 pA/√Hz
OUTFS
f
= 25 MSPS; f
CLOCK
= 1.00 MHz
OUT
= 20 mA, differential transformer coupled output, 50 Ω doubly
OUTFS
0 dBFS Output 77 90 dBc
−6 dBFS Output 87 dBc
−12 dBFS Output 82 dBc
−18 dBFS Output 82 dBc
f
= 65 MSPS; f
CLOCK
f
= 65 MSPS; f
CLOCK
f
= 65 MSPS; f
CLOCK
f
= 65 MSPS; f
CLOCK
f
= 65 MSPS; f
CLOCK
f
= 165 MSPS; f
CLOCK
f
= 165 MSPS; f
CLOCK
f
= 210 MSPS; f
CLOCK
f
= 210 MSPS; f
CLOCK
f
= 25 MSPS; f
CLOCK
f
= 50 MSPS; f
CLOCK
f
= 65 MSPS; f
CLOCK
f
= 125 MSPS; f
CLOCK
f
= 25 MSPS; f
CLOCK
f
= 50 MSPS; f
CLOCK
f
= 65 MSPS; f
CLOCK
f
= 125 MSPS; f
CLOCK
f
= 65 MSPS; f
CLOCK
f
= 65 MSPS; f
CLOCK
f
= 125 MSPS; f
CLOCK
f
= 125 MSPS; f
CLOCK
f
= 165 MSPS; f
CLOCK
f
= 165 MSPS; f
CLOCK
f
= 210 MSPS; f
CLOCK
f
= 210 MSPS; f
CLOCK
= 1.00 MHz 85 dBc
OUT
= 2.51 MHz 84 dBc
OUT
= 10 MHz 80 dBc
OUT
= 15 MHz 75 dBc
OUT
= 25 MHz 74 dBc
OUT
= 21 MHz 73 dBc
OUT
= 41 MHz 60 dBc
OUT
= 41 MHz 68 dBc
OUT
= 69 MHz 64 dBc
OUT
= 1.00 MHz; 2 MHz Span 84 90 dBc
OUT
= 5.02 MHz; 2 MHz Span 90 dBc
OUT
= 5.03 MHz; 2.5 MHz Span 87 dBc
OUT
= 5.04 MHz; 4 MHz Span 87 dBc
OUT
= 1.00 MHz −86 −77 dBc
OUT
= 2.00 MHz −77 dBc
OUT
= 2.00 MHz −77 dBc
OUT
= 2.00 MHz −77 dBc
OUT
= 5 MHz; I
OUT
= 5 MHz; I
OUT
= 5 MHz; I
OUT
= 5 MHz; I
OUT
= 5 MHz; I
OUT
= 5 MHz; I
OUT
= 5 MHz; I
OUT
= 5 MHz; I
OUT
= 20 mA 82 dB
OUTFS
= 5 mA 88 dB
OUTFS
= 20 mA 77 dB
OUTFS
= 5 mA 78 dB
OUTFS
= 20 mA 70 dB
OUTFS
= 5 mA 70 dB
OUTFS
= 20 mA 74 dB
OUTFS
= 5 mA 67 dB
OUTFS
Rev. B | Page 4 of 32
AD9744
Parameter Min Typ Max Unit
Multitone Power Ratio (8 Tones at 400 kHz Spacing)
f
= 78 MSPS; f
CLOCK
0 dBFS Output 66 dBc
−6 dBFS Output 68 dBc
−12 dBFS Output 62 dBc
−18 dBFS Output 61 dBc
1
Measured single-ended into 50 Ω load.
2
Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only.
3
Noise spectral density is the average noise power normalized to a 1 Hz bandwidth, with the DAC converting and producing an output tone.
DIGITAL SPECIFICATIONS
T
to T
MIN
Table 3.
Parameter Min Typ Max Unit
DIGITAL INPUTS1
Logic 1 Voltage 2.1 3 V
Logic 0 Voltage 0 0.9 V
Logic 1 Current −10 +10 µA
Logic 0 Current −10 +10 µA
Input Capacitance 5 pF
Input Setup Time (tS) 2.0 ns
Input Hold Time (tH) 1.5 ns
Latch Pulse Width (t
CLK INPUTS2
Input Voltage Range 0 3 V
Common-Mode Voltage 0.75 1.5 2.25 V
Differential Voltage 0.5 1.5 V
1
Includes CLOCK pin on SOIC/TSSOP packages and CLK+ pin on LFCSP package in single-ended clock input mode.
2
Applicable to CLK+ and CLK– inputs when configured for differential or PECL clock input mode.
, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I
MAX
= 15.0 MHz to 18.2 MHz
OUT
= 20 mA, unless otherwise noted.
OUTFS
) 1.5 ns
LPW
DB0–DB13
CLOCK
IOUTA
OR
IOUTB
t
S
t
PD
0.1%
t
H
t
LPW
t
ST
0.1%
02913-002
Figure 2. Timing Diagram
Rev. B | Page 5 of 32
AD9744
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter With Respect to Min Max Unit
AVDD ACOM −0.3 +3.9 V
DVDD DCOM −0.3 +3.9 V
CLKVDD CLKCOM −0.3 +3.9 V
ACOM DCOM −0.3 +0.3 V
ACOM CLKCOM −0.3 +0.3 V
DCOM CLKCOM −0.3 +0.3 V
AVDD DVDD −3.9 +3.9 V
AVDD CLKVDD −3.9 +3.9 V
DVDD CLKVDD −3.9 +3.9 V
CLOCK, SLEEP DCOM −0.3 DVDD + 0.3 V
Digital Inputs, MODE DCOM −0.3 DVDD + 0.3 V
IOUTA, IOUTB ACOM −1.0 AVDD + 0.3 V
REFIO, REFLO, FS ADJ ACOM −0.3 AVDD + 0.3 V
CLK+, CLK−, CMODE CLKCOM −0.3 CLKVDD + 0.3 V
Junction Temperature 150 °C
Storage Temperature −65 +150 °C
Lead Temperature (10 sec) 300 °C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability.
THERMAL CHARACTERISTICS
1
Thermal Resistance
28-Lead 300-Mil SOIC
= 55.9°C/W
θ
JA
28-Lead TSSOP
= 67.7°C/W
θ
JA
32-Lead LFCSP
θ
= 32.5°C/W
JA
1
Thermal impedance measurements were taken on a 4-layer board in still air, in accordance with EIA/JESD51-7.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
Rev. B | Page 6 of 32
AD9744
)
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
B
(MSB) DB13
(LSB) DB0
1
DB12
2
3
DB11
4
DB10
5
DB9
6
DB8
7
DB7
8
DB6
9
DB5
10
DB4
11
DB3
12
DB2
13
DB1
14
NC = NO CONNECT
AD9744
TOP VIEW
(Not to Scale)
Figure 3. 28-Lead SOIC and TSSOP
28
CLOCK
DVDD
27
26
DCOM
25
MODE
24
AVDD
23
RESERVED
22
IOUTA
21
IOUTB
20
ACOM
19
NC
18
FS ADJ
17
REFIO
16
REFLO
15
SLEEP
02913-003
DB7 1
DB6 2
DVDD 3
DB5 4
DB4 5
DB3 6
DB2 7
DB1 8
NC = NO CONNECT
8
B
D
2
3
(Not to Scale)
9
0
B
D
)
B
S
L
(
Figure 4. 32-Lead LFCSP
Table 5. Pin Function Descriptions
SOIC/TSSOP
Pin No.
LFCSP
Pin No. Mnemonic Description
1 27 DB13 Most Significant Data Bit (MSB).
2 to 13
28 to 32,
1, 2, 4 to 8
DB12 to
DB1
Data Bits 12 to 1.
14 9 DB0 Least Significant Data Bit (LSB).
15 25 SLEEP
Power-Down Control Input. Active high. Contains active pull-down circuit; it may be left
unterminated if not used.
16 N/A REFLO
Reference Ground when Internal 1.2 V Reference Used. Connect to ACOM for both internal
and external reference operation modes.
17 23 REFIO
Reference Input/Output. Serves as reference input when using external reference. Serves as
1.2 V reference output when using internal reference. Requires 0.1 µF capacitor to ACOM
when using internal reference.
18 24 FS ADJ Full-Scale Current Output Adjust.
19 N/A NC No Internal Connection.
20 19, 22 ACOM Analog Common.
21 20 IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s.
22 21 IOUTA DAC Current Output. Full-scale current when all data bits are 1s.
23 N/A RESERVED Reserved. Do not connect to common or supply.
24 17, 18 AVDD Analog Supply Voltage (3.3 V).
25 16 MODE Selects Input Data Format. Connect to DCOM for straight binary, DVDD for twos complement.
N/A 15 CMODE
Clock Mode Selection. Connect to CLKCOM for single-ended clock receiver (drive CLK+ and
float CLK−). Connect to CLKVDD for differential receiver. Float for PECL receiver (terminations
on-chip).
26 10, 26 DCOM Digital Common.
27 3 DVDD Digital Supply Voltage (3.3 V).
28 N/A CLOCK Clock Input. Data latched on positive edge of clock.
N/A 12 CLK+ Differential Clock Input.
N/A 13 CLK− Differential Clock Input.
N/A 11 CLKVDD Clock Supply Voltage (3.3 V).
N/A 14 CLKCOM Clock Common.
1
0
1
1
9
B
B
B
D
D
D
9
0
1
2
3
3
PIN 1
INDICATOR
AD9744
TOP VIEW
1
0
2
1
1
1
+
D
M
K
D
O
L
V
C
C
K
D
L
C
S
M
(
P
M
3
2
E
1
1
O
E
B
B
C
L
D
S
D
D
7
5
8
6
2
2
2
2
24 FS ADJ
23 REFIO
22 ACOM
21 IOUTA
20 IOUTB
19 ACOM
18 AVDD
17 AVDD
6
3
4
5
1
1
1
1
–
E
E
M
K
D
D
O
L
O
O
C
C
M
M
K
L
C
C
02913-004
Rev. B | Page 7 of 32
AD9744
TERMINOLOGY
Linearity Error (Also Called Integral Nonlinearity or INL)
It is defined as the maximum deviation of the actual analog
output from the ideal output, determined by a straight line
drawn from zero to full scale.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called the offset error. For IOUTA, 0 mA output is expected
when the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Temp er at u re D ri ft
It is specified as the maximum change from the ambient (25°C)
value to the value at either T
MIN
or T
. For offset and gain
MAX
drift, the drift is reported in ppm of full-scale range (FSR)
per °C. For reference drift, the drift is reported in ppm per °C.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal. It is
expressed as a percentage or in decibels (dB).
Multitone Power Ratio
The spurious-free dynamic range containing multiple carrier
tones of equal amplitude. It is measured as the difference
between the rms amplitude of a carrier tone to the peak spurious signal in the region of a removed tone.
3.3V
DVDD
DCOM
0.1µF
R
SET
2kΩ
50Ω
RETIMED
CLOCK
OUTPUT*
LECROY 9210
PULSE GENERATOR
3.3V
REFIO
FS ADJ
DVDD
DCOM
CLOCK
SLEEP
REFLO
1.2V REF
SEGMENTED SWITCHES
FOR DB13–DB5
CLOCK
OUTPUT
150pF
LATCHES
DIGITAL
DATA
TEKTRONIX AWG-2021
WITH OPTION 4
AVDD ACOM
PMOS
CURRENT SOURCE
ARRAY
LSB
SWITCHES
AD9744
IOUTA
IOUTB
MODE
Figure 5. Basic AC Characterization Test Set-Up (SOIC/TSSOP Packages)
Rev. B | Page 8 of 32
50Ω
MINI-CIRCUITS
T1-1T
50Ω
*AWG2021 CLOCK RETIMED
SO THAT THE DIGITAL DATA
TRANSITIONS ON FALLING EDGE
OF 50% DUTY CYCLE CLOCK.
RHODE & SCHWARZ
FSEA30
SPECTRUM
ANALYZER
02913-005
AD9744
TYPICAL PERFORMANCE CHARACTERISTICS
95
210MSPS (LFCSP)
90
85
80
75
210MSPS
70
65
SFDR (dBc)
60
55
50
45
1 10 100
65MSPS
125MSPS (LFCSP)
Figure 6. SFDR vs . f
165MSPS
f
OUT
125MSPS
(MHz)
165MSPS (LFCSP)
@ 0 dBFS
OUT
02913-006
95
90
85
80
75
70
65
SFDR (dBc)
–12dBFS
60
55
50
45
Figure 9. SFDR vs . f
–6dBFS (LFCSP)
–12dBFS (LFCSP)
0dBFS
–6dBFS
20 30010 405060
f
(MHz)
OUT
@ 165 MSPS
OUT
0dBFS (LFCSP)
02913-007
95
90
85
80
75
70
65
SFDR (dBc)
60
55
50
45
0 5 10 15 20 25
0dBFS
f
OUT
Figure 7. SFDR vs . f
95
90
85
80
75
70
65
SFDR (dBc)
60
55
50
45
0 5 10 15 20 25 30 35 40 45
f
OUT
Figure 8. SFDR vs . f
(MHz)
OUT
–6dBFS
(MHz)
OUT
–6dBFS
@ 65 MSPS
0dBFS
@ 125 MSPS
–12dBFS
–12dBFS
02913-009
02913-012
95
90
85
80
75
70
65
SFDR (dBc)
60
55
50
45
95
90
85
80
75
70
65
SFDR (dBc)
60
55
50
45
0dBFS (LFCSP)
–6dBFS (LFCSP)
–12dBFS (LFCSP)
0dBFS
–12dBFS
01020304050607080
f
(MHz)
OUT
Figure 10. SFDR vs. f
20mA
0 5 10 15 20 25
f
(MHz)
OUT
Figure 11. SFDR vs. f
OUT
and I
OUTFS
–6dBFS
@ 210 MSPS
OUT
10mA
5mA
@ 65 MSPS and 0 dBFS
02913-055
02913-010
Rev. B | Page 9 of 32
AD9744
95
90
85
210MSPS (LFCSP)
80
75
70
65
SFDR (dBc)
60
55
50
45
–25 –20 –15 –10 –5 0
210MSPS
Figure 12. Single-Tone SFDR vs. A
165MSPS
A
OUT
65MSPS
(dBFS)
OUT
@ f
125MSPS
= f
OUT
CLOCK
/11
02913-013
95
65MSPS (8.3,10.3)
90
85
80
75
70
65
SFDR (dBc)
125MSPS (16.9, 18.9)
60
55
50
45
–25 –20 –15 –10 –5 0
210MSPS (29,31)
Figure 15. Dual-Tone IMD vs. A
165MSPS (22.6, 24.6)
210MSPS (29,31)
LFCSP
(dBFS)
A
OUT
78MSPS (10.1, 12.1)
@ f
= f
OUT
OUT
CLOCK
/7
02913-014
95
90
85
80
75
70
65
SFDR (dBc)
60
55
50
45
–25 –20 –15 –10 –5 0
65MSPS
125MSPS
125MSPS (LFCSP)
210MSPS (LFCSP)
(dBFS)
A
OUT
Figure 13. Single-Tone SFDR vs. A
90
85
80
75
70
SNR (dB)
65
60
55
50
I
FS = 20mA LFCSP
OUT
I
FS = 20mA
OUT
I
FS = 10mA
OUT
I
FS = 5mA
OUT
0 30 60 90 120 150 180 210
f
(MSPS)
CLOCK
Figure 14. SNR vs. f
CLOCK
and I
OUTFS
165MSPS (LFCSP)
165MSPS
@ f
OUT
OUT
I
FS = 10mA LFCSP
OUT
I
FS = 5mA LFCSP
OUT
@ f
= 5 MHz and 0 dBFS
OUT
210MSPS
= f
CLOCK
1.5
1.0
0.5
0
ERROR (LSB)
–0.5
–1.0
–1.5
0
02913-008
/5
1.0
0.8
0.6
0.4
0.2
0
–0.2
ERROR (LSB)
–0.4
–0.6
–0.8
–1.0
0 4096
02913-011
4096 8192 12288 16384
CODE
Figure 16. Typical INL
8192 12288 16384
CODE
02913-015
02913-018
Figure 17. Typical DNL
Rev. B | Page 10 of 32
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