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AD9740-EB
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Analog Devices AD9740ARU, AD9740AR, AD9740-EB Datasheet

a
10-Bit, 165 MSPS
TxDAC
®
D/A Converter
FEATURES High-Performance Member of Pin-Compatible
TxDAC Product Family Excellent Spurious-Free Dynamic Range Performance SNR @ 5 MHz Output, 125 MSPS: 65 dB Two’s Complement or Straight Binary Data Format Differential Current Outputs: 2 mA to 20 mA Power Dissipation: 135 mW @ 3.3 V Power-Down Mode: 15 mW @ 3.3 V On-Chip 1.20 V Reference CMOS-Compatible Digital Interface Package: 28-Lead SOIC and TSSOP Packages Edge-Triggered Latches
APPLICATIONS Wideband Communication Transmit Channel:
Direct IF
Base Stations
Wireless Local Loop
Digital Radio Link
Direct Digital Synthesis (DDS)
Instrumentation

PRODUCT DESCRIPTION

The AD9740 is a 10-bit resolution, wideband, third generation member of the TxDAC series of high-performance, low power CMOS digital-to-analog converters (DACs). The TxDAC family, consisting of pin-compatible 8-, 10-, 12-, and 14-bit DACs, is specifically optimized for the transmit signal path of communica­tion systems. All of the devices share the same interface options, small outline package, and pinout, providing an upward or down­ward component selection path based on performance, resolution, and cost. The AD9740 offers exceptional ac and dc performance while supporting update rates up to 165 MSPS.
The AD9740’s low power dissipation makes it well suited for portable and low power applications. Its power dissipation can be further reduced to a mere 60 mW with a slight degradation in performance by lowering the full-scale current output. Also, a power-down mode reduces the standby power dissipation to approximately 15 mW. A segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. Edge­triggered input latches and a 1.2 V temperature compensated band gap reference have been integrated to provide a complete monolithic DAC solution. The digital inputs support 3 V CMOS logic families.
*
MODE

FUNCTIONAL BLOCK DIAGRAM

REFLO
0.1␮F
R
SET
3.3V
CLOCK
PRODUCT HIGHLIGHTS
+1.20V REF REFIO FS ADJ
DVDD
DCOM
CLOCK
SLEEP
SEGMENTED
SWITCHES
DIGITAL DATA INPUTS (DB9–DB0)
150pF
LATCHES
AD9740
3.3V
AVDD
LSB
SWITCH
AD9740
CURRENT
SOURCE
ARRAY
ACOM
IOUTA
IOUTB
1. The AD9740 is the 10-bit member of the pin-compatible TxDAC family that offers excellent INL and DNL performance.
2. Data input supports two’s complement or straight binary data coding.
3. High-speed, single-ended CMOS clock input supports 165 MSPS conversion rate.
4. Low power: Complete CMOS DAC function operates on 135 mW from a 3.0 V to 3.6 V single supply. The DAC full­scale current can be reduced for lower power operation, and a sleep mode is provided for low power idle periods.
5. On-chip voltage reference: The AD9740 includes a 1.2 V temperature-compensated band gap voltage reference.
6. Industry standard 28-lead SOIC and TSSOP packages.
TxDAC is a registered trademark of Analog Devices, Inc.
* Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519.
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
AD9740
(T
to T
DC SPECIFICATIONS
MIN
, AVDD = 3.3 V, DVDD = 3.3 V, I
MAX
Parameter Min Typ Max Unit
RESOLUTION 10 Bits
DC ACCURACY
1
Integral Linearity Error (INL) –0.7 ± 0.15 +0.7 LSB Differential Nonlinearity (DNL) –0.5 ± 0.12 +0.5 LSB
ANALOG OUTPUT
Offset Error –0.02 +0.02 % of FSR Gain Error (Without Internal Reference) –2 ±0.1 +2 % of FSR Gain Error (With Internal Reference) –2 ±0.1 +2 % of FSR Full-Scale Output Current
2
Output Compliance Range –1.0 +1.25 V Output Resistance 100 kΩ Output Capacitance 5 pF
REFERENCE OUTPUT
Reference Voltage 1.14 1.20 1.26 V Reference Output Current
3
REFERENCE INPUT
Input Compliance Range 0.1 1.25 V Reference Input Resistance (Ext. Ref) 1 MΩ Small Signal Bandwidth 0.5 MHz
TEMPERATURE COEFFICIENTS
Offset Drift 0 ppm of FSR/°C Gain Drift (Without Internal Reference) ±50 ppm of FSR/°C Gain Drift (With Internal Reference) ±100 ppm of FSR/°C Reference Voltage Drift ±50 ppm/°C
POWER SUPPLY
Supply Voltages
AVDD 2.7 3.3 3.6 V
DVDD 2.7 3.3 3.6 V Analog Supply Current (I Digital Supply Current (I Supply Current Sleep Mode (I Power Dissipation Power Dissipation
4
5
Power Supply Rejection Ratio—AVDD Power Supply Rejection Ratio—DVDD
)3336mA
AVDD
4
)
DVDD
)56mA
AVDD
6
6
OPERATING RANGE –40 +85 °C
NOTES
1
Measured at IOUTA, driving a virtual ground.
2
Nominal full-scale current, I
3
An external buffer amplifier with input bias current <100 nA should be used to drive any external load.
4
Measured at f
5
Measured as unbuffered voltage output with I
6
±5% power supply variation.
Specifications subject to change without notice.
= 25 MSPS and f
CLOCK
, is 32 times the I
OUTFS
OUT
= 1.0 MHz.
OUTFS
current.
REF
= 20 mA and 50 Ω R
at IOUTA and IOUTB, f
LOAD
= 20 mA, unless otherwise noted.)
OUTFS
2.0 20.0 mA
100 nA
89 mA
135 145 mW
145 mW –1 +1 % of FSR/V –0.04 +0.04 % of FSR/V
= 100 MSPS and f
CLOCK
= 40 MHz.
OUT
–2–
REV. 0
(T
to T
DYNAMIC SPECIFICATIONS
MIN
, AVDD = 3.3 V, DVDD = 3.3 V, I
MAX
Output, 50 ⍀ Doubly terminated, unless otherwise noted.)
= 20 mA, Differential Transformer Coupled
OUTFS
Parameter Min Typ Max Unit
DYNAMIC PERFORMANCE
Maximum Output Update Rate (f Output Settling Time (t Output Propagation Delay (t
) (to 0.1%)
ST
)1ns
PD
Glitch Impulse 5 pV-s Output Rise Time (10% to 90%) Output Fall Time (10% to 90%) Output Noise (I Output Noise (I Noise Spectral Density
OUTFS
OUTFS
= 20 mA) = 2 mA)
3
2
) 165 MSPS
CLOCK
1
1
1
2
11 ns
2.5 ns
2.5 ns 50 pA/√Hz 30 pA/√Hz –143 dBm/Hz
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
= 25 MSPS; f
f
CLOCK
= 1.00 MHz
OUT
0 dBFS Output 71 79 dBc –6 dBFS Output 75 dBc –12 dBFS Output 67 dBc –18 dBFS Output 61 dBc
= 65 MSPS; f
f
CLOCK
= 65 MSPS; f
f
CLOCK
f
= 65 MSPS; f
CLOCK
= 65 MSPS; f
f
CLOCK
= 65 MSPS; f
f
CLOCK
f
= 165 MSPS; f
CLOCK
= 165 MSPS; f
f
CLOCK
= 1.00 MHz 84 dBc
OUT
= 2.51 MHz 80 dBc
OUT
= 10 MHz 78 dBc
OUT
= 15 MHz 76 dBc
OUT
= 25 MHz 75 dBc
OUT
= 21 MHz 70 dBc
OUT
= 41 MHz 60 dBc
OUT
Spurious-Free Dynamic Range within a Window
= 25 MSPS; f
f
CLOCK
f
= 50 MSPS; f
CLOCK
= 65 MSPS; f
f
CLOCK
= 125 MSPS; f
f
CLOCK
= 1.00 MHz; 2 MHz Span 80 dBc
OUT
= 5.02 MHz; 2 MHz Span 90 dBc
OUT
= 5.03 MHz; 2.5 MHz Span 90 dBc
OUT
= 5.04 MHz; 4 MHz Span 90 dBc
OUT
Total Harmonic Distortion
= 25 MSPS; f
f
CLOCK
= 50 MSPS; f
f
CLOCK
f
= 65 MSPS; f
CLOCK
= 125 MSPS; f
f
CLOCK
= 1.00 MHz –79 –71 dBc
OUT
= 2.00 MHz –77 dBc
OUT
= 2.00 MHz –77 dBc
OUT
= 2.00 MHz –77 dBc
OUT
Signal-to-Noise Ratio
= 65 MSPS; f
f
CLOCK
= 65 MSPS; f
f
CLOCK
= 125 MSPS; f
f
CLOCK
f
= 125 MSPS; f
CLOCK
= 165 MSPS; f
f
CLOCK
= 165 MSPS; f
f
CLOCK
= 5 MHz; I
OUT
= 5 MHz; I
OUT
= 5 MHz; I
OUT
= 5 MHz; I
OUT
= 5 MHz; I
OUT
= 5 MHz; I
OUT
= 20 mA 70 dB
OUTFS
= 5 mA 81 dB
OUTFS
= 20 mA 65 dB
OUTFS
= 5 mA 76 dB
OUTFS
= 20 mA 64 dB
OUTFS
= 5 mA 71 dB
OUTFS
Multitone Power Ratio (8 Tones at 400 kHz Spacing)
= 78 MSPS; f
f
CLOCK
= 15.0 MHz to 18.2 MHz
OUT
0 dBFS Output 65 dBc –6 dBFS Output 66 dBc –12 dBFS Output 60 dBc –18 dBFS Output 55 dBc
NOTES
1
Measured single-ended into 50 Ω load.
2
Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only.
3
Noise spectral density is the average noise power normalized to a 1 Hz bandwidth, with the DAC converting and producing an output tone.
Specifications subject to change without notice.
AD9740
REV. 0
–3–
AD9740
DIGITAL SPECIFICATIONS
(T
to T
MIN
, AVDD = 3.3 V, DVDD = 3.3 V, I
MAX
= 20 mA, unless otherwise noted.)
OUTFS
Parameter Min Typ Max Unit
DIGITAL INPUTS
Logic “1” Voltage 2.1 3 V Logic “0” Voltage 0 0.9 V Logic “1” Current –10 +10 µA Logic “0” Current –10 +10 µA Input Capacitance 5 pF Input Setup Time (t Input Hold Time (t Latch Pulsewidth (t
) 2.0 ns
S
) 1.5 ns
H
) 1.5 ns
LPW
DB0–DB11
CLOCK
IOUTA
OR
IOUTB
t
S
t
PD
0.1%
t
H
t
LPW
t
ST
0.1%
Figure 1. Timing Diagram

ABSOLUTE MAXIMUM RATINGS*

With
Parameter Respect to Min Max Unit
AVDD ACOM –0.3 +3.9 V DVDD DCOM –0.3 +3.9 V ACOM DCOM –0.3 +0.3 V AVDD DVDD –3.9 +3.9 V
Model Range Description Options*
AD9740AR –40°C to +85°C 28-Lead 300 Mil SOIC R-28 AD9740ARU –40°C to +85°C 28-Lead TSSOP RU-28 AD9740-EB Evaluation Board
*R = Small Outline IC; RU = Thin Shrink Small Outline Package

ORDERING GUIDE

Temperature Package Package
CLOCK, SLEEP DCOM –0.3 DVDD + 0.3 V Digital Inputs DCOM –0.3 DVDD + 0.3 V IOUTA, IOUTB ACOM –1.0 AVDD + 0.3 V REFIO, REFLO, FSADJ ACOM –0.3 AVDD + 0.3 V Junction Temperature 150 °C Storage Temperature –65 +150 °C Lead Temperature (10 sec) 300 °C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability.

THERMAL CHARACTERISTICS

Thermal Resistance
28-Lead 300-Mil SOIC
␪JA= 71.4°C/W
28-Lead TSSOP
␪JA= 97.9°C/W

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9740 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
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PIN CONFIGURATION
AD9740
(MSB) DB9
(LSB) DB0
1
DB8
2
DB7
3
4
DB6
DB5
5
DB4
6
TOP VIEW
(Not to Scale)
DB3
7
8
DB2
9
DB1
10
NC
11
12
NC
13
NC
NC
14
NC = NO CONNECT
AD9740
CLOCK
28
DVDD
27
26
DCOM
25
MODE
AVDD
24
23
RESERVED
IOUTA
22
21
IOUTB
20
ACOM
19
NC
FS ADJ
18
REFIO
17
REFLO
16
SLEEP
15
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Description
1 DB9 Most Significant Data Bit (MSB) 2–9 DB8–DB1 Data Bits 8–1 10 DB0 Least Significant Data Bit (LSB) 11–14 NC No Internal Connection 15 SLEEP Power-Down Control Input. Active high. Contains active pull-down circuit; it may be left
unterminated if not used. 16 REFLO Reference Ground when internal 1.2 V reference used. Connect to AVDD to disable internal reference. 17 REFIO Reference Input/Output. Serves as reference input when internal reference disabled (i.e., tie REFLO to AVDD).
Serves as 1.2 V reference output when internal reference activated (i.e., tie REFLO to AGND). Requires
0.1 µF capacitor to AGND when internal reference activated.
18 FS ADJ Full-Scale Current Output Adjust 19 NC No Internal Connection 20 ACOM Analog Common 21 IOUTB Complementary DAC Current Output. Full-scale current when all data bits are 0s. 22 IOUTA DAC Current Output. Full-scale current when all data bits are 1s. 23 RESERVED Reserved. Do Not Connect to Common or Supply. 24 AVDD Analog Supply Voltage (3.3 V) 25 MODE Selects Input Data Format. Connect to DGND for straight binary, DVDD for two’s complement. 26 DCOM Digital Common 27 DVDD Digital Supply Voltage (3.3 V) 28 CLOCK Clock Input. Data latched on positive edge of clock.
REV. 0
–5–
AD9740
DEFINITIONS OF SPECIFICATIONS Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A D/A converter is monotonic if the output either increases or remains constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is called the offset error. For IOUTA, 0 mA output is expected when the inputs are all 0s. For IOUTB, 0 mA output is expected when all inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown resulting in nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the ambient (25°C) value to the value at either T
MIN
or T
MAX
. For
offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per °C. For reference drift, the drift is reported in ppm per °C.
Power Supply Rejection
The maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages.
Settling Time
The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth.
Total Harmonic Distortion
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. It is expressed as a percentage or in decibels (dB).
Multitone Power Ratio
The spurious-free dynamic range containing multiple carrier tones of equal amplitude. It is measured as the difference between the rms amplitude of a carrier tone to the peak spurious signal in the region of a removed tone.
DVDD
DCOM
R
SET
2k⍀
RETIMED
CLOCK
OUTPUT*
LECROY 9210
PULSE GENERATOR
0.1␮F
3.3V
50⍀
1.20V REF
REFIO
FS ADJ
DVDD
DCOM
CLOCK
SLEEP
3.3V
REFLO
150pF
AVDD ACOM
AD9740
PMOS
CURRENT SOURCE
ARRAY
SEGMENTED SWITCHES
FOR DB9–DB1
CLOCK
OUTPUT
LATCHES
DIGITAL
DATA
TEKTRONIX
AWG-2021
W/OPTION 4
LSB
SWITCH
IOUTA
IOUTB
MODE
50⍀
Figure 2. Basic AC Characterization Test Setup
MINI-CIRCUITS
100⍀
50⍀
20pF
20pF
* AWG2021 CLOCK RETIMED SUCH THAT DIGITAL DATA TRANSITIONS ON FALLING EDGE OF 50% DUTY CYCLE CLOCK.
T1–1T
ROHDE & SCHWARZ FSEA30 SPECTRUM ANALYZER
–6–
REV. 0
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