ANALOG DEVICES AD9739 Service Manual

14-Bit, 2.5 GSPS,

Data Sheet

FEATURES

Direct RF synthesis at 2.5 GSPS update rate

DC to 1.25 GHz in baseband mode

1.25 GHz to 3.0 GHz in mix mode

Industry leading single/multicarrier IF or RF synthesis

f

= 350 MHz, ACLR =80 dBc

OUT

f

= 950 MHz, ACLR = 78 dBc

OUT

f

= 2100 MHz, ACLR = 69 dBc

OUT

Dual-port LVDS data interface

Up to 1.25 GSPS operation

Source synchronous DDR clocking
Pin-compatible with the AD9739A
Multichip synchronization capability
Programmable output current: 8.7 mA to 31.7 mA
Low power: 1.16 W at 2.5 GSPS

APPLICATIONS

Broadband communications systems
Military jammers
Instrumentation, automatic test equipment
Radar, avionics

GENERAL DESCRIPTION

The AD9739 is a 14-bit, 2.5 GSPS high performance RF digital­to-analog converter (DAC) capable of synthesizing wideband
signals from dc up to 3.0 GHz. Its DAC core features a quad­switch architecture that provides exceptionally low distortion
performance with an industry-leading direct RF synthesis
capability. This feature enables multicarrier generation up to
the Nyquist frequency in baseband mode as well as second and
third Nyquist zones in mix mode. The output current can be
programmed over the 8.66 mA to 31.66 mA range.

The inclusion of on-chip controllers simplifies system integration.
A dual-port, source synchronous, LVDS interface simplifies the
digital interface with existing FGPA/ASIC technology. On-chip
controllers are used to manage external and internal clock domain
variations over temperature to ensure reliable data transfer from
the host to the DAC core. Multichip synchronization is possible
with an on-chip synchronization controller. A serial peripheral
interface (SPI) is used for device configuration as well as readback
of status registers.

The AD9739 is manufactured on a 0.18 µm CMOS process and
operates from 1.8 V and 3.3 V supplies. It is supplied in a 160-ball
chip scale ball grid array for reduced package parasitics.

RF Digital-to-Analog Converter

AD9739

FUNCTIONAL BLOCK DIAGRAM

RESET

SDIO

SDO

CS

SCLK

DCI

DCO

SYNC_OUT

SYNC_IN

DB0[13:0]DB1[13:0]

SPI

LVDS DDR

DATA

CONTRO LLER

LVDS DDR

CLK DISTRIBUT ION

(DIV-BY-4)

SYNC-

CONTRO LLER

PRODUCT HIGHLIGHTS

1. Ability to synthesize high quality wideband signals with

bandwidths of up to 1.25 GHz in the first or second
Nyquist zone.

2. A proprietary quad-switch DAC architecture provides

exceptional ac linearity performance while enabling mix
mode operation.

3. A dual-port, double data rate, LVDS interface supports the

maximum conversion rate of 2500 MSPS.

4. On-chip controllers manage external and internal clock

domain skews.

5. A multichip synchronization capability.

6. Programmable differential current output with a 8.66 mA

to 31.66 mA range.

RECEIVER

RECEIVER

Figure 1.

IRQ

AD9739

DAC BIAS

4-TO-1

DATA ASSEMBLER



1.2V

VREF

I120

TxDAC

CORE

DATA

LATCH

DLL

DACCLK

IOUTP

IOUTN

(MU CONTROL LER)

07851-001

Rev. B

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: [phone] www.analog.com
Fax: [phone] ©2009–2012 Analog Devices, Inc. All rights reserved.

AD9739 Data Sheet

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 4

DC Specifications ......................................................................... 4

LVDS Digital Specifications........................................................ 5

Serial Port Specifications............................................................. 6

AC Specifications.......................................................................... 7

Absolute Maximum Ratings............................................................ 8

Thermal Resistance ...................................................................... 8

ESD Caution.................................................................................. 8

Pin Configurations and Function Descriptions ........................... 9

Typical Performance Characteristics ........................................... 12

AC (Normal Mode).................................................................... 12

AC (Mix Mode) ..........................................................................15

Terminology .................................................................................... 17

Serial Port Interface (SPI) Register............................................... 18

SPI Register Map Description................................................... 18

SPI Operation.............................................................................. 18

SPI Register Map............................................................................. 20

SPI Port Configuration and Software Reset............................ 22

Power-Down LVDS Interface and TxDAC®............................ 22

Controller Clock Disable........................................................... 22

Interrupt Request (IRQ) Enable/Status ................................... 22

TxDAC Full-Scale Current Setting (I

TxDAC Quad-Switch Mode of Operation.............................. 23

) and Sleep ........... 23

OUTFS

DCI Phase Alignment Status .................................................... 23

SYNC_IN Phase Alignment Status.......................................... 23

Data Receiver Controller Configuration................................. 23

Data Receiver Controller_Data Sample Delay Value ............ 24

Data and Sync Receiver Controller_DCI Delay

Value/Window and Phase Rotation......................................... 24

Data Receiver Controller_Delay Line Status and Sync

Controller SYNC_OUT Status ................................................. 24

Sync and Data Receiver Controller Lock/Tracking Status.... 25

CLK Input Common Mode ...................................................... 25

Mu Controller Configuration and Status................................ 25

Part ID ......................................................................................... 26

Theory of Operation ...................................................................... 27

LVDS Data Port Interface.......................................................... 28

Mu Controller............................................................................. 32

Interrupt Requests...................................................................... 34

Multiple Device Synchronization............................................. 35

Analog Interface Considerations.................................................. 38

Analog Modes of Operation ..................................................... 38

Clock Input Considerations...................................................... 39

Voltage Reference ....................................................................... 40

Analog Outputs .......................................................................... 40

Nonideal Spectral Artifacts....................................................... 43

Lab Evaluation of the AD9739 ................................................. 44

Power Dissipation and Supply Domains................................. 44

Recommended Start-Up Sequence.......................................... 45

Outline Dimensions....................................................................... 48

Ordering Guide .......................................................................... 48





REVISION HISTORY

1/12—Rev. A to Rev. B

Changes to Features Section, Applications Section, General

Description Section, Figure 1, Product Highlights Section ........ 1

Changes to DC Specifications Section........................................... 4

Changed Digital Specifications Section to LVDS Digital

Specifications Section....................................................................... 5

Changes to LVDS Digital Specifications Section ......................... 5

Added Serial Port Specifications Section and Table 3;

Renumbered Sequentially................................................................ 6

Changes to AC Specifications Section........................................... 7

Changes to Table 5............................................................................ 8

Changes to Table 7.......................................................................... 10

Rev. B | Page 2 of 48

Deleted Static Linearity Section and Figure 7 to Figure 17;

Renumbered Sequentially ............................................................. 11

Changed Dynamic Performance Normal Mode, 20 mA Full
Scale (Unless Otherwise Noted) Section to AC (Normal Mode)

Section.............................................................................................. 12

Changes to AC (Normal Mode) Section ..................................... 12

Changed Dynamic Performance Mix Mode, 20 mA Full Scale

Section to AC (Mix Mode) Section.............................................. 15

Changes to AC (Mix Mode) Section............................................ 15

Added Serial Port Interface (SPI) Register Section, SPI Register
Map Description Section, Reset Section, Table 8, and SPI

Operation Section and Figure 34 ................................................. 18

Data Sheet AD9739

Deleted DOCSIS Performance Section and

Figure 46 to Figure 72.....................................................................19

Added Figure 35 through Figure 38; Renumbered Sequentially.... 19

Changes to SPI Register Map Section and Table 9......................20

Added SPI Port Configuration and Software Reset Section,
Power-Down LVDS Interface and TxDAC® Section, Controller
Clock Disable Section, Interrupt Request (IRQ) Enable/Status

Section, and Table 10 to Table 13 ..................................................22

Added TxDAC Full-Scale Current Setting (I

) and Sleep

OUTFS

Section, TxDAC Quad-Switch Mode of Operation Section, DCI
Phase Alignment Status Section, SYNC_IN Phase Alignment
Status Section, Data Receiver Controller Configuration Section,

and Table 14 to Table 18 .................................................................23

Added Data Receiver Controller_Data Sample Delay Value
Section, Data and Sync Receiver Controller_DCI Delay
Value/Window and Phase Rotation Section, Data Receiver
Controller_Delay Line Status and Sync Controller SYNC_OUT

Status Section, and Table 19 to Table 21.......................................24

Deleted Serial Peripheral Interface Section, General Operation
of the Serial Interface Section, Instruction Mode (8-Bit Instruction)

Section, and Serial Interface Port Pin Description Section .......25

Added Sync and Data Receiver Controller Lock/Tracking Status
Section, CLK Input Common Mode Section, Mu Controller

Configuration and Status Section, and Table 22 to Table 24.....25

Deleted MSB/LSB Transfers Section, Serial Port Configuration

Section, and Figure 74 to Figure 79 ..............................................26

Added Part ID Section and Table 25 ............................................26

Changes to Theory of Operation Section ....................................27

Added Figure 39 ..............................................................................27

Deleted SPI Registers Section and Table 8 to Table 31...............28

Moved and Changes to LVDS Data Port Interface Section .......28

Added Figure 40 and Figure 41 .....................................................28

Changes to Figure 42 ......................................................................29

Moved and Changes to Figure 43..................................................29

Added Data Receiver Controller Initialization Description
Section, Table 26, and Data Receiver Operation at Lower Clock

Rates Section ....................................................................................30

Added LVDS Driver and Receiver Input Section, Figure 44 to

Figure 47, and Table 27...................................................................31

Changed and Moved Mu Delay Controller Section to Mu

Controller Section...........................................................................32

Changes to Mu Controller Section, Figure 48, and Figure 49...32

Added Figure 50 and Table 28 .......................................................32

Added Mu Controller Initialization Description Section..........33

Changes to Interrupt Requests Section........................................34

Added Table 29 ................................................................................34

Changed Synchronization Controller Section to Multiple

Device Synchronization Section....................................................35

Added Figure 52 ..............................................................................35

Changes to Figure 53 ......................................................................36

Added Sync Controller Initialization Description Section........36

Added Synchronization Limitations Section...............................37

Changed Applications Information to Analog Interface

Considerations Section...................................................................38

Changes to Analog Modes of Operation Section .......................38

Deleted Clocking the AD9739 Section, Figure 85, and Figure 86..39
Added Clock Input Considerations Section, Figure 58 to

Figure 60...........................................................................................39

Deleted Clock Phase Noise Affects on AC Performance Section,
Table 32 to Table 34, Applying Data to the AD9739 Section, and

Figure 87...........................................................................................40

Moved Figure 61..............................................................................40

Changes to Voltage References Section and Analog Outputs

Section ..............................................................................................40

Added Equivalent DAC Output and Transfer Function and

Figure 63...........................................................................................40

Deleted Mu Control Operation Section, Search Mode Section,

and Figure 89 ................................................................................... 41

Moved Figure 64..............................................................................41

Added Peak DAC Output Power Capability Section and Figure 65. 41
Deleted Figure 90, Figure 91, Track Mode Section, Mu Delay
and Phase Readback Section, Operating the Mu Controller
Manually Section, and Calculating Mu Delay Line Step Size

Section ..............................................................................................42

Added Output Stage Configuration Section and Figure 66 to

Figure 70...........................................................................................42

Added Nonideal Spectral Artifacts Section, Figure 71, and

Table 30.............................................................................................43

Deleted Operation in Master Mode, Figure 93, and

Figure 94...........................................................................................44

Added Lab Evaluation of the AD9739 Section, Power Dissipation

and Supply Domains Section, and Figure 72 to Figure 74......... 44

Deleted Figure 95, Operation in Slave Mode Section, and Data

Receiver Operation in Auto Mode Section.................................. 45

Changes to Recommended Start-Up Sequence Section ............45

Added Figure 75..............................................................................45

Deleted Figure 97, Data Receiver Operation in Manual Mode
Section, Calculating the DCI Delay Line Step Size Section, and

Maximum Allowable Data Timing Skew/Jitter Section.............46

Added Table 31 ................................................................................ 46

Deleted Optimizing the Clock Common-Mode Voltage Section,
Figure 99, Analog Control Registers Section, Mirror Roll-Off

Frequency Control Section, and Figure 101................................47

Added Table 32 ................................................................................ 47

Deleted Figure 103, Figure 104, and Figure 106 .........................48

Updated Outline Dimensions........................................................48

Deleted Figure 107 to Figure 109..................................................49

Deleted Table 35 to Table 44.......................................................... 50

7/11—Rev 0 to Rev A

Changes to Table 2, DAC CLOCK INPUT (DACCLK_P,

DACCLK_N), Added DAC Clock Rate .........................................4

Changes to Table 3, Added Dynamic Performance Parameters....... 5

Change to Ordering Guide ............................................................ 53

2/09—Revision 0: Initial Release

Rev. B | Page 3 of 48

AD9739 Data Sheet

SPECIFICATIONS

DC SPECIFICATIONS

VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, I

Table 1.

Parameter Min Typ Max Unit

RESOLUTION 14 Bits
ACCURACY

Integral Nonlinearity (INL) ±1.3 LSB
Differential Nonlinearity (DNL) ±0.8 LSB

ANALOG OUTPUTS

Gain Error (with Internal Reference) 5.5 %
Full-Scale Output Current 8.66 20.2 31.66 mA
Output Compliance Range −1.0 +1.0 V
Common-Mode Output Resistance 10 MΩ
Differential Output Resistance 70 Ω
Output Capacitance 1 pF

DAC CLOCK INPUT (DACCLK_P, DACCLK_N)

Differential Peak-to-Peak Voltage 1.2 1.6 2.0 V
Common-Mode Voltage 900 mV
DAC Clock Rate 0.8 2.5 GHz

TEMPERATURE DRIFT

Gain 60 ppm/°C
Reference Voltage 20 ppm/°C

REFERENCE

Internal Reference Voltage 1.15 1.2 1.25 V
Output Resistance 5 kΩ

ANALOG SUPPLY VOLTAGES

VDDA 3.1 3.3 3.5 V
VDDC 1.70 1.8 1.90 V

DIGITAL SUPPLY VOLTAGES

VDD33 3.10 3.3 3.5 V
VDD 1.70 1.8 1.90 V

SUPPLY CURRENTS AND POWER DISSIPATION, 2.0 GSPS

I

37 38 mA

VDDA

I

159 166 mA

VDDC

I

34 37 mA

VDD33

I

233 238 mA

VDD

Power Dissipation 0.940 0.975 W
Sleep Mode, I

2.5 2.75 mA

VDDA

Power-Down Mode (Register 0x01 = 0x33 and Register 0x02 = 0x80)

I

0.02 mA

VDDA

I

3.8 mA

VDDC

I

0.5 mA

VDD33

I

0.1 mA

VDD

SUPPLY CURRENTS AND POWER DISSIPATION, 2.5 GSPS

I

37 mA

VDDA

I

223 mA

VDDC

I

34 mA

VDD33

I

290 mA

VDD

Power Dissipation 1.16 W

OUTFS

= 20 mA.

Rev. B | Page 4 of 48

Data Sheet AD9739

LVDS DIGITAL SPECIFICATIONS

VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, I
1996 reduced range link, unless otherwise noted.

Table 2.

Parameter Min Typ Max Unit

LVDS DATA INPUTS (DB0[13:0], DB1[13:0])1

Input Common-Mode Voltage Range, V

Logic High Differential Input Threshold, V

Logic Low Differential Input Threshold, V

825 1575 mV

COM

175 400 mV

IH_DTH

−175 −400 mV

IL_DTH

Receiver Differential Input Impedance, RIN 80 120 Ω

Input Capacitance 1.2 pF

LVDS Input Rate 1250 MSPS

LVDS Minimum Data Valid Period, t

(See Figure 41) 344 ps

VALI D

LVDS CLOCK INPUT (DCI and SYNC_IN)2

Input Common-Mode Voltage Range, V

Logic High Differential Input Threshold, V

Logic Low Differential Input Threshold, V

825 1575 mV

COM

175 400 mV

IH_DTH

−175 −400 mV

IL_DTH

Receiver Differential Input Impedance, RIN 80 120 Ω

Input Capacitance 1.2 pF

Maximum Clock Rate 625 MHz

LVDS CLOCK OUTPUT (DCO and SYNC_OUT)3

Output Voltage High (x_P or x_N) 1375 mV

Output Voltage Low (x_P or x_N) 1025 mV

Output Differential Voltage, |VOD| 150 200 250 mV

Output Offset Voltage, VOS 1150 1250 mV

Output Impedance, Single-Ended, RO 80 100 120 Ω

RO Single-Ended Mismatch 10 %

Maximum Clock Rate 625 MHz

1

DB0[x]P, DB0[x]N, DB1[x]P, and DB1[x]N pins.

2

DCI_P and DCI_N pins, as well as SYNC_IN_P and SYNC_IN_N pins.

3

DCO_P and DCO_N pins, as well as SYNC_OUT_P/SYNC_OUT_N pins with 100 Ω differential termination.

= 20 mA. LVDS drivers and receivers are compliant to the IEEE Standard 1596.3-

OUTFS

Rev. B | Page 5 of 48

AD9739 Data Sheet

SERIAL PORT SPECIFICATIONS

VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V.

Tabl e 3

.

Parameter Min Typ Max Unit

WRITE OPERATION (See Figure 36)

SCLK Clock Rate, f
SCLK Clock High, tHI 18 ns
SCLK Clock Low, t
SDIO to SCLK Setup Time, tDS 2 ns
SCLK to SDIO Hold Time, tDH 1 ns
CS to SCLK Setup Time, tS

SCLK to CS Hold Time, tH

READ OPERATION (See Figure 37 and Figure 38)

SCLK Clock Rate, f
SCLK Clock High, tHI 18 ns
SCLK Clock Low, t
SDIO to SCLK Setup Time, tDS 2 ns
SCLK to SDIO Hold Time, tDH 1 ns
CS to SCLK Setup Time, tS
SCLK to SDIO (or SDO) Data Valid Time, tDV 15 ns
CS to SDIO (or SDO) Output Valid to High-Z, tEZ

INPUTS (SDIO, SCLK, CS)

Voltage in High, VIH 2.0 3.3 V
Voltage in Low, VIL 0 0.8 V
Current in High, IIH −10 +10 μA
Current in Low, IIL −10 +10 μA

OUTPUT (SDIO)

Voltage Out High, VOH 2.4 3.5 V
Voltage Out Low, VOL 0 0.4 V
Current Out High, IOH 4 mA
Current Out Low, IOL 4 mA

(or /t

SCLK

18 ns

LOW

) 20 MHz

SCLK

3 ns
2 ns

(or /t

SCLK

18 ns

LOW

) 20 MHz

SCLK

3 ns

2 ns

Rev. B | Page 6 of 48

Data Sheet AD9739

AC SPECIFICATIONS

VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, I

Table 4.

Parameter Min Typ Max Unit

DYNAMIC PERFORMANCE

DAC Clock Rate 800 2500 MSPS

Adjusted DAC Update Rate1 800 2500 MSPS

Output Settling Time (tst) to 0.1% 13 ns

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

f

= 100 MHz 69.5 dBc

OUT

f

= 350 MHz 58.5 dBc

OUT

f

= 550 MHz 54 dBc

OUT

f

= 950 MHz 60 dBc

OUT

TWO-TONE INTERMODULATION DISTORTION (IMD), f

f

= 100 MHz 94 dBc

OUT

f

= 350 MHz 78 dBc

OUT

f

= 550 MHz 72 dBc

OUT

f

= 950 MHz 68 dBc

OUT

NOISE SPECTRAL DENSITY (NSD), 0 dBFS SINGLE TONE

f

= 100 MHz −166 dBm/Hz

OUT

f

= 350 MHz −161 dBm/Hz

OUT

f

= 550 MHz −160 dBm/Hz

OUT

f

= 850 MHz −160 dBm/Hz

OUT

WCDMA ACLR (SINGLE CARRIER), ADJACENT/ALTERNATE ADJACENT CHANNEL

f

= 2457.6 MSPS f

DAC

f

= 2457.6 MSPS, f

DAC

f

= 2457.6 MSPS, f

DAC

f

= 2457.6 MSPS, f

DAC

1

Adjusted DAC updated rate is calculated as f

with f

= 2500 MSPS, f

DAC

= 350 MHz 80/80 dBc

OUT

= 950 MHz 78/79 dBc

OUT

= 1700 MHz (Mix Mode) 74/74 dBc

OUT

= 2100 MHz (Mix Mode) 69/72 dBc

OUT

divided by the minimum required interpolation factor. For the AD9739, the minimum interpolation factor is 1. Thus,

adjusted = 2500 MSPS.

DAC

DAC

= 20 mA, f

OUTFS

= f

OUT2

= 2400 MSPS.

DAC

+ 1.25 MHz

OUT1

Rev. B | Page 7 of 48

AD9739 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 5.

With

Parameter

VDDA VSSA −0.3 V to +3.6 V
VDD33 VSS −0.3 V to +3.6 V
VDD VSS −0.3 V to +1.98 V
VDDC VSSC −0.3 V to +1.98 V
VSSA VSS −0.3 V to +0.3 V
VSSA VSSC −0.3 V to +0.3 V
VSS VSSC −0.3 V to +0.3 V
DACCLK_P, DACCLK_N VSSC −0.3 V to VDDC + 0.18 V
DCI, DCO, SYNC_IN,

SYNC_OUT
LVDS Data Inputs VSS −0.3 V to VDD33 + 0.3 V
IOUTP, IOUTN VSSA −1.0 V to VDDA + 0.3 V
I120, VREF VSSA −0.3 V to VDDA + 0.3 V
IRQ, CS, SCLK, SDO,

SDIO, RESET
Junction Temperature 150°C
Storage Temperature −65°C to +150°C

Respect To

VSS −0.3 V to VDD33 + 0.3 V

VSS −0.3 V to VDD33 + 0.3 V

Rating

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 6. Thermal Resistance

Package Type θJA θ

160-Ball CSP_BGA 31.2 7.0 °C/W1

1

With no airflow movement.

Unit

JC

ESD CAUTION

Rev. B | Page 8 of 48

Data Sheet AD9739

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1413121110876321954

1413121110876321954

A

B

C

D

E

F

G

H

J

K

L

M

N

P

VDDA, 3.3V, ANALOG SUPPLY

VSSA, ANALOG SUPPLY GROUND

VSSA SHIELD, ANALOG SUPPLY GROUND SHIE LD

Figure 2. Analog Supply Pins (Top View)

A

B

C

D

E

F

G

H

J

K

L

M

N

P

VDD, 1.8V, DIGITAL SUPPLY

VSS DIGITAL SUPPLY GROUND

VDD33, 3.3V DIGITAL SUPPLY

Figure 3. Digital Supply Pins (Top View)

A

B

C

D

E

F

G

H

J

K

L

M

N

P

VDDC, 1.8V, CLOCK SUPPLY

VSSC, CLOCK SUPPLY GROUND

07851-002

07851-004

Figure 4. Digital LVDS Clock Supply Pins (Top View)

1413121110876321954

A

B

DACCLK_N

DACCLK_ P

SYNC_OUT_P/_N

SYNC_IN_P/_N

DB1[0:13]P

DB1[0:13]N

DB0[0:13]P

DB0[0:13]N

07851-003

C

D

E

F

G

H

J

K

L

M

N

P

DIFFERENTIAL INPUT SIGNAL (CLOCK OR DATA)

Figure 5. Digital LVDS Input, Clock I/O (Top View)

1413121110876321954

DCO_P/_N

DCI_P/_N

07851-005

Rev. B | Page 9 of 48

AD9739 Data Sheet

IOUTN

IOUTP

1413121110876321954

A

B

C

D

E

F

G

H

J

K

L

M

N

P

Figure 6. Analog I/O and SPI Control Pins (Top View)

I120

VREF

IPTAT

IRQ

SCLK

CS

RESET

SDIO

SDO

07851-006

Table 7. AD9739 Pin Function Descriptions

Pin No. Mnemonic Description

C1, C2, D1, D2, E1, E2, E3, E4 VDDC 1.8 V Clock Supply Input.
A1, A2, A3, A4, A5, B1, B2, B3, B4, B5, C4,

VSSC

Clock Supply Return.

C5, D4, D5
A10, A11, B10, B11, C10, C11, D10, D11 VDDA
A12, A13, B12, B13, C12, C13, D12, D13, VSSA
A6, A9, B6, B9, C6, C9, D6, D9, F1, F2, F3,

VSSA Shield

3.3 V Analog Supply Input.
Analog Supply Return.
Analog Supply Return Shield. Tie to VSSA at the DAC.

F4, E11, E12, E13, E14, F11, F12
A14 NC
A7, B7, C7, D7 IOUTN
A8, B8, C8, D8 IOUTP
B14 I120

No Connect. Do not connect to this pin.
DAC Negative Current Output Source.
DAC Positive Current Output Source.
Nominal 1.2 V Reference. Tie to analog ground via a 10 kΩ

resistor to generate a 120 μA reference current.

C14 VREF

Voltage Reference Input/Output. Decouple to VSSA with a

1 nF capacitor.
D14 NC
C3, D3 DACCLK_N/DACCLK_P
F13 IRQ

Factory Test Pin. Do not connect to this pin.

Negative/Positive DAC Clock Input (DACCLK).

Interrupt Request Open Drain Output. Active high. Pull up to

VDD33 with a 10 kΩ resistor.
F14 RESET
G13

CS
G14 SDIO
H13 SCLK
H14 SDO
J3, J4, J11, J12 VDD33
G1, G2, G3, G4, G11, G12 VDD
H1, H2, H3, H4, H11, H12, K3, K4, K11, K12 VSS
J1, J2 SYNC_OUT_P/SYNC_OUT_N
K1, K2 SYNC_IN_P/SYNC_IN_N
J13, J14 DCO_P/DCO_N
K13, K14 DCI_P/DCI_N
L1, M1 DB1[0]P/DB1[0]N
L2, M2 DB1[1]P/DB1[1]N
L3, M3 DB1[2]P/DB1[2]N
L4, M4 DB1[3]P/DB1[3]N
L5, M5 DB1[4]P/DB1[4]N

Reset Input. Active high. Tie to VSS if unused.
Serial Port Enable Input.
Serial Port Data Input/Output.
Serial Port Clock Input.
Serial Port Data Output.

3.3 V Digital Supply Input.

1.8 V Digital Supply. Input.
Digital Supply Return.
Positive/Negative SYNC Output (SYNC_OUT)
Positive/Negative SYNC Input (SYNC_IN)
Positive/Negative Data Clock Output (DCO).
Positive/Negative Data Clock Input (DCI).
Port 1 Positive/Negative Data Input Bit 0.
Port 1 Positive/Negative Data Input Bit 1.
Port 1 Positive/Negative Data Input Bit 2.
Port 1 Positive/Negative Data Input Bit 3.
Port 1 Positive/Negative Data Input Bit 4.

L6, M6 DB1[5]P/DB1[5]N Port 1 Positive/Negative Data Input Bit 5.

Rev. B | Page 10 of 48

Data Sheet AD9739

Pin No. Mnemonic Description

L7, M7 DB1[6]P/DB1[6]N Port 1 Positive/Negative Data Input Bit 6.
L8, M8 DB1[7]P/DB1[7]N Port 1 Positive/Negative Data Input Bit 7.
L9, M9 DB1[8]P/DB1[8]N Port 1 Positive/Negative Data Input Bit 8.
L10, M10 DB1[9]P/DB1[9]N Port 1 Positive/Negative Data Input Bit 9.
L11, M11 DB1[10]P/DB1[10]N Port 1 Positive/Negative Data Input Bit 10.
L12, M12 DB1[11]P/DB1[11]N Port 1 Positive/Negative Data Input Bit 11.
L13, M13 DB1[12]P/DB1[12]N Port 1 Positive/Negative Data Input Bit 12.
L14, M14 DB1[13]P/DB1[13]N Port 1 Positive/Negative Data Input Bit 13.
N1, P1 DB0[0]P/DB0[0]N Port 0 Positive/Negative Data Input Bit 0.
N2, P2 DB0[1]P/DB0[1]N Port 0 Positive/Negative Data Input Bit 1.
N3, P3 DB0[2]P/DB0[2]N Port 0 Positive/Negative Data Input Bit 2.
N4, P4 DB0[3]P/DB0[3]N Port 0 Positive/Negative Data Input Bit 3.
N5, P5 DB0[4]P/DB0[4]N Port 0 Positive/Negative Data Input Bit 4.
N6, P6 DB0[5]P/DB0[5]N Port 0 Positive/Negative Data Input Bit 5.
N7, P7 DB0[6]P/DB0[6]N Port 0 Positive/Negative Data Input Bit 6.
N8, P8 DB0[7]P/DB0[7]N Port 0 Positive/Negative Data Input Bit 7.
N9, P9 DB0[8]P/DB0[8]N Port 0 Positive/Negative Data Input Bit 8.
N10, P10 DB0[9]P/DB0[9]N Port 0 Positive/Negative Data Input Bit 9.
N11, P11 DB0[10]P/DB0[10]N Port 0 Positive/Negative Data Input Bit 10.
N12, P12 DB0[11]P/DB0[11]N Port 0 Positive/Negative Data Input Bit 11.
N13, P13 DB0[12]P/DB0[12]N Port 0 Positive/Negative Data Input Bit 12.
N14, P14 DB0[13]P/DB0[13]N Port 0 Positive/Negative Data Input Bit 13.

Rev. B | Page 11 of 48

AD9739 Data Sheet

–

–

TYPICAL PERFORMANCE CHARACTERISTICS

AC (NORMAL MODE)

I

= 20 mA, nominal supplies, 25°C, unless otherwise noted.

OUTFS

10dB/DIV

Figure 7. Single-Tone Spectrum at f

80

1.2GSPS

75

70

65

60

2.4GSPS

55

50

SFDR (dBc)

45

40

35

30

0 100 200 300 400 500 60 0 700 800 900 1000 1100 1200

2.0GSPS

Figure 8. SFDR vs. f

150

–152

–154

–156

–158

–160

–162

NSD (dBm/Hz)

–164

–166

–168

–170

0 100 200 300 400 500 600 700 800 900 1000 1100 1200

Figure 9. Single-Tone NSD over f

VBW 10kHz

1.6GSPS

f

f

OUT

OUT

OUT

(MHz)

OUT

1.2GSPS

(MHz)

= 91 MHz, f

over f

DAC

2.4GSPS

OUT

STOP 2.4GHzSTART 20MHz

= 2.4 GSPS

DAC

10dB/DIV

STOP 2.4GHzSTART 20MHz

2.4GSPS

VBW 10kHz

1.2GSPS

f

OUT

1.2GSPS

f

OUT

= 1091 MHz, f

OUT

2.4GSPS

(MHz)

over f

OUT

(MHz)

2.0GSPS

DAC

OUT

DAC

= 2.4 GSPS

1100 1200

07851-010

07851-011

07851-012

07851-007

Figure 10. Single-Tone Spectrum at f

100

95

90

85

80

75

1.6GSPS

70

65

60

IMD (dBc)

55

50

45

40

35

30

0 100 200 300 400 500 600 700 800 900 1000

07851-008

Figure 11. IMD vs. f

160

–161

–162

–163

–164

–165

–166

NSD (dBm/Hz)

–167

–168

–169

–170

0 100 200 300 400 500 600 700 800 900 1000 1100 1200

07851-009

Figure 12. Eight-Tone NSD over f

Rev. B | Page 12 of 48

Data Sheet AD9739

f

= 2 GSPS, I

DAC

90

= 20 mA, nominal supplies, 25°C, unless otherwise noted.

OUTFS

110

80

70

60

SFDR (dBc)

50

40

30

0 100 200 300 400 500 600 700 800 900 1000

Figure 13. SFDR vs. f

90

80

70

60

SFDR (dB)

50

0dBFS

–6dBFS

f

(MHz)

OUT

over Digital Full Scale

OUT

–6dBFS

0dBFS

–3dBFS

–3dBFS

100

90

80

70

IMD (dBc)

60

50

40

30

0 100 200 300 400 500 600 700 800 900 1000

f

(MHz)

07851-013

Figure 16. IMD vs. f

90

80

70

60

SFDR (dB)

50

0dBFS

OUT

over Digital Full Scale

OUT

–6dBFS

–3dBFS

–6dBFS

–3dBFS

0dBFS

07851-016

40

30

0 100 200 300 400 500 600 700 800 900 1000

f

(MHz)

OUT

Figure 14. SFDR for Second Harmonic over f

90

80

70

60

SFDR (dBc)

50

40

30

0 100 200 300 400 500 600 700 800 900 1000

10mA FS

20mA FS

f

OUT

Figure 15. SFDR vs. f

(MHz)

OUT

vs. Digital Full Scale

OUT

30mA FS

over DAC I

OUTFS

40

30

0 100 200 300 400 500 600 700 800 900 1000

f

(MHz)

10mA FS

f

OUT

OUT

(MHz)

over DAC I

OUT

vs. Digital Full Scale

OUT

30mA FS

OUTFS

07851-014

Figure 17. SFDR for Third Harmonic over f

110

100

90

80

70

IMD (dBc)

60

50

40

30

0 100 200 300 400 500 600 700 800 900 1000

07851-015

20mA FS

Figure 18. IMD vs. f

7851-017

07851-018

Rev. B | Page 13 of 48

AD9739 Data Sheet

–

–

–

90

110

80

70

–40°C

+85°C

60

SFDR (dBc)

50

+25°C

40

30

0 100 200 300 400 500 600 700 800 900 1000

f

(MHz)

OUT

Figure 19. SFDR vs. f

over Temperature

OUT

150

–152

–154

–156

–158

–40°C

–160

–162

NSD (dBm/Hz)

–164

–166

–168

–170

0 200 400 600 800 1000100 300 500 700 900

+25°C

Figure 20. Single-Tone NSD vs. f

f

OUT

+85°C

(MHz)

over Temperature

OUT

100

90

+85°C

80

70

IMD (dBc)

60

+25°C

–40°C

50

40

30

0 100 200 300 400 500 600 700 800 900 1000

f

(MHz)

07851-019

Figure 22. IMD vs. f

OUT

over Temperature

OUT

07851-022

150

–152

–154

–156

–158

–160

–162

NSD (dBm/Hz)

–164

–40°C

–166

–168

–170

0 200 400 600 800 1000100 300 500 700 900

07851-020

+25°C

f

OUT

(MHz)

Figure 23. Eight-Tone NSD vs. f

+85°C

over Temperature

OUT

07851-023

50

10dB/DI V

CENTER 350. 27MHz
#RES BW 30kHz

RMS RESULTS

CARRIER POWER
–14.54dBm/

3.84MHz

FREQ
OFFSET
(MHz)
5
10
15
20
25

VBW 300kHz

REF

BW

(dBc)

(MHz)

–79.90

3.84
–80.60

3.84
–80.90

3.84
–80.62

3.84
–80.76

3.84

Figure 21. Single-Carrier WCDMA at 350 MHz, f

SPAN 53.84MHz

SWEEP 174.6ms (601pts)

(dBm)
–94.44
–95.14
–95.45
–95.16
–95.30

(dBc)
–79.03
–79.36
–80.73
–80.97
–80.95

UPPER

DAC

LOWER

(dBm)
–93.57
–94.40
–95.27
–95.51
–95.49

= 2457.6 MSPS

07851-021

Rev. B | Page 14 of 48

–55

–60

–65

–70

ACLR (dBc)

–75

FIRST ADJ CH

–80

–85

–90

0

245.76

122.88

FIFTH ADJ CH

491.52

368.64

f

OUT

614.40

(MHz)

737.28

Figure 24. Four-Carrier WCDMA at 350 MHz, f

SECOND ADJ CH

983.04

860.16

1105.90

= 2457.6 MSPS

DAC

1228.80

07851-024

Data Sheet AD9739

–

AC (MIX MODE)

f

= 2.4 GSPS, I

DAC

= 20 mA, nominal supplies, 25°C, unless otherwise noted.

OUTFS

10dB/DIV

START 20MHz
#RES BW 10kHz

VBW 10kHz

Figure 25. Single-Tone Spectrum at f

= 2.31 GHz, f

OUT

STOP 2.4GHz

SWEEP 28.7s (601pts)

= 2.4 GSPS

DAC

07851-025

80

75

70

65

60

55

50

45

40

SFDR (dBc)

35

30

25

20

15

10

1200 1300 1400 1500 1 600 1700 1800 1900 2000 2100 2200 2300 2400

f

(MHz)

OUT

Figure 26. SFDR in Mix Mode vs. f

10dB/DIV

CENTER 2.10706M Hz
#RES VW 30kHz

RMS RESULTS

CARRIER PO WER
–21.43dBm/

3.84MHz

FREQ
OFFSET
(MHz)
5
10
15
20
25

(MHz)

VBW 300kHz

REF

LOWER

BW

(dBc)

3.84

–68.99

3.84

–72.09

3.84

–72.86

3.84

–74.34

3.84

–74.77

at 2.4 GSPS

OUT

SPAN 53.84MHz

SWEEP 174.6ms (601pts)

UPPER

(dBm)

(dBc)
–63.94
–71.07
–71.34
–72.60
–73.26

(dBm)
–90.37
–92.50
–92.77
–94.03
–94.70

–90.43
–93.52
–94.30
–95.77
–96.20

07851-027

Figure 27. Typical Single-Carrier WCDMA ACLR Performance at 2.1 GHz,

= 2457.6 MSPS (Second Nyquist Zone)

f

DAC

Rev. B | Page 15 of 48

10dB/DIV

START 20MHz
#RES BW 10kHz

VBW 10kHz

Figure 28. Single-Tone Spectrum in Mix Mode at f

= 2.4 GSPS

f

DAC

90

85

80

75

70

65

60

55

IMD (dBc)

50

45

40

35

30

1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400

f

(MHz)

07851-026

OUT

Figure 29. IMD in Mix Mode vs. f

40

SECOND NYQUI ST ZO NE THIRD NYQUIST ZONE

–45

–50

–55

–60

–65

–70

ACLR (dBc)

–75

–80

–85

–90

1229 1475 1720 1966 2212 2458 2703 2949 3195 3441 3686

FIRST ADJ CH

FIFTH ADJ CH

f

OUT

(MHz)

Figure 30. Single-Carrier WCDMA ACLR vs. f

STOP 2.4GHzSTART 20MHz STOP 2.4GHz

SWEEP 28.7s (601pts)

= 1.31 GHz,

OUT

at 2.4 GSPS

OUT

SECOND ADJ CH

at 2457.6 MSPS

OUT

07851-028

07851-029

07851-030