Datasheet AD9739 Datasheet (ANALOG DEVICES)

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14-Bit, 2.5 GSPS,

Data Sheet

FEATURES

Direct RF synthesis at 2.5 GSPS update rate

DC to 1.25 GHz in baseband mode

1.25 GHz to 3.0 GHz in mix mode

Industry leading single/multicarrier IF or RF synthesis

= 350 MHz, ACLR =80 dBc

OUT

= 950 MHz, ACLR = 78 dBc

OUT

= 2100 MHz, ACLR = 69 dBc

OUT

Dual-port LVDS data interface

Up to 1.25 GSPS operation

Source synchronous DDR clocking Pin-compatible with the AD9739A Multichip synchronization capability Programmable output current: 8.7 mA to 31.7 mA Low power: 1.16 W at 2.5 GSPS

APPLICATIONS

Broadband communications systems Military jammers Instrumentation, automatic test equipment Radar, avionics

GENERAL DESCRIPTION

The AD9739 is a 14-bit, 2.5 GSPS high performance RF digitalto-analog converter (DAC) capable of synthesizing wideband signals from dc up to 3.0 GHz. Its DAC core features a quadswitch architecture that provides exceptionally low distortion performance with an industry-leading direct RF synthesis capability. This feature enables multicarrier generation up to the Nyquist frequency in baseband mode as well as second and third Nyquist zones in mix mode. The output current can be programmed over the 8.66 mA to 31.66 mA range.

The inclusion of on-chip controllers simplifies system integration. A dual-port, source synchronous, LVDS interface simplifies the digital interface with existing FGPA/ASIC technology. On-chip controllers are used to manage external and internal clock domain variations over temperature to ensure reliable data transfer from the host to the DAC core. Multichip synchronization is possible with an on-chip synchronization controller. A serial peripheral interface (SPI) is used for device configuration as well as readback of status registers.

The AD9739 is manufactured on a 0.18 µm CMOS process and operates from 1.8 V and 3.3 V supplies. It is supplied in a 160-ball chip scale ball grid array for reduced package parasitics.

RF Digital-to-Analog Converter

AD9739

FUNCTIONAL BLOCK DIAGRAM

RESET

SDIO

SDO

SCLK

DCI

DCO

SYNC_OUT

SYNC_IN

DB0[13:0]DB1[13:0]

SPI

LVDS DDR

DATA

CONTRO LLER

LVDS DDR

CLK DISTRIBUT ION

(DIV-BY-4)

SYNC-

CONTRO LLER

PRODUCT HIGHLIGHTS

1. Ability to synthesize high quality wideband signals with

bandwidths of up to 1.25 GHz in the first or second Nyquist zone.

2. A proprietary quad-switch DAC architecture provides

exceptional ac linearity performance while enabling mix mode operation.

3. A dual-port, double data rate, LVDS interface supports the

maximum conversion rate of 2500 MSPS.

4. On-chip controllers manage external and internal clock

domain skews.

5. A multichip synchronization capability.

6. Programmable differential current output with a 8.66 mA

to 31.66 mA range.

RECEIVER

Figure 1.

IRQ

AD9739

DAC BIAS

4-TO-1

DATA ASSEMBLER



1.2V

VREF

I120

TxDAC

CORE

DATA

LATCH

DLL

DACCLK

IOUTP

IOUTN

(MU CONTROL LER)

07851-001

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9739 Data Sheet

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 4

DC Specifications ......................................................................... 4

LVDS Digital Specifications........................................................ 5

Serial Port Specifications............................................................. 6

AC Specifications.......................................................................... 7

Absolute Maximum Ratings............................................................ 8

Thermal Resistance ...................................................................... 8

ESD Caution.................................................................................. 8

Pin Configurations and Function Descriptions ........................... 9

Typical Performance Characteristics ........................................... 12

AC (Normal Mode).................................................................... 12

AC (Mix Mode) ..........................................................................15

Terminology .................................................................................... 17

Serial Port Interface (SPI) Register............................................... 18

SPI Register Map Description................................................... 18

SPI Operation.............................................................................. 18

SPI Register Map............................................................................. 20

SPI Port Configuration and Software Reset............................ 22

Power-Down LVDS Interface and TxDAC®............................ 22

Controller Clock Disable........................................................... 22

Interrupt Request (IRQ) Enable/Status ................................... 22

TxDAC Full-Scale Current Setting (I

TxDAC Quad-Switch Mode of Operation.............................. 23

) and Sleep ........... 23

OUTFS

DCI Phase Alignment Status .................................................... 23

SYNC_IN Phase Alignment Status.......................................... 23

Data Receiver Controller Configuration................................. 23

Data Receiver Controller_Data Sample Delay Value ............ 24

Data and Sync Receiver Controller_DCI Delay

Value/Window and Phase Rotation......................................... 24

Data Receiver Controller_Delay Line Status and Sync

Controller SYNC_OUT Status ................................................. 24

Sync and Data Receiver Controller Lock/Tracking Status.... 25

CLK Input Common Mode ...................................................... 25

Mu Controller Configuration and Status................................ 25

Part ID ......................................................................................... 26

Theory of Operation ...................................................................... 27

LVDS Data Port Interface.......................................................... 28

Mu Controller............................................................................. 32

Interrupt Requests...................................................................... 34

Multiple Device Synchronization............................................. 35

Analog Interface Considerations.................................................. 38

Analog Modes of Operation ..................................................... 38

Clock Input Considerations...................................................... 39

Voltage Reference ....................................................................... 40

Analog Outputs .......................................................................... 40

Nonideal Spectral Artifacts....................................................... 43

Lab Evaluation of the AD9739 ................................................. 44

Power Dissipation and Supply Domains................................. 44

Recommended Start-Up Sequence.......................................... 45

Outline Dimensions....................................................................... 48

Ordering Guide .......................................................................... 48



REVISION HISTORY

1/12—Rev. A to Rev. B

Changes to Features Section, Applications Section, General

Description Section, Figure 1, Product Highlights Section ........ 1

Changes to DC Specifications Section........................................... 4

Changed Digital Specifications Section to LVDS Digital

Specifications Section....................................................................... 5

Changes to LVDS Digital Specifications Section ......................... 5

Added Serial Port Specifications Section and Table 3;

Renumbered Sequentially................................................................ 6

Changes to AC Specifications Section........................................... 7

Changes to Table 5............................................................................ 8

Changes to Table 7.......................................................................... 10

Rev. B | Page 2 of 48

Deleted Static Linearity Section and Figure 7 to Figure 17;

Renumbered Sequentially ............................................................. 11

Changed Dynamic Performance Normal Mode, 20 mA Full Scale (Unless Otherwise Noted) Section to AC (Normal Mode)

Section.............................................................................................. 12

Changes to AC (Normal Mode) Section ..................................... 12

Changed Dynamic Performance Mix Mode, 20 mA Full Scale

Section to AC (Mix Mode) Section.............................................. 15

Changes to AC (Mix Mode) Section............................................ 15

Added Serial Port Interface (SPI) Register Section, SPI Register Map Description Section, Reset Section, Table 8, and SPI

Operation Section and Figure 34 ................................................. 18

Data Sheet AD9739

Deleted DOCSIS Performance Section and

Figure 46 to Figure 72.....................................................................19

Added Figure 35 through Figure 38; Renumbered Sequentially.... 19

Changes to SPI Register Map Section and Table 9......................20

Added SPI Port Configuration and Software Reset Section, Power-Down LVDS Interface and TxDAC® Section, Controller Clock Disable Section, Interrupt Request (IRQ) Enable/Status

Section, and Table 10 to Table 13 ..................................................22

Added TxDAC Full-Scale Current Setting (I

) and Sleep

OUTFS

Section, TxDAC Quad-Switch Mode of Operation Section, DCI Phase Alignment Status Section, SYNC_IN Phase Alignment Status Section, Data Receiver Controller Configuration Section,

and Table 14 to Table 18 .................................................................23

Added Data Receiver Controller_Data Sample Delay Value Section, Data and Sync Receiver Controller_DCI Delay Value/Window and Phase Rotation Section, Data Receiver Controller_Delay Line Status and Sync Controller SYNC_OUT

Status Section, and Table 19 to Table 21.......................................24

Deleted Serial Peripheral Interface Section, General Operation of the Serial Interface Section, Instruction Mode (8-Bit Instruction)

Section, and Serial Interface Port Pin Description Section .......25

Added Sync and Data Receiver Controller Lock/Tracking Status Section, CLK Input Common Mode Section, Mu Controller

Configuration and Status Section, and Table 22 to Table 24.....25

Deleted MSB/LSB Transfers Section, Serial Port Configuration

Section, and Figure 74 to Figure 79 ..............................................26

Added Part ID Section and Table 25 ............................................26

Changes to Theory of Operation Section ....................................27

Added Figure 39 ..............................................................................27

Deleted SPI Registers Section and Table 8 to Table 31...............28

Moved and Changes to LVDS Data Port Interface Section .......28

Added Figure 40 and Figure 41 .....................................................28

Changes to Figure 42 ......................................................................29

Moved and Changes to Figure 43..................................................29

Added Data Receiver Controller Initialization Description Section, Table 26, and Data Receiver Operation at Lower Clock

Rates Section ....................................................................................30

Added LVDS Driver and Receiver Input Section, Figure 44 to

Figure 47, and Table 27...................................................................31

Changed and Moved Mu Delay Controller Section to Mu

Controller Section...........................................................................32

Changes to Mu Controller Section, Figure 48, and Figure 49...32

Added Figure 50 and Table 28 .......................................................32

Added Mu Controller Initialization Description Section..........33

Changes to Interrupt Requests Section........................................34

Added Table 29 ................................................................................34

Changed Synchronization Controller Section to Multiple

Device Synchronization Section....................................................35

Added Figure 52 ..............................................................................35

Changes to Figure 53 ......................................................................36

Added Sync Controller Initialization Description Section........36

Added Synchronization Limitations Section...............................37

Changed Applications Information to Analog Interface

Considerations Section...................................................................38

Changes to Analog Modes of Operation Section .......................38

Deleted Clocking the AD9739 Section, Figure 85, and Figure 86..39 Added Clock Input Considerations Section, Figure 58 to

Figure 60...........................................................................................39

Deleted Clock Phase Noise Affects on AC Performance Section, Table 32 to Table 34, Applying Data to the AD9739 Section, and

Figure 87...........................................................................................40

Moved Figure 61..............................................................................40

Changes to Voltage References Section and Analog Outputs

Section ..............................................................................................40

Added Equivalent DAC Output and Transfer Function and

Figure 63...........................................................................................40

Deleted Mu Control Operation Section, Search Mode Section,

and Figure 89 ................................................................................... 41

Moved Figure 64..............................................................................41

Added Peak DAC Output Power Capability Section and Figure 65. 41 Deleted Figure 90, Figure 91, Track Mode Section, Mu Delay and Phase Readback Section, Operating the Mu Controller Manually Section, and Calculating Mu Delay Line Step Size

Section ..............................................................................................42

Added Output Stage Configuration Section and Figure 66 to

Figure 70...........................................................................................42

Added Nonideal Spectral Artifacts Section, Figure 71, and

Table 30.............................................................................................43

Deleted Operation in Master Mode, Figure 93, and

Figure 94...........................................................................................44

Added Lab Evaluation of the AD9739 Section, Power Dissipation

and Supply Domains Section, and Figure 72 to Figure 74......... 44

Deleted Figure 95, Operation in Slave Mode Section, and Data

Receiver Operation in Auto Mode Section.................................. 45

Changes to Recommended Start-Up Sequence Section ............45

Added Figure 75..............................................................................45

Deleted Figure 97, Data Receiver Operation in Manual Mode Section, Calculating the DCI Delay Line Step Size Section, and

Maximum Allowable Data Timing Skew/Jitter Section.............46

Added Table 31 ................................................................................ 46

Deleted Optimizing the Clock Common-Mode Voltage Section, Figure 99, Analog Control Registers Section, Mirror Roll-Off

Frequency Control Section, and Figure 101................................47

Added Table 32 ................................................................................ 47

Deleted Figure 103, Figure 104, and Figure 106 .........................48

Updated Outline Dimensions........................................................48

Deleted Figure 107 to Figure 109..................................................49

Deleted Table 35 to Table 44.......................................................... 50

7/11—Rev 0 to Rev A

Changes to Table 2, DAC CLOCK INPUT (DACCLK_P,

DACCLK_N), Added DAC Clock Rate .........................................4

Changes to Table 3, Added Dynamic Performance Parameters....... 5

Change to Ordering Guide ............................................................ 53

2/09—Revision 0: Initial Release

Rev. B | Page 3 of 48

AD9739 Data Sheet

SPECIFICATIONS

DC SPECIFICATIONS

VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, I

Table 1.

Parameter Min Typ Max Unit

RESOLUTION 14 Bits ACCURACY

Integral Nonlinearity (INL) ±1.3 LSB Differential Nonlinearity (DNL) ±0.8 LSB

ANALOG OUTPUTS

Gain Error (with Internal Reference) 5.5 % Full-Scale Output Current 8.66 20.2 31.66 mA Output Compliance Range −1.0 +1.0 V Common-Mode Output Resistance 10 MΩ Differential Output Resistance 70 Ω Output Capacitance 1 pF

DAC CLOCK INPUT (DACCLK_P, DACCLK_N)

Differential Peak-to-Peak Voltage 1.2 1.6 2.0 V Common-Mode Voltage 900 mV DAC Clock Rate 0.8 2.5 GHz

TEMPERATURE DRIFT

Gain 60 ppm/°C Reference Voltage 20 ppm/°C

REFERENCE

Internal Reference Voltage 1.15 1.2 1.25 V Output Resistance 5 kΩ

ANALOG SUPPLY VOLTAGES

VDDA 3.1 3.3 3.5 V VDDC 1.70 1.8 1.90 V

DIGITAL SUPPLY VOLTAGES

VDD33 3.10 3.3 3.5 V VDD 1.70 1.8 1.90 V

SUPPLY CURRENTS AND POWER DISSIPATION, 2.0 GSPS

37 38 mA

VDDA

159 166 mA

VDDC

34 37 mA

VDD33

233 238 mA

VDD

Power Dissipation 0.940 0.975 W Sleep Mode, I

2.5 2.75 mA

VDDA

Power-Down Mode (Register 0x01 = 0x33 and Register 0x02 = 0x80)

0.02 mA

VDDA

3.8 mA

VDDC

0.5 mA

VDD33

0.1 mA

VDD

SUPPLY CURRENTS AND POWER DISSIPATION, 2.5 GSPS

37 mA

VDDA

223 mA

VDDC

34 mA

VDD33

290 mA

VDD

Power Dissipation 1.16 W

OUTFS

= 20 mA.

Rev. B | Page 4 of 48

Data Sheet AD9739

LVDS DIGITAL SPECIFICATIONS

VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, I 1996 reduced range link, unless otherwise noted.

Table 2.

Parameter Min Typ Max Unit

LVDS DATA INPUTS (DB0[13:0], DB1[13:0])1

Input Common-Mode Voltage Range, V

Logic High Differential Input Threshold, V

Logic Low Differential Input Threshold, V

825 1575 mV

COM

175 400 mV

IH_DTH

−175 −400 mV

IL_DTH

Receiver Differential Input Impedance, RIN 80 120 Ω

Input Capacitance 1.2 pF

LVDS Input Rate 1250 MSPS

LVDS Minimum Data Valid Period, t

(See Figure 41) 344 ps

VALI D

LVDS CLOCK INPUT (DCI and SYNC_IN)2

Input Common-Mode Voltage Range, V

Logic High Differential Input Threshold, V

Logic Low Differential Input Threshold, V

825 1575 mV

COM

175 400 mV

IH_DTH

−175 −400 mV

IL_DTH

Receiver Differential Input Impedance, RIN 80 120 Ω

Input Capacitance 1.2 pF

Maximum Clock Rate 625 MHz

LVDS CLOCK OUTPUT (DCO and SYNC_OUT)3

Output Voltage High (x_P or x_N) 1375 mV

Output Voltage Low (x_P or x_N) 1025 mV

Output Differential Voltage, |VOD| 150 200 250 mV

Output Offset Voltage, VOS 1150 1250 mV

Output Impedance, Single-Ended, RO 80 100 120 Ω

RO Single-Ended Mismatch 10 %

Maximum Clock Rate 625 MHz

DB0[x]P, DB0[x]N, DB1[x]P, and DB1[x]N pins.

DCI_P and DCI_N pins, as well as SYNC_IN_P and SYNC_IN_N pins.

DCO_P and DCO_N pins, as well as SYNC_OUT_P/SYNC_OUT_N pins with 100 Ω differential termination.

= 20 mA. LVDS drivers and receivers are compliant to the IEEE Standard 1596.3-

OUTFS

Rev. B | Page 5 of 48

AD9739 Data Sheet

SERIAL PORT SPECIFICATIONS

VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V.

Tabl e 3

Parameter Min Typ Max Unit

WRITE OPERATION (See Figure 36)

SCLK Clock Rate, f SCLK Clock High, tHI 18 ns SCLK Clock Low, t SDIO to SCLK Setup Time, tDS 2 ns SCLK to SDIO Hold Time, tDH 1 ns CS to SCLK Setup Time, tS

SCLK to CS Hold Time, tH

READ OPERATION (See Figure 37 and Figure 38)

SCLK Clock Rate, f SCLK Clock High, tHI 18 ns SCLK Clock Low, t SDIO to SCLK Setup Time, tDS 2 ns SCLK to SDIO Hold Time, tDH 1 ns CS to SCLK Setup Time, tS SCLK to SDIO (or SDO) Data Valid Time, tDV 15 ns CS to SDIO (or SDO) Output Valid to High-Z, tEZ

INPUTS (SDIO, SCLK, CS)

Voltage in High, VIH 2.0 3.3 V Voltage in Low, VIL 0 0.8 V Current in High, IIH −10 +10 μA Current in Low, IIL −10 +10 μA

OUTPUT (SDIO)

Voltage Out High, VOH 2.4 3.5 V Voltage Out Low, VOL 0 0.4 V Current Out High, IOH 4 mA Current Out Low, IOL 4 mA

(or /t

SCLK

18 ns

LOW

) 20 MHz

SCLK

3 ns 2 ns

(or /t

SCLK

18 ns

LOW

) 20 MHz

SCLK

3 ns

2 ns

Rev. B | Page 6 of 48

Data Sheet AD9739

AC SPECIFICATIONS

VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, I

Table 4.

Parameter Min Typ Max Unit

DYNAMIC PERFORMANCE

DAC Clock Rate 800 2500 MSPS

Adjusted DAC Update Rate1 800 2500 MSPS

Output Settling Time (tst) to 0.1% 13 ns

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

= 100 MHz 69.5 dBc

OUT

= 350 MHz 58.5 dBc

OUT

= 550 MHz 54 dBc

OUT

= 950 MHz 60 dBc

OUT

TWO-TONE INTERMODULATION DISTORTION (IMD), f

= 100 MHz 94 dBc

OUT

= 350 MHz 78 dBc

OUT

= 550 MHz 72 dBc

OUT

= 950 MHz 68 dBc

OUT

NOISE SPECTRAL DENSITY (NSD), 0 dBFS SINGLE TONE

= 100 MHz −166 dBm/Hz

OUT

= 350 MHz −161 dBm/Hz

OUT

= 550 MHz −160 dBm/Hz

OUT

= 850 MHz −160 dBm/Hz

OUT

WCDMA ACLR (SINGLE CARRIER), ADJACENT/ALTERNATE ADJACENT CHANNEL

= 2457.6 MSPS f

DAC

= 2457.6 MSPS, f

DAC

= 2457.6 MSPS, f

DAC

= 2457.6 MSPS, f

DAC

Adjusted DAC updated rate is calculated as f

with f

= 2500 MSPS, f

DAC

= 350 MHz 80/80 dBc

OUT

= 950 MHz 78/79 dBc

OUT

= 1700 MHz (Mix Mode) 74/74 dBc

OUT

= 2100 MHz (Mix Mode) 69/72 dBc

OUT

divided by the minimum required interpolation factor. For the AD9739, the minimum interpolation factor is 1. Thus,

adjusted = 2500 MSPS.

DAC

= 20 mA, f

OUTFS

= f

OUT2

= 2400 MSPS.

DAC

+ 1.25 MHz

OUT1

Rev. B | Page 7 of 48

AD9739 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 5.

With

Parameter

VDDA VSSA −0.3 V to +3.6 V VDD33 VSS −0.3 V to +3.6 V VDD VSS −0.3 V to +1.98 V VDDC VSSC −0.3 V to +1.98 V VSSA VSS −0.3 V to +0.3 V VSSA VSSC −0.3 V to +0.3 V VSS VSSC −0.3 V to +0.3 V DACCLK_P, DACCLK_N VSSC −0.3 V to VDDC + 0.18 V DCI, DCO, SYNC_IN,

SYNC_OUT LVDS Data Inputs VSS −0.3 V to VDD33 + 0.3 V IOUTP, IOUTN VSSA −1.0 V to VDDA + 0.3 V I120, VREF VSSA −0.3 V to VDDA + 0.3 V IRQ, CS, SCLK, SDO,

SDIO, RESET Junction Temperature 150°C Storage Temperature −65°C to +150°C

Respect To

VSS −0.3 V to VDD33 + 0.3 V

Rating

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 6. Thermal Resistance

Package Type θJA θ

160-Ball CSP_BGA 31.2 7.0 °C/W1

With no airflow movement.

Unit

ESD CAUTION

Rev. B | Page 8 of 48

Data Sheet AD9739

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1413121110876321954

VDDA, 3.3V, ANALOG SUPPLY

VSSA, ANALOG SUPPLY GROUND

VSSA SHIELD, ANALOG SUPPLY GROUND SHIE LD

Figure 2. Analog Supply Pins (Top View)

VDD, 1.8V, DIGITAL SUPPLY

VSS DIGITAL SUPPLY GROUND

VDD33, 3.3V DIGITAL SUPPLY

Figure 3. Digital Supply Pins (Top View)

VDDC, 1.8V, CLOCK SUPPLY

VSSC, CLOCK SUPPLY GROUND

07851-002

07851-004

Figure 4. Digital LVDS Clock Supply Pins (Top View)

1413121110876321954

DACCLK_N

DACCLK_ P

SYNC_OUT_P/_N

SYNC_IN_P/_N

DB1[0:13]P

DB1[0:13]N

DB0[0:13]P

DB0[0:13]N

07851-003

DIFFERENTIAL INPUT SIGNAL (CLOCK OR DATA)

Figure 5. Digital LVDS Input, Clock I/O (Top View)

1413121110876321954

DCO_P/_N

DCI_P/_N

07851-005

Rev. B | Page 9 of 48

AD9739 Data Sheet

IOUTN

IOUTP

1413121110876321954

Figure 6. Analog I/O and SPI Control Pins (Top View)

I120

VREF

IPTAT

IRQ

SCLK

RESET

SDIO

SDO

07851-006

Table 7. AD9739 Pin Function Descriptions

Pin No. Mnemonic Description

C1, C2, D1, D2, E1, E2, E3, E4 VDDC 1.8 V Clock Supply Input. A1, A2, A3, A4, A5, B1, B2, B3, B4, B5, C4,

VSSC

Clock Supply Return.

C5, D4, D5 A10, A11, B10, B11, C10, C11, D10, D11 VDDA A12, A13, B12, B13, C12, C13, D12, D13, VSSA A6, A9, B6, B9, C6, C9, D6, D9, F1, F2, F3,

VSSA Shield

3.3 V Analog Supply Input. Analog Supply Return. Analog Supply Return Shield. Tie to VSSA at the DAC.

F4, E11, E12, E13, E14, F11, F12 A14 NC A7, B7, C7, D7 IOUTN A8, B8, C8, D8 IOUTP B14 I120

No Connect. Do not connect to this pin. DAC Negative Current Output Source. DAC Positive Current Output Source. Nominal 1.2 V Reference. Tie to analog ground via a 10 kΩ

resistor to generate a 120 μA reference current.

C14 VREF

Voltage Reference Input/Output. Decouple to VSSA with a

1 nF capacitor. D14 NC C3, D3 DACCLK_N/DACCLK_P F13 IRQ

Factory Test Pin. Do not connect to this pin.

Negative/Positive DAC Clock Input (DACCLK).

Interrupt Request Open Drain Output. Active high. Pull up to

VDD33 with a 10 kΩ resistor. F14 RESET G13

CS G14 SDIO H13 SCLK H14 SDO J3, J4, J11, J12 VDD33 G1, G2, G3, G4, G11, G12 VDD H1, H2, H3, H4, H11, H12, K3, K4, K11, K12 VSS J1, J2 SYNC_OUT_P/SYNC_OUT_N K1, K2 SYNC_IN_P/SYNC_IN_N J13, J14 DCO_P/DCO_N K13, K14 DCI_P/DCI_N L1, M1 DB1[0]P/DB1[0]N L2, M2 DB1[1]P/DB1[1]N L3, M3 DB1[2]P/DB1[2]N L4, M4 DB1[3]P/DB1[3]N L5, M5 DB1[4]P/DB1[4]N

Reset Input. Active high. Tie to VSS if unused. Serial Port Enable Input. Serial Port Data Input/Output. Serial Port Clock Input. Serial Port Data Output.

3.3 V Digital Supply Input.

1.8 V Digital Supply. Input. Digital Supply Return. Positive/Negative SYNC Output (SYNC_OUT) Positive/Negative SYNC Input (SYNC_IN) Positive/Negative Data Clock Output (DCO). Positive/Negative Data Clock Input (DCI). Port 1 Positive/Negative Data Input Bit 0. Port 1 Positive/Negative Data Input Bit 1. Port 1 Positive/Negative Data Input Bit 2. Port 1 Positive/Negative Data Input Bit 3. Port 1 Positive/Negative Data Input Bit 4.

L6, M6 DB1[5]P/DB1[5]N Port 1 Positive/Negative Data Input Bit 5.

Rev. B | Page 10 of 48

Data Sheet AD9739

Pin No. Mnemonic Description

L7, M7 DB1[6]P/DB1[6]N Port 1 Positive/Negative Data Input Bit 6. L8, M8 DB1[7]P/DB1[7]N Port 1 Positive/Negative Data Input Bit 7. L9, M9 DB1[8]P/DB1[8]N Port 1 Positive/Negative Data Input Bit 8. L10, M10 DB1[9]P/DB1[9]N Port 1 Positive/Negative Data Input Bit 9. L11, M11 DB1[10]P/DB1[10]N Port 1 Positive/Negative Data Input Bit 10. L12, M12 DB1[11]P/DB1[11]N Port 1 Positive/Negative Data Input Bit 11. L13, M13 DB1[12]P/DB1[12]N Port 1 Positive/Negative Data Input Bit 12. L14, M14 DB1[13]P/DB1[13]N Port 1 Positive/Negative Data Input Bit 13. N1, P1 DB0[0]P/DB0[0]N Port 0 Positive/Negative Data Input Bit 0. N2, P2 DB0[1]P/DB0[1]N Port 0 Positive/Negative Data Input Bit 1. N3, P3 DB0[2]P/DB0[2]N Port 0 Positive/Negative Data Input Bit 2. N4, P4 DB0[3]P/DB0[3]N Port 0 Positive/Negative Data Input Bit 3. N5, P5 DB0[4]P/DB0[4]N Port 0 Positive/Negative Data Input Bit 4. N6, P6 DB0[5]P/DB0[5]N Port 0 Positive/Negative Data Input Bit 5. N7, P7 DB0[6]P/DB0[6]N Port 0 Positive/Negative Data Input Bit 6. N8, P8 DB0[7]P/DB0[7]N Port 0 Positive/Negative Data Input Bit 7. N9, P9 DB0[8]P/DB0[8]N Port 0 Positive/Negative Data Input Bit 8. N10, P10 DB0[9]P/DB0[9]N Port 0 Positive/Negative Data Input Bit 9. N11, P11 DB0[10]P/DB0[10]N Port 0 Positive/Negative Data Input Bit 10. N12, P12 DB0[11]P/DB0[11]N Port 0 Positive/Negative Data Input Bit 11. N13, P13 DB0[12]P/DB0[12]N Port 0 Positive/Negative Data Input Bit 12. N14, P14 DB0[13]P/DB0[13]N Port 0 Positive/Negative Data Input Bit 13.

Rev. B | Page 11 of 48

AD9739 Data Sheet

–

TYPICAL PERFORMANCE CHARACTERISTICS

AC (NORMAL MODE)

= 20 mA, nominal supplies, 25°C, unless otherwise noted.

OUTFS

10dB/DIV

Figure 7. Single-Tone Spectrum at f

1.2GSPS

2.4GSPS

SFDR (dBc)

0 100 200 300 400 500 60 0 700 800 900 1000 1100 1200

2.0GSPS

Figure 8. SFDR vs. f

150

–152

–154

–156

–158

–160

–162

NSD (dBm/Hz)

–164

–166

–168

–170

0 100 200 300 400 500 600 700 800 900 1000 1100 1200

Figure 9. Single-Tone NSD over f

VBW 10kHz

1.6GSPS

OUT

(MHz)

OUT

1.2GSPS

(MHz)

= 91 MHz, f

over f

DAC

2.4GSPS

OUT

STOP 2.4GHzSTART 20MHz

= 2.4 GSPS

DAC

10dB/DIV

STOP 2.4GHzSTART 20MHz

2.4GSPS

VBW 10kHz

1.2GSPS

OUT

1.2GSPS

OUT

= 1091 MHz, f

OUT

2.4GSPS

(MHz)

over f

OUT

(MHz)

2.0GSPS

DAC

OUT

DAC

= 2.4 GSPS

1100 1200

07851-010

07851-011

07851-012

07851-007

Figure 10. Single-Tone Spectrum at f

100

1.6GSPS

IMD (dBc)

0 100 200 300 400 500 600 700 800 900 1000

07851-008

Figure 11. IMD vs. f

160

–161

–162

–163

–164

–165

–166

NSD (dBm/Hz)

–167

–168

–169

–170

0 100 200 300 400 500 600 700 800 900 1000 1100 1200

07851-009

Figure 12. Eight-Tone NSD over f

Rev. B | Page 12 of 48

Data Sheet AD9739

= 2 GSPS, I

DAC

= 20 mA, nominal supplies, 25°C, unless otherwise noted.

OUTFS

110

SFDR (dBc)

0 100 200 300 400 500 600 700 800 900 1000

Figure 13. SFDR vs. f

SFDR (dB)

0dBFS

–6dBFS

(MHz)

OUT

over Digital Full Scale

OUT

–6dBFS

0dBFS

–3dBFS

100

IMD (dBc)

0 100 200 300 400 500 600 700 800 900 1000

(MHz)

07851-013

Figure 16. IMD vs. f

SFDR (dB)

0dBFS

OUT

over Digital Full Scale

OUT

–6dBFS

–3dBFS

–6dBFS

–3dBFS

0dBFS

07851-016

0 100 200 300 400 500 600 700 800 900 1000

(MHz)

OUT

Figure 14. SFDR for Second Harmonic over f

SFDR (dBc)

0 100 200 300 400 500 600 700 800 900 1000

10mA FS

20mA FS

OUT

Figure 15. SFDR vs. f

(MHz)

OUT

vs. Digital Full Scale

OUT

30mA FS

over DAC I

OUTFS

0 100 200 300 400 500 600 700 800 900 1000

(MHz)

10mA FS

OUT

(MHz)

over DAC I

OUT

vs. Digital Full Scale

OUT

30mA FS

OUTFS

07851-014

Figure 17. SFDR for Third Harmonic over f

110

100

IMD (dBc)

0 100 200 300 400 500 600 700 800 900 1000

07851-015

20mA FS

Figure 18. IMD vs. f

7851-017

07851-018

Rev. B | Page 13 of 48

AD9739 Data Sheet

–

110

–40°C

+85°C

SFDR (dBc)

+25°C

0 100 200 300 400 500 600 700 800 900 1000

(MHz)

OUT

Figure 19. SFDR vs. f

over Temperature

OUT

150

–152

–154

–156

–158

–40°C

–160

–162

NSD (dBm/Hz)

–164

–166

–168

–170

0 200 400 600 800 1000100 300 500 700 900

+25°C

Figure 20. Single-Tone NSD vs. f

OUT

+85°C

(MHz)

over Temperature

OUT

100

+85°C

IMD (dBc)

+25°C

–40°C

0 100 200 300 400 500 600 700 800 900 1000

(MHz)

07851-019

Figure 22. IMD vs. f

OUT

over Temperature

OUT

07851-022

150

–152

–154

–156

–158

–160

–162

NSD (dBm/Hz)

–164

–40°C

–166

–168

–170

0 200 400 600 800 1000100 300 500 700 900

07851-020

+25°C

OUT

(MHz)

Figure 23. Eight-Tone NSD vs. f

+85°C

over Temperature

OUT

07851-023

10dB/DI V

CENTER 350. 27MHz #RES BW 30kHz

RMS RESULTS

CARRIER POWER –14.54dBm/

3.84MHz

FREQ OFFSET (MHz) 5 10 15 20 25

VBW 300kHz

REF

(dBc)

(MHz)

–79.90

3.84 –80.60

3.84 –80.90

3.84 –80.62

3.84 –80.76

3.84

Figure 21. Single-Carrier WCDMA at 350 MHz, f

SPAN 53.84MHz

SWEEP 174.6ms (601pts)

(dBm) –94.44 –95.14 –95.45 –95.16 –95.30

(dBc) –79.03 –79.36 –80.73 –80.97 –80.95

UPPER

DAC

LOWER

(dBm) –93.57 –94.40 –95.27 –95.51 –95.49

= 2457.6 MSPS

07851-021

Rev. B | Page 14 of 48

–55

–60

–65

–70

ACLR (dBc)

–75

FIRST ADJ CH

–80

–85

–90

245.76

122.88

FIFTH ADJ CH

491.52

368.64

OUT

614.40

(MHz)

737.28

Figure 24. Four-Carrier WCDMA at 350 MHz, f

SECOND ADJ CH

983.04

860.16

1105.90

= 2457.6 MSPS

DAC

1228.80

07851-024

Data Sheet AD9739

–

AC (MIX MODE)

= 2.4 GSPS, I

DAC

= 20 mA, nominal supplies, 25°C, unless otherwise noted.

OUTFS

10dB/DIV

START 20MHz #RES BW 10kHz

VBW 10kHz

Figure 25. Single-Tone Spectrum at f

= 2.31 GHz, f

OUT

STOP 2.4GHz

SWEEP 28.7s (601pts)

= 2.4 GSPS

DAC

07851-025

SFDR (dBc)

1200 1300 1400 1500 1 600 1700 1800 1900 2000 2100 2200 2300 2400

(MHz)

OUT

Figure 26. SFDR in Mix Mode vs. f

10dB/DIV

CENTER 2.10706M Hz #RES VW 30kHz

RMS RESULTS

CARRIER PO WER –21.43dBm/

3.84MHz

FREQ OFFSET (MHz) 5 10 15 20 25

(MHz)

VBW 300kHz

REF

LOWER

(dBc)

3.84

–68.99

3.84

–72.09

3.84

–72.86

3.84

–74.34

3.84

–74.77

at 2.4 GSPS

OUT

SPAN 53.84MHz

SWEEP 174.6ms (601pts)

UPPER

(dBm)

(dBc) –63.94 –71.07 –71.34 –72.60 –73.26

(dBm) –90.37 –92.50 –92.77 –94.03 –94.70

–90.43 –93.52 –94.30 –95.77 –96.20

07851-027

Figure 27. Typical Single-Carrier WCDMA ACLR Performance at 2.1 GHz,

= 2457.6 MSPS (Second Nyquist Zone)

DAC

Rev. B | Page 15 of 48

10dB/DIV

START 20MHz #RES BW 10kHz

VBW 10kHz

Figure 28. Single-Tone Spectrum in Mix Mode at f

= 2.4 GSPS

DAC

IMD (dBc)

1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400

(MHz)

07851-026

OUT

Figure 29. IMD in Mix Mode vs. f

SECOND NYQUI ST ZO NE THIRD NYQUIST ZONE

–45

–50

–55

–60

–65

–70

ACLR (dBc)

–75

–80

–85

–90

1229 1475 1720 1966 2212 2458 2703 2949 3195 3441 3686

FIRST ADJ CH

FIFTH ADJ CH

OUT

(MHz)

Figure 30. Single-Carrier WCDMA ACLR vs. f

STOP 2.4GHzSTART 20MHz STOP 2.4GHz

SWEEP 28.7s (601pts)

= 1.31 GHz,

OUT

at 2.4 GSPS

OUT

SECOND ADJ CH

at 2457.6 MSPS

OUT

07851-028

07851-029

07851-030

AD9739 Data Sheet

10dB/DIV

CENTER 2.807G Hz #RES BW 30kHz

RMS RESULTS

CARRIER PO WER –24.4dBm/

3.84MHz

FREQ OFFSET (MHz) 5 10 15 20 25

VBW 300kHz

REF BW

(dBc)

(MHz)

–64.90

3.84 –66.27

3.84 –68.44

3.84 –70.20

3.84 –70.85

3.84

LOWER

–89.30 –90.67 –92.84 –94.60 –95.25

(dBm)

SPAN 53.84MHz

SWEEP 174.6ms (601pts)

UPPER

(dBm)

(dBc)

–88.22

–63.82

–90.10

–65.70

–90.95

–66.55

–93.35

–68.95

–94.85

–70.45

07851-031

Figure 31. Typical Single-Carrier WCDMA ACLR Performance at 2.8 GHz,

= 2457.6 MSPS (Third Nyquist Zone)

DAC

10dB/DIV

CENTER 2.81271GHz #RES BW 30kHz

RMS RESULTS

CARRIER PO WER –27.98dBm/

3.84MHz

FREQ OFFSET (MHz) 5 10 15 20 25 30

VBW 300kHz

REF

LOWER

(MHz)

(dBc)

3.84

–0.42

3.84

–64.32

3.84

–66.03

3.84

–66.27

3.84

–66.82

3.84

–67.16

(dBm) –28.40 –92.30 –94.01 –94.24 –94.79 –95.13

SPAN 63.84MHz

SWEEP 207ms (601p ts)

UPPER

(dBc)

(dBm)

–0.10

–28.07

–0.08

–28.06

–65.37

–93.34

–66.06

–94.03

–63.36

–93.34

–66.54

–94.51

Figure 33. Typical Four-Carrier WCDMA ACLR Performance at 2.8 GHz,

= 2457.6 MSPS (Third Nyquist Zone)

DAC

07851-033

CENTER 2.09758G Hz #RES BW 30kHz

RMS RESULTS

CARRIER POWER –25.53dBm/

3.84MHz

FREQ OFFSET (MHz) 5 10 15 20 25 30

VBW 300kHz

REF

LOWER

(MHz)

(dBc)

3.84

0.22

3.84

–66.68

3.84

–68.01

3.84

–68.61

3.84

–68.87

3.84

–69.21

(dBm) –25.31 –92.21 –93.53 –94.14 –94.40 –94.74

SPAN 63.84MHz

SWEEP 207ms ( 601pts)

UPPER

(dBc)

(dBm)

0.24

–25.29

0.14

–25.38

–66.82

–92.35

–67.83

–93.36

–67.64

–93.17

–68.50

–94.03

Figure 32. Typical Four-Carrier WCDMA ACLR Performance at 2.1 GHz,

= 2457.6 MSPS (Second Nyquist Zone)

DAC

07851-032

Rev. B | Page 16 of 48

Data Sheet AD9739

TERMINOLOGY

Linearity Error (Integral Nonlinearity or INL)

The maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from 0 to full scale.

Differential Nonlinearity (DNL)

The measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code.

Monotonicity

A DAC is monotonic if the output either increases or remains constant as the digital input increases.

Offset Error

The deviation of the output current from the ideal of 0 is called the offset error. For IOUTP, 0 mA output is expected when the inputs are all 0s. For IOUTN, 0 mA output is expected when all inputs are set to 1.

Gain Error

The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1 minus the output when all inputs are set to 0.

Output Compliance Range

The range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance.

Temp er at u re D ri ft

Specified as the maximum change from the ambient (25°C) value to the value at either T drift, the drift is reported in ppm of full-scale range (FSR) per °C. For reference drift, the drift is reported in ppm per °C.

MIN

or T

. For offset and gain

MAX

Power Supply Rejection (PSR)

The maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages.

Spurious-Free Dynamic Range (SFDR)

The difference, in decibels (dB), between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth.

Total Harmonic Distortion (THD)

The ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. It is expressed as a percentage or in decibels (dB).

Noise Spectral Density (NSD)

NSD is the converter noise power per unit of bandwidth. This is usually specified in dBm/Hz in the presence of a 0 dBm full-scale signal.

Adjacent Channel Leakage Ratio (ACLR)

The adjacent channel leakage (power) ratio is a ratio, in dBc, of the measured power within a channel relative to its adjacent channels.

Modulation Error Ratio (MER)

Modulated signals create a discrete set of output values referred to as a constellation. Each symbol creates an output signal corresponding to one point on the constellation. MER is a measure of the discrepancy between the average output symbol magnitude and the rms error magnitude of the individual symbol.

Intermodulation Distortion (IMD)

IMD is the result of two or more signals at different frequencies mixing together. Many products are created according to the formula, aF1 ± bF2, where a and b are integer values.

Rev. B | Page 17 of 48

AD9739 Data Sheet

SERIAL PORT INTERFACE (SPI) REGISTER

SPI REGISTER MAP DESCRIPTION

The AD9739 contains a set of programmable registers described in Tabl e 1 0 that are used to configure and monitor various internal parameters. Note the following points when programming the

AD9739 SPI registers:

• Registers pertaining to similar functions are grouped

together and assigned adjacent addresses.

• Bits that are undefined within a register should be assigned

a 0 when writing to that register.

• Registers that are undefined should not be written to.

• A hardware or software reset is recommended upon

power-up to place SPI registers in a known state.

• A SPI initialization routine is required as part of the boot

process. See Tab l e 3 1 and Tabl e 32 for example procedures.

Reset

Issuing a hardware or software reset places the AD9739 SPI registers in a known state. All SPI registers (excluding 0x00) are set to their default states as described in Tabl e 1 0 upon issuing a reset. After issuing a reset, the SPI initialization process need only write to registers that are required for the boot process as well as any other register settings that must be modified, depending on the target application.

Although the AD9739 does feature an internal power-on-reset (POR), it is still recommended that a software or hardware reset be implemented shortly after power-up. The internal reset signal is derived from a logical OR operation from the internal POR signal, the RESET pin, and the software reset state. A software reset can be issued via the reset bit (Register 0x00, Bit 5) by toggling the bit high then low. Note that, because the MSB/LSB format may still be unknown upon initial power-up (that is, internal POR is unsuccessful), it is also recommended that the bit settings for Bits[7:5] be mirrored onto Bits[2:0] for the instruction cycle that issues a software reset. A hardware reset can be issued from a host or external supervisory IC by applying a high pulse with a minimum width of 40 ns to the RESET pin (that is, Pin F14). RESET should be tied to VSS if unused.

Table 8. SPI Registers Pertaining to SPI Options

Address (Hex) Bit Description

0x00

7 Enable 3-wire SPI 6 Enable SPI LSB first 5 Software reset

SPI OPERATION

The serial port of the AD9739 shown in Figure 34 has a 3- or 4-wire SPI capability, allowing read/write access to all registers that configure the device’s internal parameters. It provides a flexible, synchronous serial communications port, allowing easy interface to many industry-standard microcontrollers and microprocessors. The 3.3 V serial I/O is compatible with most synchronous transfer formats, including the Motorola® SPI and the Intel® SSR protocols.

SDO (PIN H14)

SDIO (PIN G14)

SCLK (PIN H13)

CS (PIN G13)

Figure 34. AD9739 SPI Port

The default 4-wire SPI interface consists of a clock (SCLK), serial port enable (

), serial data input (SDIO), and serial data output (SDO). The inputs to SCLK, trigger with a nominal hysteresis of 0.4 V centered about VDD33/2.

The maximum frequency for SCLK is 20 MHz. The SDO pin is active only during the transmission of data and remains threestated at any other time.

A 3-wire SPI interface can be enabled by setting the SDIO_DIR bit (Register 0x00, Bit 7). This causes the SDIO pin to become bidirectional such that output data only appears on the SDIO pin during a read operation. The SDO pin remains three-stated in a 3-wire SPI interface.

Instruction Header Information

MSB LSB

17 16 15 14 13 12 11 10 R/W

A6 A5 A4 A3 A2 A1 A0

An 8-bit instruction header must accompany each read and write operation. The MSB is a R/

W indicating a read operation. The remaining seven bits specify the address bits to be accessed during the data transfer portion. The eight data bits immediately follow the instruction header for both read and write operations. For write operations, registers change immediately upon writing to the last bit of each transfer

byte.

can be raised after each sequence of eight bits (except the last byte) to stall the bus. The serial transfer resumes when CS

is lowered. Stalling on nonbyte boundaries resets the SPI.

AD9739

SPI PORT

07851-034

, and SDIO contain a Schmitt

indicator bit with logic high

Rev. B | Page 18 of 48

Data Sheet AD9739

The AD9739 serial port can support both most significant bit (MSB) first and least significant bit (LSB) first data formats. Figure 35 illustrates how the serial port words are formed for the MSB first and LSB first modes. The bit order is controlled by the SDIO_DIR bit (Register 0x00, Bit 7). The default value is 0, MSB first. When the LSB first bit is set high, the serial port interprets both instruction and data bytes LSB first.

SCLK

SDATA

SCLK

SDATA

INSTRUCTI ON CYCLE

R/W

A3A1 A2A0 A4

Figure 35. SPI Timing, MSB First (Upper) and LSB First (Lower)

DATA TRANSFER CYCLE

A1A3 A2A4N1N1N2

DATA TRANSFER CYCLEINSTRUCTI ON CYCLE

R/W

D01D1

D1ND0

D6ND7

07851-035

Figure 36 illustrates the timing requirements for a write operation to the SPI port. After the serial port enable (

) signal goes low, data (SDIO) pertaining to the instruction header is read on the rising edges of the clock (SCLK). To initiate a write operation, the read/not-write bit is set low. After the instruction header is read, the eight data bits pertaining to the specified register are shifted into the SDIO pin on the rising edge of the next eight clock cycles.

Figure 37 illustrates the timing for a 3-wire read operation to the SPI port. After

goes low, data (SDIO) pertaining to the instruction header is read on the rising edges of SCLK. A read operation occurs if the read/not-write indicator is set high. After the address bits of the instruction header are read, the eight data bits pertaining to the specified register are shifted out of the SDIO pin on the falling edges of the next eight clock cycles.

Figure 38 illustrates the timing for a 4-wire read operation to the SPI port. The timing is similar to the 3-wire read operation with the exception that data appears at the SDO pin only, while the SDIO pin remains at high impedance throughout the operation. The SDO pin is an active output only during the data transfer phase and remains three-stated at all other times.

SCLK

SDIO

SCLK

R/W

LOW

N1 N0

7851-036

Figure 36. SPI Write Operation Timing

CLK

SDIO

SCLK

R/W

LOW

07851-037

Figure 37. SPI 3-Wire Read Operation Timing

SCLK

SDIO

SCLK

R/W

LOW

SDO

07851-038

Figure 38. SPI 4-Wire Read Operation Timing

Rev. B | Page 19 of 48

AD9739 Data Sheet

SPI REGISTER MAP

Table 9. Full Register Map (N/A = Not Applicable)

Name

Mode 00 SDIO_DIR LSB/MSB Reset N/A N/A N/A N/A N/A 0x00 Power-

Down CNT_

CLK_DIS IRQ_EN 03 N/A N/A SYNC_

IRQ_REQ 04 N/A N/A SYNC_

RSVD 05 N/A N/A N/A N/A N/A N/A N/A N/A N/A FSC_1 06 FSC[7] FSC[6] FSC[5] FSC[4] FSC[3] FSC[2] FSC[1] FSC[0] 0x00 FSC_2 07 Sleep N/A N/A N/A N/A N/A FSC[9] FSC[8] 0x02 DEC_

CNT RSVD 09 N/A N/A N/A N/A N/A N/A N/A N/A N/A LVDS_

CNT DIG_

STAT LVDS_

STAT1 LVDS_

STAT2 RSVD 0E N/A N/A N/A N/A N/A N/A N/A N/A N/A RSVD 0F N/A N/A N/A N/A N/A N/A N/A N/A N/A LVDS_

REC_ CNT1

LVDS_ REC_ CNT2

LVDS_ REC_ CNT3

LVDS_ REC_ CNT4

LVDS_ REC_ CNT5

LVDS_ REC_ CNT6

LVDS_ REC_ CNT7

LVDS_ REC_ CNT8

LVDS_ REC_ CNT9

LVDS_ REC_ STAT1

LVDS_ REC_ STAT2

Hex Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default

01 N/A N/A LVDS_

02 N/A N/A N/A N/A CLKGEN_PD N/A REC_CNT_

08 N/A N/A N/A N/A N/A N/A DAC_DEC[1] DAC_DEC[0] 0x00

0A N/A N/A N/A N/A HNDOFF_

0B HNDOFF_

Fall[3]

0C SUP/HLD_

Edge1

0D SUP/HLD_

SYNC

10 SYNC_

FLG_RST

11 SMP_DEL[1] SMP_

12 SMP_DEL[9] SMP_

13 DCI_DEL[3] DCI_

14 CLKDIVPH[1] CLKDIVPH[0] DCI_

15 SYNC_

GAIN[1]

16 N/A SYNCO_

17 SYNCSH_

DEL[0]

18 SYNCSH_

DEL[8]

19 SMP_DEL[1] SMP_DEL[0] N/A N/A SMP_

1A SMP_DEL[9] SMP_

HNDOFF_ Fall[2]

N/A DCI_

SUP/HLD_ Edge0

SYNC_ LOOP_ON

DEL[0]

DEL[8]

DEL[2]

SYNC_ GAIN[0]

DEL[6]

N/A N/A N/A N/A N/A N/A N/A 0x00

SYNCSH_ DEL[7]

DEL[8]

DRVR_PD

LST_EN

LST_IRQ

HNDOFF_ Fall[1]

PHS3 SYNC_

SAMP1

SYNC_ MST/SLV

FINE_ DEL_ MID[3]

SMP_ DEL[7]

DCI_ DEL[1]

DEL[9]

SYNCOUT_ PH[1]

SYNCO_ DEL[5]

SYNCSH_ DEL[6]

SMP_ DEL[7]

LVDS_ RCVR_PD

SYNC_ LCK_EN

SYNC_ LCK_IRQ

HNDOFF_ Fall[0]

DCI_ PHS1

SYNC_ SAMP0

SYNC_ CNT_ENA

FINE_ DEL_ MID[2]

SMP_ DEL[6]

DCI_ DEL[0]

DCI_ DEL[8]

SYNCOUT_ PH[0]

SYNCO_ DEL[4]

SYNCSH_ DEL[5]

SMP_ DEL[6]

N/A N/A CLK_

MU_LST_EN MU_LCK_EN RCV_

MU_LST_ IRQ

CHK_RST HNDOFF_

Rise[3] DCI_PRE_

PH2 LVDS1_HI LVDS1_LO LVDS0_HI LVDS0_LO RNDM/0

N/A RCVR_

FINE_DEL_ MID[1]

SMP_ DEL[5]

FINE_DEL_ SKW[3]

DCI_ DEL[7]

LCKTHR[3] LCKTHR[2] LCKTHR[1] LCKTHR[0] 0x42

SYNCO_ DEL[3]

SYNCSH_ DEL[4]

FINE_ DEL[3]

SMP_ DEL[5]

MU_LCK_ IRQ

N/A LVDS_

HNDOFF_ Rise[2]

DCI_PRE_ PH0

FLG_RST

FINE_DEL_ MID[0]

SMP_ DEL[4]

FINE_DEL_ SKW[2]

DCI_ DEL[6]

SYNCO_ DEL[2]

SYNCSH_ DEL[3]

SMP_ FINE_ DEL[2]

SMP_ DEL[4]

RCVR_PD

CLK

LST_EN RCVLST_

IRQ

Bias[1] HNDOFF_

Rise[1] DCI_PST_

PH2

RCVR_ LOOP_ON

RCVR_ GAIN[1]

SMP_ DEL[3]

FINE_DEL_ SKW[1]

DCI_ DEL[5]

SYNCO_ DEL[1]

SYNCSH_ DEL[2]

SMP_ FINE_ DEL[1]

SMP_ DEL[3]

DAC_ BIAS_PD

MU_CNT_ CLK

RCV_ LCK_EN

RCVLCK_ IRQ

LVDS_ Bias[0]

HNDOFF_ Rise[0]

DCI_PST_ PH0

RCVR_ CNT_ENA

RCVR_ GAIN[0]

SMP_ DEL[2]

FINE_DEL_ SKW[0]

DCI_ DEL[4]

SYNCO_ DEL[0]

SYNCSH_ DEL[1]

SMP_ FINE_ DEL[0]

SMP_ DEL[2]

0x00

0x03

0x00

RNDM

0x42

0xDD

0x29

0x71

0x0A

0x00

0xC7

0x29

Rev. B | Page 20 of 48

Data Sheet AD9739

Hex

Name

LVDS_ REC_ STAT3

LVDS_ REC_ STAT4

LVDS_ REC_ STAT5

LVDS_ REC_ STAT6

LVDS_ REC_ STAT7

LVDS_ REC_ STAT8

LVDS_ REC_ STAT9

CROSS_ CNT1

CROSS_ CNT2

PHS_ DET

MU_ DUTY

MU_ CNT1

MU_ CNT2

MU_ CNT3

MU_ CNT4

MU_ STAT1

RSVD 2B N/A N/A N/A N/A N/A N/A N/A N/A N/A RSVD 2C N/A N/A N/A N/A N/A N/A N/A N/A N/A ANA_

CNT1 ANA_

CNT2 RSVD 34 N/A N/A N/A N/A N/A N/A N/A N/A N/A PART ID 35 ID[7] ID[6] ID[5] ID[4] ID[3] ID[2] ID[1] ID[0] 0x20

Addr

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default

1B DCI_DEL[1] DCI_DEL[0] N/A N/A SYNCOUT

1C DCI_DEL[9] DCI_

1D FINE_DEL_

PST[3]

1E N/A SYNCO_

1F SYNCSH_

DEL[0]

20 SYNCSH_

DEL[8]

21 SYNC_

TRK_ON

22 N/A N/A N/A DIR_P CLKP_

23 N/A N/A N/A DIR_N CLKN_

24 N/A N/A CMP_BST PHS_DET

25 MU_

DUTYAUTO_EN

26 N/A Slope Mode[1] Mode[0] Read Gain[1] Gain[0] Enable 0x42

27 MUDEL[0] SRCH_MODE

28 MUDEL[8] MUDEL[7] MUDEL[6] MUDEL[5] MUDEL[4] MUDEL[3] MUDEL[2] MUDEL[1] 0x00

29 SEARCH_TOL Retry CONTRST Guard[4] Guard[3] Guard[2] Guard[1] Guard[0] 0x0B

2A N/A N/A N/A N/A N/A N/A MU_LOST MU_LKD 0x00

32 HDRM[7] HDRM[6] HDRM[5] HDRM[4] HDRM[3] HDRM[2] HDRM[1] HDRM[0] 0xCA

33 N/A N/A N/A N/A N/A N/A MSEL[1] MSEL[0] 0x03

DEL[8]

FINE_DEL_ PST[2]

DEL[6]

N/A N/A N/A N/A N/A N/A N/A 0x00

SYNCSH_ DEL[7]

SYNC_ INIT_ON

POS/NEG ADJ[5] ADJ[4] ADJ[3] ADJ[2] ADJ[1] ADJ[0] 0x00

[1]

DCI_ DEL[7]

FINE_DEL_ PST[1]

SYNCO_ DEL[5]

SYNCSH_ DEL[6]

SYNC_ LST_LCK

SRCH_MODE [0]

DCI_ DEL[6]

FINE_DEL_ PST[0]

SYNCO_ DEL[4]

SYNCSH_ DEL[5]

SYNC_LCK RCVR_

AUTO_EN

SET_PHS[4] SET_PHS[3] SET_PHS[2] SET_PHS[1] SETPHS[0] 0x40

PH[1]

DCI_ DEL[5]

FINE_DEL_ PRE[3]

SYNCO_ DEL[3]

SYNCSH_ DEL[4]

TRK_ON

OFFSET[3]

OFFSET[3] Bias[3] Bias[2] Bias[1] Bias[0] 0x00

SYNCOUT PH[0]

DCI_ DEL[4]

FINE_DEL_ PRE[2]

SYNCO_ DEL[2]

SYNCSH_ DEL[3]

RCVR_ FE_ON

CLKP_ OFFSET[2]

CLKN_ OFFSET[2]

CLKDIV PH[1]

DCI_ DEL[3]

FINE_DEL_ PRE[1]

SYNCO_ DEL[1]

SYNCSH_ DEL[2]

RCVR_LST RCVR_LCK 0x00

CLKP_ OFFSET[1]

CLKN_ OFFSET[1]

CLKDIV PH[0]

DCI_ DEL[2]

FINE_DEL_ PRE[0]

SYNCO_ DEL[0]

SYNCSH_ DEL[1]

CLKP_ OFFSET[0]

CLKN_ OFFSET[0]

0xC0

0x29

0x86

0x00

Rev. B | Page 21 of 48

AD9739 Data Sheet

SPI PORT CONFIGURATION AND SOFTWARE RESET

Table 10. SPI Port Configuration and Software Reset Register

Address (Hex)

0x00

Name Bit R/W

SDIO_DIR 7 R/W 0 0 = 4-wire SPI, 1 = 3-wire SPI. LSB/MSB 6 R/W 0 0 = MSB first, 1 = LSB first. Reset 5 R/W 0

POWER-DOWN LVDS INTERFACE AND TXDAC®

Table 11. Power-Down LVDS Interface and TxDAC Register

Address (Hex)

0x01

Name Bit R/W

LVDS_DRVR_PD 5 R/W 0 LVDS_RCVR_PD 4 R/W 0 CLK_RCVR_PD 1 R/W 0 DAC_BIAS_PD 0 R/W 0

CONTROLLER CLOCK DISABLE

Default Setting

Comments

Software reset is recommended before modification of other SPI registers from the default setting. Setting the bit to 1 causes all registers (except 0x00) to be set to the default setting. Setting the bit to 0 corresponds to the inactive state, allowing the user to modify registers from the default setting.

Default Setting

Comments

Power-down of the LVDS drivers/receivers and TxDAC. 0 = enable, 1 = disable.

Table 12. Controller Clock Disable Register

Address (Hex) Name Bit R/W

0x02

CLKGEN_PD 3 R/W 0

REC_CNT_CLK 1 R/W 1 MU_CNT_CLK 0 R/W 1

Default Setting Comments

INTERRUPT REQUEST (IRQ) ENABLE/STATUS

Table 13. Interrupt Request (IRQ) Enable/Status Register

Address (Hex) Name Bit R/W

0x03

0x04

SYNC_LST_EN 5 W 0 SYNC_LCK_EN 4 W 0 MU_LST_EN 3 W 0 MU_LCK_EN 2 W 0 RCV_LST_EN 1 W 0 RCV_LCK_EN 0 W 0 SYNC_LST_IRQ 5 R 0 SYNC_LCK_IRQ 4 R 0 MU_LST_IRQ 3 R 0 MU_LCK_IRQ 2 R 0 RCV_LST_IRQ 1 R 0 RCV_LCK_IRQ 0 R 0

Default Setting Comments

This register enables the sync, mu, and LVDS Rx controllers to update their corresponding IRQ status bits in Register 0x04, which defines whether the controller is locked (LCK) or unlocked (LST). 0 = disable (resets the status bit). 1 = enable.

This register indicates the status of the controllers. For LCK_IQR bits: 0 = lost locked, 1 = locked. For LST_IQR bits: 0 = not lost locked, 1 = unlocked. Note that, if the controller IRQ is serviced, the relevant bits in Register 0x03 should be reset by writing 0, followed by another write of 1 to enable.

Internal CLK distribution enable: 0 = enable, 1 = disable.

LVDS receiver and Mu controller clock disable. 0 = disable, 1 = enable.

Rev. B | Page 22 of 48

Data Sheet AD9739

TxDAC FULL-SCALE CURRENT SETTING (I

) AND SLEEP

OUTFS

Table 14. TxDAC Full-Scale Current Setting (I

Address (Hex)

0x06 FSC_1 [7:0] R/W 0x00 0x07

Name Bit R/W

FSC_2 [1:0] R/W Sleep 7 R/W

Default Setting

0x02

) and Sleep Register

OUTFS

Comments

Sets the TxDAC I I

= 0.0226 × FSC[9:0] + 8.58, where FSC = 0 to 1023.

OUTFS

0 = enable DAC output, 1 = disable DAC output (sleep).

current between 8 mA and 31 mA (default = 20 mA).

OUTFS

TxDAC QUAD-SWITCH MODE OF OPERATION

Table 15. TxDAC Quad-Switch Mode of Operation Register

Address (Hex) Name Bit R/W

0x08 DAC-DEC [1:0] R/W 0x00

Default Setting Comments

DCI PHASE ALIGNMENT STATUS

Table 16. DCI Phase Alignment Status Register

Address (Hex) Name Bit R/W

0x0C

DCI_PRE_PH0 2 R 0

DCI_PST_PH0 0 R 0

Default Setting Comments

0 = DCI rising edge is after the PRE delayed version of the Phase 0 sampling edge. 1 = DCI rising edge is before the PRE delayed version of the Phase 0 sampling edge.

0 = DCI rising edge is after the POST delayed version of the Phase 0 sampling edge. 1 = DCI rising edge is before the POST delayed version of the Phase 0 sampling edge.

SYNC_IN PHASE ALIGNMENT STATUS

0x00 = normal baseband mode. 0x01 = return-to-zero mode. 0x02 = mix mode.

Table 17. SYNC_IN Phase Alignment Status Register

Address (Hex) Name Bit R/W

0x0D

SYNC_IN_PH90 5 R 0

SYNC_IN_PH0 4 R 0

Default Setting Comments

DATA RECEIVER CONTROLLER CONFIGURATION

Table 18. Data Receiver Controller Configuration Register

Address (Hex)

0x10

Name Bit R/W

SYNC_FLG_RST 7 W 0 Sync controller flag reset. Write 1 followed by 0 to reset flags. SYNC_LOOP_ON 6 R/W 1

SYNC_MST/SLV 5 R/W 0 Sync controller configuration. 0 = slave, 1 = master. SYNC_CNT_ENA 4 R/W 0 Sync controller enable. 0 = disable, 1 = enable RCVR_FLG_RST 2 W 0 Data receiver controller flag reset. Write 1 followed by 0 to reset flags. RCVR_LOOP_ON 1 R/W 1

RCVR_CNT_ENA 0 R/W 0 Data receiver controller enabled. 0 = disable, 1 = enable.

Default Setting

Comments

0 = disable, 1 = enable. Enable for master only. When enabled, sync controller generates an IRQ when master falls out of lock and automatically begins search/track routine.

0 = disable, 1 = enable. When enabled, the data receiver controller generates an IRQ; it falls out of lock and automatically begins a search/track routine.

0 = SYNCIN rising edge is after Phase 90 sampling edge. 1 = SYNCIN rising edge is before Phase 90 sampling edge.

0 = SYNCIN rising edge is after Phase 0 sampling edge. 1 = SYNCIN rising edge is before Phase 0 sampling edge.

Rev. B | Page 23 of 48

AD9739 Data Sheet

DATA RECEIVER CONTROLLER_DATA SAMPLE DELAY VALUE

Table 19. Data Receiver Controller_Data Sample Delay Value Register

Address (Hex)

0x11 SMP_DEL[1:0] [7:6] R/W 11

0x12 SMP_DEL[9:2] [7:0] R/W 0x25

Name Bit R/W

DATA AND SYNC RECEIVER CONTROLLER_DCI DELAY VALUE/WINDOW AND PHASE ROTATION

Table 20. Data and Sync Receiver Controller_DCI Delay Value/Window and Phase Rotation Register

Address (Hex)

0x14

0x15

Name Bit R/W

DCI_DEL[3:0] [7:4] R/W 0111 Refer to the DCI_DEL description in Register 0x14. 0x13

FINE_DEL_SKEW [3:0] R/W 0001

CLKDIVPH[1:0] [7:6] R/W 00

DCI_DEL[9:4] [5:0] R/W 001010

SYNC GAIN[1:0] [7:6] R/W 00 Sets the sync tracking gain (optimal value is 1).

Default Setting

Comments

Controller enabled: the 10-bit value (with a maximum of 332) represents the start value for the delay line used by the state machine to sample data. Leave at the default setting of 167, which represents the midpoint of the delay line. Controller disabled: the value sets the actual value of the delay line.

Comments

A 4-bit value sets the difference (that is, window) for the DCI PRE and POST sampling clocks. Leave at the default value of 1 for a narrow window.

Relative phase of internal div-by-4 circuit. This feature allows phase rotation in 90° increments (that is, 1 count) to extend Rx controllers locking range for clock rates between 0.8 GSPS to 1.6 GSPS (only valid with sync controller disabled).

Controller enabled: the 10-bit value (with a maximum of 332) represents the start value for the delay line used by the state machine to sample the DCI input. Leave at the default setting of 167, which represents the midpoint of the delay line. Controller disabled: the value sets the actual value of the delay line.

SYNCOUT_PH[1:0] [5:4] R/W 00 Readback of the present SYNC_OUT phase selection.

LCKTHR[3:0] [3:0] R/W 0000 Sets the difference between the sample and DCI delays to lock (optimal value is 2).

0x16 SYNCO_DEL[6:0] [6:0] R/W 0x00

0x17 SYNCSH_DEL[0] [7] R/W 0x00

0x18 SYNCSH_DEL[8:1] [7:0] R/W 0x00

Sets the sync output delay value when the synch controller is disabled; otherwise, is the read status of the sync output delay value when sync is enabled.

Sets the sync setup and hold delay value when the synch controller is disabled; otherwise, is the read status of sync setup and hold value when sync is enabled.

DATA RECEIVER CONTROLLER_DELAY LINE STATUS AND SYNC CONTROLLER SYNC_OUT STATUS

Table 21. Data Receiver Controller_Delay Line Status and Sync Controller SYNC_OUT Status Register

Address (Hex) Name Bit R/W

0x19 SMP_DEL[1:0] [7:6] R 00 0x1A SMP_DEL[9:2] [7:0] R 0x00 0x1B

0x1C DCI_DEL[9:2] [7:0] R 0x00

SYNCOUT_PH[1:0] 3:2 R 00 CLKDIV PH[1:0] 1:0 R 00 DCI_DEL[1:0] [7:6] R 00

Default Setting Comments

The actual value of the DCI and data delay lines determined by the data receiver controller (when enabled) after the state machine completes its search and enters track mode. Note that these values should be equal.

SYNCOUT_PH provides phase status (0/90/180/270) of phase select mux, while CLKDIVPH provides phase status of data receiver controller (Register 0x14).

Rev. B | Page 24 of 48

Data Sheet AD9739

SYNC AND DATA RECEIVER CONTROLLER LOCK/TRACKING STATUS

Table 22. Sync and Data Receiver Controller Lock/Tracking Status Register

Address (Hex)

0x21

Name Bit R/W

SYNC_TRK_ON 7 R 0 SYNC_LST 5 R 0 SYNC_LCK 4 R 0 RCVR_TRK_ON 3 R 0 RCVR_LST 1 R 0

RCVR_LCK 0 R 0

CLK INPUT COMMON MODE

Table 23. CLK Input Common Mode Register

Address (Hex) Name Bit R/W

DIR_P 4 R/W 0 0x22 CLKP_OFFSET[3:0] [3:0] R/W 0000 DIR_N 4 R/W 0 0x23 CLKN_OFFSET[3:0] [3:0] R/W 0000

Default Setting Comments

Default Setting

DIR_P and DIR_N: 0 = VCM at the DACCLK_P input decreases with the offset value. 1 = VCM at the DACCLK_P input increases with the offset value. CLKx_OFFSET sets the magnitude of the offset for the DACCLK_P and DACCLK_N inputs. For optimum performance, set to 1111.

Comments

SYNC_TRK_ON and RCVR_TRK_ON: 0 = tracking not established. 1 = tracking established. SYNC_LCK and RCVR_LCK: 0 = controller is not locked. 1 = controller is locked. SYNC_LST and RCVR_LST: 0 = lock has not been lost. 1 = lock has been lost at some point.

MU CONTROLLER CONFIGURATION AND STATUS

Table 24. Mu Controller Configuration and Status Register

Address (Hex) Name Bit R/W

CMP_BST 5 R/W 0 0x24

4 R/W 0

7 R/W 0 Mu controller duty cycle enable. Note that this bit should always be set to 1 to enable.

0x25

0x26

0x27

PHS_DET AUTO_EN

MU_DUTY AUTO_EN

Slope 6 R/W 1

Mode[1:0] [5:4] R/W 00

Read 3 R/W 0 Set to 1 to read the current value of the Mu delay line in.

Gain[1:0] [2:1] R/W 01 Sets the mu controller tracking gain. Recommended to leave at the default 01 setting.

Enable 0 R/W 0

MUDEL[0] 7 R/W 0 The LSB of the 9-bit MUDEL setting. SRCH_MODE[1:0] [6:5] R/W 0

SET_PHS[4:0] [4:0] R/W 0

Default Setting Comments

Phase detector enable and boost bias bits. Note that both bits should always be set to 1 to enable these functions.

Mu controller phase slope lock. 0 = negative slope, 1 = positive slope. Refer to Table 2 8 for optimum setting.

Sets the mu controller mode of operation. 00 = search and track (recommended). 01 = search only. 10 = track.

1 = enable the mu controller. 0 = disable the mu controller.

Sets the direction in which the mu controller searches (from its initial MUDEL setting) for the optimum mu delay line setting that corresponds to the desired phase/slope setting (that is, SET_PHS and slope ). 00 = down. 01 = up. 10 = down/up (recommended).

Sets the target phase that the mu controller locks to with a maximum setting of 16. Refer to Table 2 8 for optimum setting.

Rev. B | Page 25 of 48

AD9739 Data Sheet

Address (Hex) Name Bit R/W

0x28 MUDEL[8:1] [7:0]

0x29

0x2A

SEARCH_TOL 7 R/W 0

Retry 6 R/W 0

CONTRST 5 R/W 0

Guard[4:0] 4 R/W 01011

MU_LST 1 R 0

MU_LKD 0 R 0

Default Setting Comments

W 0x00

R 0x00

With enable (Bit 0, Register 0x26) set to 0, this 9-bit value represents the value that the mu delay is set to. Note that the maximum value is 432. With enable set to 1, this value represents the mu delay value at which the controller begins its search. Setting this value to the delay line midpoint of 216 is recommended.

When read (Bit 3, Register 0x26) is set to 1, the value read back is equal to the value written into the register when enable = 0 or the value that the mu controller locks to when enable = 1.

0 = not exact (can find a phase within two values of the desired phase). 1 = finds the exact phase that is targeted (optimal setting).

0 = stop the search if the correct value is not found. 1 = retry the search if the correct value is not found.

Controls whether the controller resets or continues when it does not find the desired phase. 0 = continue (optimal setting). 1 = reset.

Sets a guard band from the beginning and end of the mu delay line which the mu controller does not enter into unless it does not find a valid phase outside the guard band (optimal value is Decimal 11 or 0x0B).

0 = mu controller has not lost lock. 1 = mu controller has lost lock.

0 = mu controller is not locked. 1= mu controller is locked.

PART ID

Table 25. Part ID Register

Default

Address (Hex) Name Bit R/W

0x35 PART_ID [7:0] R 0x20 Part ID number.

Setting Comments

Rev. B | Page 26 of 48

Data Sheet AD9739

THEORY OF OPERATION

Figure 39 shows a top-level functional diagram of the AD9739. A high performance TxDAC core delivers a signal dependent, differential current (nominal ±10 mA) to a balanced load referenced to ground. The frequency of the clock signal appearing at the AD9739 differential clock receiver, DACCLK, sets the TxDAC’s update rate. This clock signal, which serves as the master clock, is routed directly to the TxDAC as well as to a clock distribution block that generates all critical internal and external clocks.

SDIO

SDO

SCLK

DCI

DCO

SYNC_OUT

SYNC_IN

RESET

SPI

DB0[13:0]DB1[13:0]

Figure 39. Functional Block Diagram of the AD9739

LVDS DDR

DATA

CONTRO LLER

LVDS DDR

CLK DISTRIBUTI ON

(DIV-BY-4)

SYNC-

CONTRO LLER

RECEIVER

IRQ

AD9739

DAC BIAS

4-TO-1

DATA ASSEMBLER



1.2V

VREF

I120

TxDAC

CORE

DATA

LATCH

DLL

DACCLK

IOUTP

IOUTN

(MU CONTROL LER)

07851-039

The AD9739 includes two 14-bit LVDS data ports (DB0 and DB1) to reduce the data interface rate to ½ the TxDAC update rate. The host processor drives deinterleaved data with offset binary format onto the DB0 and DB1 ports, along with an embedded DCI clock that is synchronous with the data. Because the interface is double data rate (DDR), the DCI clock is essentially an alternating 010101……….01010 bit pattern with a frequency equal to ¼ the TxDAC update rate (f

). To simplify synchronization with the

DAC

host processor, the AD9739 passes an LVDS clock output (DCO) that is also equal to the DCI frequency.

The AD9739 data receiver controller generates an internal sampling clock offset by 90° from the DCI to sample the input data on the DB0 and DB1 ports. When enabled and configured properly for track mode, it ensures proper data recovery between the host and the AD9739 clock domains. The data receiver controller has the ability to track several hundreds of ps of drift between these clock domains, typically caused by supply and temperature variation.

As mentioned, the host processor provides the AD9739 with a deinterleaved data stream such that the DB0 and DB1 data ports receive alternating samples (that is, odd/even data streams). The

AD9739 data assembler is used to reassemble (that is, multiplex)

the odd/even data streams into their original order before delivery into the TxDAC for signal reconstruction. The pipeline delay from a sample being latched into the data port to when it appears at the DAC output is on the order of 78 (±) DACCLK cycles. Applications that require matching pipeline delays (that is, synchronization) between multiple AD9739s can use the SYNC controller. The SYNC controller phase aligns the outputs of one or more AD9739 devices (that is,. slaves) to a master

AD9739 device.

The AD9739 includes a delay lock loop (DLL) circuit controlled via a mu controller to optimize the timing hand-off between the

AD9739 digital clock domain and TxDAC core. Besides ensuring

proper data reconstruction, the TxDAC’s ac performance is also dependent on this critical hand-off between these clock domains with speeds of up to 2.5 GSPS. Once properly initialized and configured for track mode, the DLL maintains optimum timing alignment over temperature, time, and power supply variation.

A SPI interface is used to configure the various functional blocks as well as monitor their status for debug purposes. Proper operation of the AD9739 requires that controller blocks be initialized upon power-up. A simple SPI initialization routine is used to configure the controller blocks (see Figure 51 and Figure 52). An IRQ output signal is available to alert the host should any of the controllers fall out of lock during normal operation.

The following sections discuss the various functional blocks in more detail as well as their implications when interfacing to external ICs and circuitry. While a detailed description of the various controllers (and associated SPI registers used to configure and monitor) is also included for completeness, the recommended SPI boot procedure can be used to ensure reliable operation.

Rev. B | Page 27 of 48

AD9739 Data Sheet

LVDS DATA PORT INTERFACE

The AD9739 supports input data rates from 1.6 GSPS to 2.5 GSPS using dual LVDS data ports. The interface is source synchronous and double data rate (DDR) where the host provides an embedded data clock input (DCI) at f aligned with the data transitions. The data format is offset binary; however, twos complement format can be realized by reversing the polarity of the MSB differential trace. As shown in Figure 40, the host feeds the AD9739 with deinterleaved input data into two 14-bit LVDS data ports (DB0 and DB1) at ½ the DAC clock rate (that is, f

/2). The AD9739 internal data receiver controller

DAC

then generates a phase shifted version of DCI to register the input data on both the rising and falling edges.

HOST

PROCESSOR

EVEN DATA

SAMPLES

DATA

ODD DATA

SAMPLES

LVDS DDR DRI VER

DATA DEINTERLEAVER

DCI

DCO

Figure 40. Recommended Digital Interface Between the AD9739 and

As shown in Figure 41, the DCI clocks edges must be coincident with the data bit transitions with minimum skew, jitter, and intersymbol interference. To ensure coincident transitions with the data bits, the DCI signal should be implemented as an additional data line with an alternating (010101…) bit sequence from the same output drivers used for the data. Maximizing the opening of the eye in both the DCI and data signals improves the reliability of the data port interface. Differential controlled impedance traces of equal length (that is, delay) should also be used between the host processor and AD9739 input to limit bit-to-bit skew.

/4 with its rising and falling edges

DAC

AD9739

14 × 2

DB0[13:0]

DAC

14 × 2

DB1[13:0]

1 × 2

DAC

DCI

DCO

DIV-BY-4

Host Processor

LVDS DDR

RECEIVER

LVDS DDR

RECEIVER

DATA

CONTROL LER

DAC

07851-040

The maximum allowable skew and jitter out of the host processor with respect to the DCI clock edge on each LVDS port is calculated as

MaxSkew + Jitter = Period(ns) − ValidWindow(ps) − Guard

= 800 ps − 344 ps − 100 ps

= 356 ps

where Va li dW in d ow (ps) is represented by t represented by t

in Figure 41.

GUARD

and Guard is

VA L I D

The minimum specified LVDS valid window is 344 ps, and a guard band of 100 ps is recommended. Therefore, at the maximum operating frequency of 2.5 GSPS, the maximum allowable FPGA and PCB bit skew plus jitter is equal to 356 ps.

For synchronous operation, the AD9739 provides a data clock output, DCO, to the host at the same rate as DCI (that is, f

DAC

/4) to maintain the lowest skew variation between these clock domains. Since the DCO signal is generated from a separate clock divider, its phase relationship relative to the f

/4 clocks

DAC

used by the data receiver controller will vary upon each power-up. Applications sensitive to this phase ambiguity (resulting in a ±2 DACCLK pipeline variation) should consider using the sync controller.

The host processor has a worst-case skew between DCO and DCI that is both implementation and process dependent. This worst-case skew can also vary an additional 30% over temperature and supply corners. The delay line within the data receiver controller can track a ±1.5 ns skew variation after initial lock. While it is possible for the host to have an internal PLL that generates a synchronous f

/4 from which the DCI signal is

DAC

derived, digital implementations that result in the shortest propagation delays result in the lowest skew variation.

The data receiver controller is used to ensure proper data hand-off between the host and AD9739 internal digital clock domains. The circuit shown in Figure 42 functions as a delay lock loop in which a 90

phase shifted version of the DCI clock input is used to sample the input data into the DDR receiver registers. This ensures that the sampling instance occurs in the middle of the data pattern eyes (assuming matched DCI and DBx[13:0] delays). Note that, because the DCI delay and sample delay clocks are derived from the div-by-4 circuitry, this 90° phase relationship holds as long as the delay settings (that is, DCI_DEL, SMP_DEL) are also matched.

2 × 1

DAC

DCI

VALID

DB0[13:0]

ND DB1[13:0]

VALID

GUARD

MAX SKEW

+ JITTER

07851-041

Figure 41. LVDS Data Port Timing Requirements

Rev. B | Page 28 of 48

Data Sheet AD9739

DATA RECEI VER CONT ROLLE R

DCI WINDOW PRE

DCI

DDR

DBx[13:1]

DCO

DDR

DCI WINDOW P OST

DCI WINDOW SAMPLE

DDR

SAMPLE

DDR

FINE

DELAY

PRE

FINE

DELAY

POST

FINE

DELAY

DDR

ELASTIC FIFO

DELAY

Figure 42. Top Level Diagram of the Data Receiver Controller

The div-by-4 circuit generates four clock phases that serve as inputs to the data receiver controller. All of the DDR registers in the data and DCI paths operate on both clock edges; however, for clarity purposes, only the phases (that is, 0

and 90o) corresponding to the positive edge of each path are shown. One of the div-by-4 phases is used to generate the DCO signal; therefore, the phase relationship between DCO and clocks fed into the controller remains fixed. Note that it is this attribute that allows possible factory calibration of images and clock spurs attributed to f

DAC

modulation of the critical DAC clock.

Once this data has been successively sampled into the first set of registers, an elastic FIFO is used to transfer the data into the AD9739 clock domain. To continuously track any phase variation between the two clock domains, the data receiver controller should always be enabled and placed into track mode (Register 0x10, Bit 1 and Bit 0). Tracking mode operates continuously in the background to track delay variations between the host and AD9739 clock domains. It does so by ensuring that the DCI signal is sampled within a very narrow window defined by two internally generated clocks (that is, PRE and PST), as shown in Figure 43.

STATE MACHINE/ TRACKING LOOP

DDR

DELAY

DCI DELAY

SAMPLE

DELAY

DCI

DELAY

PATH

SAMPLE

DELAY

PATH

DDR

TO SYNC

CONTROLLER

DATA TO CORE

FROM SYNC CONTRO LLER

SPI REG 0x14, BIT[7:6]

PHASE ROTATION

DIV-BY-4

180 270

DIV-BY-4

Proper sampling of the DCI signal can also be confirmed by monitoring the status of DCI_PRE_PH0 (Register 0x0C, Bit 2) and DCI_PST_PH0 (Register 0x0C, Bit 0). If the delay settings are correct, the state of DCI_ PRE_PH0 should be 0, and the state of DCI_PST_PH0 should be 1. Note that the states of these status bits may toggle occasionally due to cycle-to cycle jitter exceeding the window width. However, the controller averages these status bits over multiple clock cycles to ensure that the DCI signal falls within a programmable window.

DCI

FINE DELAY

PST

FINE DELAY

PRE

FINE_DEL_SKEW

Figure 43. Pre- and Post-Delay Sampling Diagram

The skew or window width (FINE_DEL_SKEW) is set via Register 0x13, Bits[3:0], with a maximum skew of approximately 180 ps and resolution of 12 ps. It is recommended that the skew be set to 36 ps (that is, Register 0x13 = 0x72) during initialization. The skew setting also affects the speed of the controller loop, with tighter skew settings corresponding to longer response time.

DAC

07851-042

07851-043

Rev. B | Page 29 of 48

AD9739 Data Sheet

Data Receiver Controller Initialization Description

The data controller should be initialized and placed into track mode as the second step in the SPI boot sequence. The following steps are recommended for the initialization of the data receiver controller:

1. Set FINE_DEL_SKEW to 2 for a larger DCI sampling

window (Register 0x13 = 0x72). Note that the default DCI_DEL and SMP_DEL settings of 167 are optimum.

2. Disable the controller before enabling (that is, Register

0x10 = 0x00).

3. Enable the Rx controller in two steps: Register 0x10 = 0x02

followed by Register 0x10 = 0x03.

4. Wait 135K clock cycles.

5. Read back Register 0x21 and confirm that it is equal to

0x05 to ensure that the DLL loop is locked and tracking.

6. Include this step for operation <1.6 GSPS. Read back the

DCI_DEL value to determine whether the value falls within a user-defined tracking guard band. If it does not, rotate CLKDIVPH by 1 (Register 0x14, Bits[7:6] and go back to Step 2.

Once the controller is enabled during the initial SPI boot process (see Ta b le 3 1 and Ta b le 3 2), the controller enters a search mode where it seeks to find the closest rising edge of the DCI clock (relative to a delayed version of an internal f

/4 clock)

DAC

by simultaneously adjusting the delays in the clocks used to register the DCI and data inputs. A state machine searches above and below the initial DCI_DEL value. The state machine first searches for the first rising edge above the DCI_DEL and then searches for the first rising edge below the DCI_DEL value. The state machine selects the closest rising edge and then enters track mode. It is recommended that the default midscale delay setting (that is, Decimal 167) for the DCI_DEL and SMP_DEL bits be kept to ensure that the selected edge remains closest to the delay line midpoint, thus providing the greatest range for tracking timing variations and preventing the controller from falling out of lock.

The adjustable delay span for these internal clocks (that is, DCI and sample delay) is nominally 4 ns. The 10-bit delay value is user programmable from the decimal equivalent code (0 to 384) with approximately 12 ps/LSB resolution via the DCI_DEL and SMP_DEL registers (via Register 0x11 thru Register 0x14). When the controller is enabled, it overwrites these registers with the delay value it converges upon. The minimum difference between this delay value and the minimum/maximum values (that is, 0 and 334) represents the guard band for tracking. Therefore, if the controller initially converges upon a DCI_DEL and SMP_DEL value between 80 and 304, the controller has a guard band of at least 80 code (approximately 1 ns) to track phase variations between the clock domains.

Upon initialization of the AD9739, a certain period of time is required for the data receiver controller to lock onto the DCI clock signal. Note that, due to its dependency on the mu controller and

Rev. B | Page 30 of 48

synchronization controller (optional), the data receiver controller should be enabled only after these other controllers have been enabled and established locked. All of the internal controllers operate at submultiples of the DAC update rate. The number of f

clock cycles required to lock onto the DCI clock is dependent

DAC

on whether the synchronization controller is enabled as shown in Tab l e 2 6 .

Table 26. Typical/Worst-Case Lock Times for LVDS Controller (Relative to 1/f

Synchronization Controller Typical Worst Case

Off 70K 135K Slave 70K 135K Master 300K 560K

DAC

)

During the SPI initialization process, the user has the option of polling Register 0x21 (Bit 0, Bit 1, and Bit 3) to determine if the data receiver controller is locked, has lost lock, or has entered into track mode before completing the boot sequence. Alternatively, the appropriate IRQ bit (Register 0x03 and Register 0x04) can be enabled such that an IRQ output signal is generated upon the controller establishing lock (see the Interrupt Requests section).

The data receiver controller can also be configured to generate an interrupt request (IRQ) upon losing lock. Losing lock can be caused by excessive jitter on the DCI input signal, disruption of the main DAC clock input, or loss of a power supply rail. To service the interrupt, the host can poll the RCVR_LCK bit (Register 0x21, Bit 0) to determine the current state of the controller. If this bit is cleared, the search/track procedure can be restarted by setting the RCVR_LOOP_ON bit in Register 0x10, Bit 1. After waiting the required lock time, the host can poll the RCVR_LCK bit to see if it has been set. Before leaving the interrupt routine, the RCVR_FLG_RST bit (Register 0x10, Bit 2) should be reset by writing a high followed by a low.

Data Receiver Operation at Lower Clock Rates

At clock rates below 1.6 GSPS, it is recommended to include provisions to rotate the CLKDIVPH setting in the SPI boot process. As previously mentioned, the delay line can be varied over a nominal 4 ns window. If the minimum specified clock rate of 800 MSPS is considered, a DCI clock rate of 200 MSPS corresponds to a 5 ns period, thus exceeding the delay line length. Therefore, it becomes possible that the initial startup phase from the div-by-4 circuit (and DCO output) is such that the data receiver controller can never establish initial lock upon power up.

If the clock rate is increased to 1600 MSPS (that is, DCI clock period of 2.5 ns), the controller will always be able to find at least two DCI clock edges, therefore, establish lock. However, should the DCI edges fall symmetrically (equal distance) from the initial DCI_DEL midscale setting, a guard band of ±0.75 ns (that is, (4.0 − 2.5)/2) results. Rotating the CLKDIVPH can result in an improvement in this case by skewing one of the DCI edges toward the DCI_DEL midscale value.

Data Sheet AD9739

Rotating the CLKDIVPH phase provides a means of adjusting the delay in course steps of f

/4. For example, in the 800 MSPS

DAC

and 1600 MSPS cases described above, rotating the CLKDIVPH setting by 1 corresponds to a delay shift of 5 ns and 2.5 ns, respectively. By adding an additional step in the SPI initialization routine for the data receiver controller, it becomes possible to increase the effective range of the delay line to ensure a DCI_DEL value that falls within a reasonable guard band.

LVDS Driver and Receiver Input

The AD9739 features a LVDS-compatible driver and receivers. The LVDS driver output used for the DCO and SYNC_OUT signal includes an equivalent 200  source resistor that limits its nominal output voltage swing to ±200 mV when driving a 100  load. The DCO output driver can be powered down via Register 0x01, Bit 5. An equivalent circuit is shown in Figure 44

DD33

DCO_N

V+

ESD ESD

V–

100Ω

VCM

V–

DCO_P

V+

COM

(VP + VN)/2

LOGIC BIT

EQUIVALENT

VP = 1.4V

P, N

EXAMPLE

Figure 46. LVDS Data Input Levels

DD33 = 3.3V

100Ω

LVDS INPUTS

(NO FAIL-SAFE)

GND

LVDS_1

LVD S

RECEIVER

1.4V

1.0V

0.4V

–0.4V

LOGIC 1

LOGIC 0

07851-046

VSS

07851-044

Figure 44. Equivalent LVDS Output

DD33

VP = 1.4V

R1 = 4.75 × 100/ N R2 = 2.50 × 100/ N

DCI_P

DBx[13:0]P

ESD

100Ω

ESD

DCI_N DBx[13:0]N

Figure 47. Resistor Network to Bias Unused LVDS Data Inputs

VSS

07851-045

Figure 45. Equivalent LVDS Input

The LVDS receivers include 100  termination resistors, as shown in Figure 45. These receivers meet the IEEE-1596.3-1996 reduced swing specification (with the exception of input hysteresis, which cannot be guaranteed over all process corners). Figure 46

The AD9739 LVDS inputs do not include fail-safe capability. Any unused data input pins should be biased with an external network or static driver. Figure 47 shows an external biasing network that can be used to place unused data bits into a known state. The resistor values for R1 and R2 are selected to establish a V

and VN of 1.4 V and 1.0 V, respectively, depending on the

number of unused digital inputs, N.

and Figure 47 show an example of nominal LVDS voltage levels seen at the input of the differential receiver with resulting commonmode voltage and equivalent logic level. The LVDS receivers can be powered down via Register 0x01, Bit 4.

Table 27. Example of LVDS Input Levels

Applied Voltages Resulting Differential Voltage Resulting Common-Model Voltage

VP (V) VN (V) V

P, N

Logic Bit Binary Equivalent

COM

1.4 1.0 +0.4 V 1.2 V 1

1.0 1.4 −0.4 V 1.2 V 0

1.0 0.8 +200 mV 900 mV 1

0.8 1.0 −200 mV 900 mV 0

100Ω

LVDS_2

LVDS_N

07851-047

Rev. B | Page 31 of 48

AD9739 Data Sheet

MU CONTROLLER

A delay lock loop (DLL) is used to optimize the timing between the internal digital and analog domains of the AD9739 such that data is successfully transferred into the TxDAC core at rates of up to 2.5 GSPS. As shown in Figure 48, the DAC clock is split into an analog and a digital path with the critical analog path leading to the DAC core (for minimum jitter degradation) and the digital path leading to a programmable delay line. Note that the output of this delay line serves as the master internal digital clock from which all other internal and external digital clocks are derived. The amount of delay added to this path is under the control of the mu controller, which optimizes the timing between these two clock domains and continuously tracks any variation (once in track mode) to ensure proper data hand-off.

14-BI

DAC

CLOCK

DATA

DIGIT AL

CIRCUITRY

DELAY

CONTROL LER

Figure 48. Mu Delay Controller Block Diagram

The mu controller adjusts the timing relationship between the digital and analog domains via a tapped digital delay line having a nominal total delay of 864 ps. The delay value is programmable to a 9-bit resolution (that is, 0 to 432 decimal) via the MUDEL register, resulting in a nominal resolution of 2 ps/LSB. Because a time delay maps to a phase offset for a fixed clock frequency, the control loop essentially compares the phase relationship between the two clock domains and adjusts the phase (that is, via a tapped delay line) of the digital clock such that it is at the desired fixed phase offset (SET_PHS) from the critical analog clock.

GUARD

BAND

DESIRED PHASE

MU PHASE

0 40 80 120 160 200 240 280 320 360 400 440

SEARCH START ING

LOCATION

Figure 49. Typical Mu Phase Characteristic Plot at 2.4 GSPS

DELAY

MU DELAY

14-BI

DATA

PHASE

DETECTOR

ANALOG

CIRCUITRY

IOUTP

IOUTN

GUARD

BAND

07851-048

07851-049

Figure 49 maps the typical mu phase characteristic at 2.4 GSPS vs. the 9-bit digital delay setting (MUDEL). The mu phase scaling is such that a value of 16 corresponds to 180 degrees. The critical keep-out window between the digital and analog domains occurs at a value of 0 (but can extend out to 2 depending on the clock rate). The target mu phase (and slope) is selected to provide optimum ac performance while ensuring that the mu controller for any device can establish and maintain lock. For example, while a slope and phase setting of −6 is considered optimum for operation between 1.6 GSPS and 2.5 GSPS, other values are required below 1.6 GSPS.

NOM_P1 SLOW_P1

FAST_P1

MU PHASE

0 40 80 120 160 200 240 280 320 360 400 440

DELAY LINE TAP

07851-050

Figure 50. Mu Phase Characteristics of Three Devices from Different Process

Lots at 1.2 GSPS

The mu phase characteristics can vary significantly among devices due to gm variations in the digital delay line that are sensitive to process skews (along with temperature and supply). As a result, careful selection of the target phase location is required such that the mu controller can converge upon this phase location for all devices. Figure 50 shows that mu phase characteristics of three devices at 25°C from slow, nominal, and fast skew lots at

1.2 GSPS. Note that a −6 mu phase setting does not map to any delay line tap setting for the fast process skew case; therefore, another target mu phase is recommended at this clock rate.

Tabl e 28 provides a list of recommended mu phase/slope settings over the specified clock range of the AD9739 based on the considerations previously described. These values should be used to ensure robust operation of the mu controller.

Table 28. Recommended Target Mu Phase Settings vs. Clock Rate

Clock Rate (GSPS) Slope MU Phase

0.8 − 6

0.9 − 4

1.0 + 5

1.1 + 8

1.2 + 12

1.3 − 12

1.4 − 10

1.5 − 8

1.6 to 2.5 − 6

Rev. B | Page 32 of 48

Data Sheet AD9739

After the mu controller completes its search and establishes lock on the target mu phase, it attempts to maintain a constant timing relationship between the two clock domains over the specified temperature and supply range. If the mu controller requests a mu delay setting that exceeds the tapped delay line range (that is, <0 or >432), the mu controller can lose lock, causing possible system disruption (that is, can generate IRQ or restart the search). To avoid this scenario, symmetrical guard bands are recommended at each end of the mu delay range. The guard band scaling is such that one LSB of Guard[4:0] (Register 0x29) corresponds to eight LSBs of MUDEL (Register 0x28). The recommended guard band setting of 11 (that is, Register 0x29 = 0xCB) corresponds to 88 LSBs, thus providing sufficient margin.

Mu Controller Initialization Description

The mu controller must be initialized and placed into track mode as a first step in the SPI boot sequence. The following steps are required for initialization of the mu controller. Note that the AD9739 data sheet specifications and characterization data are based on the following mu controller settings:

1. Turn on the phase detector with boost (Register 0x24 = 0x30).

2. Enable the mu delay controller duty-cycle correction

circuitry and specify the recommended slope for phase. (that is, Register 0x25 = 0x80 corresponds to a negative slope).

3. Specify search/track mode with a recommended target

phase, SET_PHS, of 6 (for example) and an initial MUDEL[8:0] setting of 216 (Register 0x27 = 0x46 and Register 0x28 = 0x6C).

4. Set search tolerance to exact and retry if the search fails

its initial attempt. Also, set the guard band to the recommended setting of 11 (Register 0x29 = 0xCB).

5. Set the mu controller tracking gain to the recommended

setting and enable the mu controller state machine (Register 0x26 = 0x03).

Upon completion of the last step, the mu controller begins a search algorithm that starts with an initial delay setting specified by the MUDEL register (that is, 216, which corresponds to the midpoint of the delay line). The initial search algorithm works by sweeping through different mu delay values in an alternating manner until the desired phase (that is, a SET_PHS of 4) is exactly measured. When the desired phase is measured, the slope of the phase measurement is then calculated and compared against the specified slope (slope = negative).

If everything matches, the search algorithm is finished. If not, the search continues in both directions until an exact match can be found or a programmable guard band is reached in one of the directions. When the guard band is reached, the search still continues but only in the opposite direction. If the desired phase is not found before the guard band is reached in the second direction, the search changes back to the alternating mode and continues looking within the guard band. The typical locking time for the mu controller is approximately 180K DAC cycles (at 2 GSPS ~ 75 µs).

The search fails if the mu delay controller reaches the endpoints. The mu controller can be configured to retry (Register 0x29, Bit 6) the search or stop. For applications that have a microcontroller, the preferred approach is to poll the MU_LKD status bit (Register 0x2A, Bit 0) after the typical locking time has expired. This method allows the system controller to check the status of other system parameters (that is, power supplies and clock source) before reattempting the search (by writing 0x03 to Register 0x26). For applications that do not have polling capabilities, the mu controller state machine should be reconfigured to restart the search in hopes that the system’s condition that did not cause locking on the first attempt has disappeared.

Once the mu delay value is found that exactly matches the desired mu phase setting and slope (for example, 6 with a negative. slope), the mu controller goes into track mode. In this mode, the mu controller makes slight adjustments to the delay value to track any variations between the two clock paths due to temperature, time, and supply variations. Two status bits, MU_LKD (Register 0x2A, Bit 0) and MU_LST (Register 0x2A, Bit 1) are available to the user to signal the existing status control loop. If the current phase is more than four steps away from the desired phase, the MU_LKD bit is cleared, and if the lock acquired was previously set, the MU_LST bit is set. Should the phase deviation return to within three steps, the MU_LKD bit is set again while the MU_LST is cleared. Note that this sort of event may occur if the main clock input (that is, DACCLK) is disrupted or the mu controller exceeds the tapped delay line range (that is, <0 or >432).

If lock is lost, the mu controller has the option of remaining in the tracking loop or resetting and starting the search again via the CONTRST bit (Register 0x29, Bit 5). Continued tracking is the preferred state because it is the least disruptive to a system in which the the mu delay and phase value by first setting the read bit high (Register 0x26, Bit 3). Once the read bit is set, the MUDEL[8:0] bits and the SET_PHS[4:0] bits (Register 0x27 and Register 0x28) that the controller is currently using can be read.

AD9739 temporarily loses lock. The user can poll

Rev. B | Page 33 of 48

AD9739 Data Sheet

INTERRUPT REQUESTS

The AD9739 can provide the host processor with an interrupt request output signal (IRQ) that indicates that one or more of the

AD9739 internal controllers have achieved lock or lost lock. These

controllers include the mu, data receiver, and synchronization controllers. The host can then poll the IRQ status register (Register 0x04) to determine which controller has lost lock. The IRQ output signal is an active high output signal available on Pin F13. If used, its output should be connected via a 10 kΩ pull-up resistor to VDD33.

Each IRQ is enabled by setting the enable bits in Register 0x03, which purposely has the same bit mapping as the IRQ status bits in Register 0x04. Note that these IRQ status bits are set only when the controller transitions from a false to true state. Therefore, it is possible for the x_LCK_IRQ and x_LST_IRQ status bits to be set when a controller temporarily loses lock but is able to reestablish lock before the IRQ is serviced by the host. In this case, the host should validate the present status of the suspect controller by reading back its current status bits, which are available in Register 0x21 and/or Register 0x2A. Based on the status of these bits, the host can take appropriate action, if required, to reestablish lock. To clear an IRQ after servicing, it is necessary to reset relevant bits in Register 0x03 by writing 0 followed by another write of 1 to reenable. A detailed diagram of the interrupt circuitry is shown in Figure 51.

(PIN F13)

SPI ISR READ DATA

SPI ADDRESS

INT SOURCE

SPI

DATA

SCLK

INT(n)

INT

SOURCE

IMR

Figure 51. Interrupt Request Circuitry

SPI WRITE

DATA = 1

07851-051

It is also possible to use the IRQ during the AD9739 initialization phase after power-up to determine when the mu and data receiver controllers have achieved lock. For example, before enabling the mu controller, the MU_LCK_EN bit (Register 0x03, Bit 2) can be set and the IRQ output signal monitored to determine when lock has been established before continuing in a similar manner with the data receiver controllers. Note that the relevant LCK bit should be cleared before continuing to the next controller. After all controllers are locked, the lost lock enable bits (that is, x_LST_EN) should be set.

Table 29. Interrupt Request Registers

Address (Hex)

0x03

Bit Description

5 SYNC_LST_EN 4 SYNC_LCK_EN 3 MU_LST_EN 2 MU_LCK_EN 1 RCV_LST_EN 0 RCV_LCK_EN

0x04

5 SYNC_LST_IRQ 4 SYNC_LCK_IRQ 3 MU_LST_IRQ 2 MU_LCK_IRQ 1 RCV_LST_IRQ 0 RCV_LCK_IRQ

0x21

7 SYNC_TRK_ON 5 SYNC_LST 4 SYNC_LCK 3 RCVR_TRK_ON 1 RCVR_LST 0 RCVR_LCK 1 MU_LST 0x2A 0 MU_LKD

Rev. B | Page 34 of 48

Data Sheet AD9739

MULTIPLE DEVICE SYNCHRONIZATION

Synchronization of multiple AD9739s requires all of the devices to have matching pipeline delays. This implies the DAC outputs are time aligned to the same phase when all devices are fed with the same data pattern at the same instance of time. The main contributor to phase ambiguity between devices is from the div-by-4 circuitry that drives the Rx data path and data controller (see Figure 53). This phase ambiguity can result in a ±2 sample offset between any two devices. Because the state of this internal divider is unknown at power-up, a synchronization method that phase aligns the digital paths of multiple AD9739s is required to ensure matching pipeline delays.

Figure 52 shows a top-level diagram of multiple AD9739s synchronized to each other with sample alignment of the different data streams within the FPGA (or among multiple FPGAs) being assumed. A common RF clock source is distributed to each of the AD9739 devices via a dual clock buffer (such as the ADCLK946) with matched PCB trace lengths to each device to ensure matched propagation delays.

MATCHED DELAYS

One AD9739 is designated as the master providing a SYNC_OUT reference clock (equal to f

/4) to itself as well as the other

DAC

AD9739 slave device’s SYNC_IN input. LVDS fanout buffers with

matched output delays are again used to distribute the SYNC_OUT and DCO signals of the master to the slave devices and FPGAs, respectively, thus ensuring tight time alignment. Note, in the case of a single FPGA implementation (that is, I/Q application), the DCO of the master can drive the FPGA directly.

After synchronization, the internal div-by-4 circuitry will have equal phases that drive their respective LVDS controllers. Note, the mu and data receiver controller of both devices must be configured for the same SPI register settings (that is, SET_PHS and DCI_DEL) upon SPI initialization such that controllers converge to similar delays. To validate that delays are roughly matched, the user can read back the delays of both devices (that is, MUDEL and DCI_DEL) to determine if they are in an acceptable window that accounts for slight mismatches between different devices’ delay lines.

FPGA_1

MASTER

DCO

FPGA_2

1:N

LVDS

REPEATER

DCO DACCL K

AD9739

MASTER

DCI

SYNC_IN

DCO DACCL K

AD9739

SLAVE_1

DCI

SYNC_OUT

DCO DACCL K

AD9739

SLAVE_N

DCI

SYNC_OUT

SYNC_IN

DCO

TO FPG A_2

TO OTHER FPG As

TO SLAVE_1

TO SLAVE_N

MATCHED DELAYS

ADCLK346

1:N

LVD S

REPEATER

COMMON

CLOCK SOURCE

0.8GHz T O 2.0GH z

Figure 52. Functional Block Diagram of Two AD9739s Synchronized

Rev. B | Page 35 of 48

07851-052

AD9739 Data Sheet

DB0[13:0]

DB1[13:0]

DCI

SYNC_IN

SYNC_OUT

DB0

EVEN

DB0 ODD

DB1

EVEN

DB1 ODD

DELAY

STATE MACHI NE

TRACKING LOOP

RX DATA CONTROLL ER

SYNCHRONIZ ATION CONTROLLER

PHASE

COMPARISO N

DELAY

STATE MACHI NE

TRACKING LOOP

DELAY

180

270

PHZ MUX

TO DAC

4:1 MUX

DATA ASSMBLER

DISTRIBUT ION

90/270

DAC

DIV-BY-4

0/180

PHASE

ROTATOR

SLAVE ONLY

DAC

Mu Delay

MU DELAY

DAC

DCO

Figure 53. Top Level Block Diagram of Synchronization Circuitry and Controller

Figure 53 shows a top-level diagram of the synchronization controller (bottom) and how it interfaces to other digital functional blocks within the AD9739. Note the following observations of this top level diagram:

• Synchronization between multiple devices is achieved by

rotating the div-by-4 phases of the slave devices such that they align with the master.

• For the slave devices, the sync controller compares the phase

alignment of the master’s SYNC_IN reference signal with the initial 0

/90o outputs of the div-by-4 and then rotates the div-by-4 phase until the SYNC_IN signal falls between these phases.

• A reference signal common to all devices is required for

synchronization. The master device generates this signal by providing a SYNC_OUT signal which is then distributed to all the devices (including itself with tight time alignment) as a SYNC_IN signal.

• Because the SYNC_IN signal has a defined relationship

between the div-by-4 phase of the master, the slave devices can now align their respective div-by-4 phases to the SYNC_IN phase thus ensuring phase alignment among all devices.

DIV-BY-4

07851-053

• It is not possible to manually rotate the div-by-4 phases of

the data path with the sync controller enabled. This can be a problem at lower clock rates were one may desire to rotate the div-by-4 phase to ensure locking of the data receiver controller and/or achieve a more optimum DCI_DEL value.

• The DCO output signal is generated from a separate div-

by-4 circuit, and therefore, has a random phase upon each startup. For this reason, the DCO of the master should be distributed to all the FPGAs.

SYNC Controller Initialization Description

The sync controller of the master is enabled by writing 0x70 to Register 0x10. Once enabled, a state machine automatically adjusts the output delay of its SYNC_OUT signal such that the fed back reference SYNC_IN signal is centered between the 0° and 90° output phases associated with its div-by-4 circuit. Note that the coarse delay is performed by shifting phases via PHZ MUX while the fine delay that centers (and tracks) variation is done by a variable delay line. The variable delay line tap size is 12 ps. Once SYNC_IN is centered, the controller enters tracking mode such that SYNC_IN remains centered despite possible system variations in temperature and/or supply. Centering the SYNC_IN signal on the master device ensures that the SYNC_IN signals of the slave

Rev. B | Page 36 of 48

Data Sheet AD9739

devices also remain centered between their respective div-by-4 phases; therefore, providing the greatest margin to absorb nonideal timing skews. The following status bits are available in Register 0x21 indicating lock, lost-lock, and tracking: SYNC_LCK, SYNC_LST and SYNC_TRK_ON.

The sync controller of the slave is enabled by writing 0x50 to Register 0x10. Once enabled, the state machine compares the reference SYNC_IN signal to the 0°/90° phase outputs of the div-by-4 phase settings. If the SYNC_IN signal does not fall between these phases, the state machine of the slave rotates the divby-4 phase setting until it does. To validate that phase alignment has been achieved, the SYNC_IN_PH90 and SYNC_IN_PH0 status bits should read 1 and 0, respectively (that is, Register 0x0D, Bits[5:4]). Note that the DCO and SYNC_OUT outputs of the slave can be disabled via Register 0x01, Bit 5.

Synchronization Limitations

Ensuring consistent synchronization over production lots in systems containing two or more AD9739s becomes increasingly more challenging at the higher update rates because the timing offset between adjacent phases of the div-by-4 output clock is equal to 1/f

. For example, a DAC update of 2 GSPS corresponds

DAC

to a 500 ps period. If the SYNC_IN signal of an ideal master device is positioned in the center of its div-by-4 0

and 90o phase outputs, only ±250 ps of timing margin exists for the slave devices. This ideal margin is actually reduced by quadrature phase errors in the div-by-4 circuit of the master as well as its ability to position the SYNC_IN exactly in the center of the 0° and 90° output phases.

The timing margin is further eroded by the following sources:

• Master-to-slave device(s) mismatch in the propagation delays

in the mu delay clock path and SYNC_IN. Note that these mismatches can be up to 100 ps between devices that are at opposite extremes of the process corners.

• Quadrature phase errors in the div-by-4 outputs of the slave.

These sources of timing skews become more significant as the DACCLK period is decreased (that is, clock rate is increased), leaving less margin for timing skews external to the master-toslave device(s). Special consideration to PCB layout and selection of clock distribution ICs are required to ensure minimum skew between the distributed DACCLK and SYNC_IN signals. Note that timing skews can quickly accumulate considering that the propagation delay on an FR4 PCB is on the order of 170 ps/inch, and that output-to-output skews on each clock distribution IC can be as high as 25 ps.

The problem becomes more pronounced in multiboard synchronization where clock signals (that is, DACCLK, SYNC_OUT, and DCO) are distributed over a back plane to multiple PCBs. Data alignment among the various data sources is required when driven by phase aligned DCO signals that are a buffered version of the master’s DCO. However, these data sources (FPGAs) also have process, supply voltage, and temperature sensitivities (PVTs) that can cause misalignment among their respective DCI outputs.

Adding to this dilemma is that it also possible for the data receiver controller of different AD9739s to converge on different delay settings due to PVT variations of the delay line (even if DCI inputs are exactly aligned). This can result in a four sample pipeline mismatch between devices if the difference in absolute delays exceeds a period of 4/f

. Recall that the controller searches

DAC

up/down for its first valid edge from its initial start value (that is, DCI_DEL and SMP_DEL). While the initial start values between devices should be made the same, different absolute time delays due to PVT can cause devices to converge on different edges of DCI above or below this initial start value. As a result, confirm that DCI_DEL values between multiple devices are matched sufficiently such that the absolute differences between the readback DCI_DEL values do not exceed a data period (that is, 4/f

). If the difference exceeds a data period, modify the

DAC

DCI_DEL (and SMP_DEL) setting of the slave device so that its start point is roughly ½ the difference between the master and slave readback values.

Rev. B | Page 37 of 48

AD9739 Data Sheet

ANALOG INTERFACE CONSIDERATIONS

ANALOG MODES OF OPERATION

The AD9739 uses the quad-switch architecture shown in Figure 54. The quad-switch architecture masks the code-dependent glitches that occur in a conventional two-switch DAC. Figure 55 compares the waveforms for a conventional DAC and the quad-switch DAC. In the two-switch architecture, a code-dependent glitch occurs each time the DAC switches to a different state (that is, D1 to D2). This code-dependent glitching causes an increased amount of distortion in the DAC. In a quad-switch architecture (no matter what the codes are), there are always two switches transitioning at each half clock cycle, thus eliminating the codedependent glitches. However, a constant glitch occurs at 2 × DACCLK because half of the internal switches change state on the rising DACCLK edge, while the other half change state on the falling DACCLK edge.

DACCLK_x

DBx[13:0]

DACCLK_x

TWO-SWITCH DAC OUTPUT

FOUR-SW ITCH

DAC OUTPUT

(NORMAL MODE)

Another attribute of the quad-switch architecture is that it also enables the DAC core to operate in one of the following three modes: normal mode, mix mode, and return-to-zero (RZ) mode. The mode is selected via SPI Register 0x08, Bits[1:0] with normal mode being the default value. In the mix mode, the output is effectively chopped at the DAC sample rate. This has the effect of reducing the power of the fundamental signal while increasing the power of the images centered around the DAC sample rate, thus improving the output power of these images. The RZ mode is similar to the analog mix mode, except that the intermediate data samples are replaced with midscale values.

CLK

VG1

1G4VG3VG2

LATCHES

IOUTP

IOUTN

Figure 54. AD9739 Quad-Switch Architecture

INPU

D1D2D3D4D

DATA

D1D2D3D4D

D6D7D8D9D

Figure 55. Two-Switch and Quad-Switch DAC Waveforms

07851-054

INPUT

DATA

DACCLK_x

FOUR-SW ITCH

DAC OUTPUT

(

MIX MODE)

FOUR-SW ITCH

DAC OUTPUT

(RETURN TO

ZERO MO DE)

D1D2D3D4D

–D

D1D2D3D4D

D6D7D8D9D

–D

D6D7D8D9D

–D

07851-056

Figure 56. Mix-Mode and RZ DAC Waveforms

Figure 56 shows the DAC waveforms for both the mix mode and the RZ mode. Note that the disadvantage of the RZ mode is the 6 dB loss of power to the load because the DAC is only functioning for ½ the DAC update period. This ability to change modes provides the user the flexibility to place a carrier anywhere in the first three Nyquist zones, depending on the operating mode selected. Switching between the analog modes reshapes the sinc roll-off inherent at the DAC output. The maximum amplitude in all three Nyquist zones is impacted by this sinc roll-off, depending on where the carrier is placed (see Figure 57). As a practical matter, the usable bandwidth in the third Nyquist zone becomes limited at higher DAC clock rates (that is, >2 GSPS) when the output bandwidth of DAC core and the interface network (that is, balun) contributes to additional roll-off.

FIRST

NYQUIST ZONE

–5

RZ MODE

–10

–15

07851-055

dBFS

–20

–25

–30

–35

0FS 1.50FS1.25FS1.00FS0.75FS0.50FS0.25FS

Figure 57. Sinc Roll-Off for Each Analog Operating Mode

SECOND

NYQUIST ZONE

MIX MODE

FREQUENCY (Hz)

NORMAL

MODE

THIRD

NYQUIST ZONE

07851-057

Rev. B | Page 38 of 48

Data Sheet AD9739

CLOCK INPUT CONSIDERATIONS

The quality of the clock source and its drive strength are important considerations in maintaining the specified ac performance. The phase noise and spur characteristics of the clock source should be selected to meet the target application requirements. Phase noise and spurs at a given frequency offset on the clock source are directly translated to the output signal. It can be shown that the phase noise characteristics of a reconstructed output sine wave are related to the clock source by 20 × log10 (f thermal and quantization effects, are negligible.

The AD9739 clock receiver provides optimum jitter performance when driven by a fast slew rate originating from the LVPECL or CML output drivers. For a low jitter sinusoidal clock source, the

ADCLK914 can be used to square-up the signal and provide a

CML input signal for the AD9739 clock receiver. Note that all specifications and characterization presented in the data sheet are with the ADCLK914 driven by a high quality RF signal generator with the clock receiver biased at a 800 mV level. A dc blocking capacitor is used between the clock driver output and clock receiver input to allow for different dc bias levels. To minimize signal loss for high clock rates, a high quality, dc blocking RF capacitor is recommended.

Figure 60 shows a clock source based on the ADF4350 low phase noise/jitter PLL. The ADF4350 can provide output frequencies from 140 MHz up to 4.4 GHz with jitter as low as 0.5 ps rms.

) when the DAC clock path contribution, along with

OUT/fCLK

Each single-ended output can provide a squared-up output level that can be varied from −4 dBm to +5 dBm allowing for >2 V p-p output differential swings. The ADF4350 also includes an additional CML buffer that can be used to drive another

AD9739 device.

4-BIT PM OS

IOUT ARRAY

CLKx_OFF SET

DACCLK_P DACCLK_N

ESD

DIR_x = 0

CLKx_OFF SET

DIR_x = 0

4-BIT NMOS

IOUT ARRAY

Figure 58. Clock Input and Common-Mode Control

VDDC

VSSC

07851-060

The AD9739 clock receiver features the ability to independently adjust the common-mode level of its inputs over a span of ±100 mV centered about its midsupply point (that is, VDDC/2) as well as an offset for hysteresis purposes. Figure 58 shows the equivalent input circuit of one of the inputs. ESD diodes are not shown for clarity purposes. It has been found through characterization that the optimum setting is for both inputs to be biased at approximately 0.8 V. This can be achieved by writing a 0x0F (corresponding to a −15) setting to both cross controller registers (that is, Register 0x22 and Register 0x23).

ADCLK914

50Ω 50Ω

1nF

100Ω

1nF

AD9739

DACCLK_P

DACCLK_N

07851-058

50Ω

10nF

REF

50Ω 50Ω

Figure 59. ADCLK914 Interface to the AD9739 CLK Input

AD9739

DACCLK_P

DACCLK_N

07851-059

FREF

ADF4350

PLL

VCO

DIV-BY-2

N = 0 – 4

VCO

OUT

Figure 60. ADF4350 Interface to the AD9739 CLK Input

3.9nH

1.8V p-p

1nF

100Ω

A+

A–

A+

A–

Rev. B | Page 39 of 48

AD9739 Data Sheet

1.10

1.05

1.00

0.95

0.90

0.85

COMMON-MODE (V)

0.80

0.75

0.70 –15 –13 –11 –9 –7 –5 –3 –1 1 3 5 7 9 11 13 15

OFFSET CODE

CLKP CLKN

07851-061

Figure 61. Common-Mode Voltage with Respect to

CLKP_OFFSET/CLKN_OFFSET and DIR_P/DIR_N

VOLTAGE REFERENCE

The AD9739 output current is set by a combination of digital control bits and the I120 reference current, as shown in Figure 62.

AD9739

1.2V

1nF

VREF

I120

10kΩ

AGND

–

I120

Figure 62. Voltage Reference Circuit

The reference current is obtained by forcing the band gap voltage across an external 10 kΩ resistor from I120 (Pin B14) to ground. The 1.2 V nominal band gap voltage (VREF) generates a 120 µA reference current in the 10 kΩ resistor. Note the following constraints when configuring the voltage reference circuit:

• Both the 10 kΩ resistor and 1 nF bypass capacitor are required

for proper operation.

• Adjusting the output full-scale current, I

from its default setting of 20 mA should be performed digitally.

• The AD9739 is not a multiplying DAC. Modulating the

reference current, I120, with an ac signal is not supported.

• The band gap voltage appearing at VREF (Pin C14) must

be buffered for use with external circuitry because its output impedance is approximately 5 kΩ.

• An external reference can be used to overdrive the internal

reference by connecting it to VREF (Pin C14).

can be adjusted digitally over 8.7 mA to 31.7 mA by using

OUTFS

FSC[9:0] (Register 0x06 and Register 0x07).

FSC[9:0]

CURRENT

SCALING

DAC

IFULL -SCALE

, of the DAC

OUTFS

07851-062

The following equation relates I

to the FSC[9:0] register,

OUTFS

which can be set from 0 to 1023:

= 22.6 × FSC[9:0]/1000 + 8.7 (1)

OUTFS

Note that a default value of 0x200 generates 20 mA full scale, which is used for most of the characterization presented in this data sheet (unless noted otherwise).

ANALOG OUTPUTS

Equivalent DAC Output and Transfer Function

The AD9739 provides complementary current outputs, IOUTP and IOUTN, that source current into an external ground reference load. Figure 63 shows an equivalent output circuit for the DAC. Note that, compared to most current output DACs of this type, the AD9739 outputs exhibit a slight offset current (that is, I

/16), and the peak differential ac current is slightly below

OUTFS

/2 (that is, 15/32 × I

OUTFS

PEAK

15/32 × I

Figure 63. Equivalent DAC Output Circuit

As shown in Figure 63, the DAC output can be modeled as a pair of dc current sources that source a current of 17/32 × I output. A differential ac current source, I the signal-dependent nature of the DAC output. The polarity and signal dependency of this ac current source are related to the digital code by the following equations:

F(Code) = (DACCODE − 8192)/8192 (2)

−1 ≤ F(Code) < 1 (3)

where DACCODE = 0 to 16,383 (decimal).

Because I

can swing ±(15/32) × I

PEAK

measured at IOUTP and IOUTN can span from I I

. However, because the ac signal-dependent current

OUTFS

component is complementary, the sum of the two outputs is always constant (that is, IOUTP + IOUTN = (34/32) × I

The code-dependent current measured at the IOUTP (and IOUTN) output is as follows:

IOUTP = 17/32 × I

IOUTN = 17/32 × I

OUTFS

= 8.6 – 31.2mA

17/32 × I

OUTFS

17/32 × I

OUTFS

70Ω

OUTFS

+ 15/32 × I

− 15/32 × I

2.2pF

07851-063

to each

OUTFS

is used to model

PEAK,

, the output currents

/16 to

OUTFS

× F(Code) (4)

OUTFS

× F(Code) (5)

OUTFS

Rev. B | Page 40 of 48

Data Sheet AD9739

Figure 64 shows the IOUTP vs. DACCODE transfer function when I

is set to 19.65 mA.

OUTFS

OUTPUT CURRENT (mA)

0 4096 8192 12,288

DAC CODE

Figure 64. Gain Curve for FSC[9:0] = 512, DAC Offset = 1.228 mA

16,384

07851-064

Peak DAC Output Power Capability

The maximum peak power capability of a differential current output DAC is dependent on its peak differential ac current, I

PEAK

, and the equivalent load resistance it sees. Because the AD9739 includes a differential 70  resistance, it is best to use a doubly terminated external output network similar to what is shown in Figure 65. In this case, the equivalent load seen by the ac current source of the DAC is 25 .

= 8.6 – 31.2mA

OUTFS

If the AD9739 is programmed for I current is 9.375 mA and its peak power delivered to the equivalent load is 2.2 mW (that is, P = I

R). Because the source and load resistance seen by the 1:1 balun are equal, this power is shared equally; therefore, the output load receives 1.1 mW or 0.4 dBm.

To calculate the rms power delivered to the load, the following must be considered:

• Peak-to-rms of the digital waveform

• Any digital backoff from digital full scale

• The DAC’s sinc response and nonideal losses in external

network

For example, a reconstructed sine wave with no digital backoff ideally measures −2.6 dBm because it has a peak-to-rms ratio of 3 dB. If a typical balun loss of 0.4 dBm is included, −3 dBm of actual power can be expected in the region where the sinc response of the DAC has negligible influence. Increasing the output power is best accomplished by increasing I linearity performance must be considered acceptable for the target application.

SOURCE

= 50Ω

= 20 mA, its peak ac

OUTFS

, although any degradation in

OUTFS

LOSSLESS

BALUN

1:1

15/32 × I

PEAK

OUTFS

70Ω

180Ω

Figure 65. Equivalent Circuit for Determining Maximum Peak Power to a 50 Ω Load

LOAD

= 50Ω

07851-065

Rev. B | Page 41 of 48

AD9739 Data Sheet

Output Stage Configuration

The AD9739 is intended to serve high dynamic range applications that require wide signal reconstruction bandwidth (that is, DOCSIS CMTS) and/or high IF/RF signal generation. Optimum ac performance can only be realized if the DAC output is configured for differential (that is, balanced) operation with its output common-mode voltage biased to analog ground. The output network used to interface to the DAC should provide a near 0  dc bias path to analog ground. Any imbalance in the output impedance between the IOUTP and IOUTN pins results in asymmetrical signal swings that degrade the distortion performance (mostly even order) and noise performance. Component selection and layout are critical in realizing the performance potential of the AD9739.

MINI-CIRCUITS

IOUTP

90Ω

70Ω

IOUTN

90Ω

TC1-33-75G+

Figure 66. Recommended Balun for Wideband Applications with Upper

Bandwidths of up to 2.2 GHz

07851-066

Most applications requiring balanced-to-unbalanced conversion can take advantage of the Ruthroff 1:1 balun configuration shown in Figure 66. This configuration provides excellent amplitude/phase balance over a wide frequency range while providing a 0  dc bias path to each DAC output. Also, its design provides exceptional bandwidth and can be considered for applications requiring signal reconstruction of up to 2.2 GHz. The characterization plots shown in this data sheet are based on the AD9739 evaluation board, which uses this configuration. Figure 67 compares the measured frequency response for normal and mix mode using the AD9739 evaluation board vs. the ideal frequency response.

–3

BASEBAND TC1-33-75G

–6

–9

–12

–15

–18

–21

POWER (d Bc)

–24

–27

–30

–33

–36

0 500 1000 1500 2000 2500 3000 3500

Figure 67. Measured vs. Ideal Frequency Response for Normal (Baseband)

and Mix Mode Operation Using a TC1-33-75G Transformer on the AD9739

IDEAL BASEBAND MODE

IDEAL MIX MODE

FREQUENC Y (MHz)

Evaluation Board

MIX MODE

TC1-33-75G

07851-067

Figure 68 shows an interface that can be considered when interfacing the DAC output to a self-biased differential gain block. The inductors shown serve as RF chokes (L) that provide the dc bias path to analog ground. The value of the inductor, along with the dc blocking capacitors (C), determines the lower cutoff frequency of the composite pass-band response. An RF balun should also be considered before the RF differential gain stage and any filtering to ensure symmetrical common-mode impedance seen by the DAC output while suppressing any common-mode noise, harmonics, and clock spurs prior to amplification.

IOUTP

90Ω

70Ω

90Ω

IOUTN

Figure 68. Interfacing the DAC Output to the Self-Biased Differential Gain Stage

OPTIO NAL BALUN AND FI LTER

LPF

RF DIFF

AMP

For applications operating the AD9739 in mix mode with output frequencies extending beyond 2.2 GHz, the circuits shown in Figure 69 should be considered. The circuit in Figure 69 uses a wideband balun with a configuration similar to the one shown in Figure 68 to provide a dc bias path for the DAC outputs. The circuit in Figure 70 takes advantage of ceramic chip baluns to provide a dc bias path for the DAC outputs while providing excellent amplitude/phase balance over a narrower RF band. These low cost, low insertion loss baluns are available for different popular RF bands and provide excellent amplitude/ phase balance over their specified frequency range.

MINI-CIRCUITS

IOUTP

IOUTN

70Ω

90Ω

TC1-1-462M

07851-069

Figure 69. Recommended Mix Mode Configuration Offering Extended RF

Bandwidth Using a TC1-1-43A+ Balun

MURATA

JOHANSON TECHNOLOGY

IOUTP

IOUTN

70Ω

180Ω

CHIP BALU NS

07851-070

Figure 70. Lowest Cost and Size Configuration for Narrow RF Band Operation

07851-068

Rev. B | Page 42 of 48

Data Sheet AD9739

NONIDEAL SPECTRAL ARTIFACTS

The AD9739 output spectrum contains spectral artifacts that are not part of the original digital input waveform. These nonideal artifacts included harmonics (including alias harmonics), images, and clock spurs. Figure 71 shows a spectral plot of the

AD9739 within the first Nyquist zone (that is, dc to f

reconstructing a 650 MHz, 0 dBFS sine wave at 2.4 GSPS. Besides the desired fundamental tone at the −7.8 dBm level, the spectrum also reveals these nonideal artifacts that also appear as spurs above the measurement noise floor. Because these nonideal artifacts are also evident in the second and third Nyquist zones during mix mode operation, the effects of these artifacts should also be considered when selecting the DAC clock rate for a target RF band.

–10

–20

–30

–40

–50

/4 –

DAC

–60

POWER ( dBc)

–100

OUT

–70

–80

–90

HD4

0 200 400 600 800 1000 1 200

FUND AT –7.6dBm

/2 –

DAC

OUT

HD3

FREQUENCY (MHz)

Figure 71. Spectral Plot

3/4 ×

HD5

HD6

Note the following important observations pertaining to these nonideal spectral artifacts:

1. A full-scale sine wave (that is, single-tone) typically represents

the worst-case condition because it has a peak-to-rms ratio of 3 dB and is unmodulated. Harmonics and aliased harmonics of a sine wave are easy to identify because they also appear as discrete spurs. Significant characterization of a high speed DAC is performed using single (or multitone) signals for this reason.

2. Modulated signals (that is, AM, PM, or FM) do not appear as

spurs but rather as signals whose power spectral density is spread over a defined bandwidth determined by the modulation parameters of the signals. Any harmonics from the DAC spread over a wider bandwidth determined by the order of the harmonic and bandwidth of the modulated signal. For this reason, harmonics often appear as slight bumps in the measurement noise floor and can be difficult to discern.

OUT

HD9

DAC

HD2

DAC

/4 –

/2)

07851-071

3. Images appear as replicas of the original signal, therefore,

can be easier to identify. In the case of the AD9739, internal modulation of the sampling clock at intervals related to f

/4 generate image pairs at ¼ × f

DAC

, ½ × f

, and ¾ × f

DAC

Both upper and lower sideband images associated with ¼ × f

fall within the first Nyquist zone, while only the lower

DAC

image of ½ × f

and ¾ × f

DAC

fall back. Note that the lower

DAC

images appear frequency inverted. The difference in dBc between the fundamental and various images remains mostly signal independent because the mechanism causing these images is related to corruption of the sampling clock.

4. The magnitude of these images for a given device is dependent

on several factors including DAC clock rate, output frequency, mu controller phase setting, and div-by-4 clock divider phase (Register 0x14, bit [7:6]. Tab le 3 0 shows how the magnitude of these images vary as the phase is varied for the case represented in Figure 71. Because the phase varies at power up, the image magnitude varies making it difficult to compensate digitally through a one-time factory calibration procedure. Also, the image magnitude can vary a few decibels over temperature and between devices due to process dependencies. (Note that the AD9739A is a viable option if factory calibration is considered acceptable for nonmultichip synchronization applications operating with clock rates in the 1.6 GSPS to 2.5 GSPS range).

Table 30. Image Magnitude vs. Phase (PHZ) Setting

Image location PHZ0 PHZ1 PHZ2 PHZ3

/4 − f

DAC

/2 − f

DAC

¾ × f

5. A clock spur appears at f

−70.2 −71.4 −72.2 −77.1

OUT

−80.2 −71.3 −69.9 −74.9

OUT

− f

DAC

−69.9 −72.5 −73.4 −73.7

OUT

/4 and integer multiples of this

DAC

frequency. Similar to images, the spur magnitude is also dependent on the same factors that cause variations in image levels. However, unlike images and harmonics, clock spurs always appear as discrete spurs, albeit their magnitude shows a slight dependency on the digital waveform and output frequency. Note that the clock spur appearing at f

DAC

can also be factory calibrated.

6. A large clock spur also appears at 2 × f

in either normal

DAC

or mix mode operation. This clock spur is due to the quad switch DAC architecture causing switching events to occur on both edges of f

DAC

Rev. B | Page 43 of 48

AD9739 Data Sheet

LAB EVALUATION OF THE AD9739

Figure 72 shows a recommended lab setup that was used to characterize the performance of the AD9739. The DPG2 is a dual port LVDS/CMOS data pattern generator available from Analog Devices, Inc., with an up to 1.25 GSPS data rate. The DPG2 directly interfaces to the AD9739 evaluation board via Tyco Z-PACK HM-Zd connectors. A low phase noise/jitter RF source, such as an R&S SMA100A signal generator, is used for the DAC clock. A 5 V power supply is used to power up the

AD9739 evaluation board, and SMA cabling is used to interface

to the supply, clock source, and spectrum analyzer. A USB 2.0 interface to a host PC is used to communicate to both the AD9739 evaluation board and the DPG2.

A high dynamic range spectrum analyzer is required to evaluate the AD9739 reconstructed waveform’s ac performance. This is especially the case when measuring ACLR performance for high dynamic range applications, such as multicarrier DOCSIS CMTS applications. Harmonic, SFDR, and IMD measurements pertaining to unmodulated carriers can benefit by using a sufficiently high RF attenuation setting because these artifacts are easy to identify above the spectrum analyzer noise floor. However, reconstructed waveforms having modulated carrier(s) often benefit from the use of a high dynamic range RF amplifier and/or passive filters to measure close-in and wideband ACLR performance when using spectrum analyzers of limited dynamic range.

RHODE AND

SCHWARTZ

SMA 100A

10 MHz REFIN

ADI PATTERN G ENERATOR

DCO

1.6GHz TO

2.5GHz 3dBm

DPG2

LVDS

DATA

AND DCI

AD9739

EVAL. BOARD

10 MHz REOUT

Figure 72. Lab Test Setup Used to Characterize the AD9739

USB 2.0

POWER

SUPPLY

+5V

LAB

AGILENT PSA

E4440A

GPIB

07851-072

POWER DISSIPATION AND SUPPLY DOMAINS

The power dissipation of the AD9739 is dependent on the DAC clock rate as shown in Figure 73 and Figure 74. The current consumption from the 3.3 V supply remains relatively constant because it is used for biasing the DAC core (that is, VDDA) and differential input receivers (that is, VDD33). However, the current consumption from the 1.8 V supply is clock rate dependent and increases linearly with frequency because this supply is used by the digital path (that is, VDD) as well as the clock distribution circuitry (that is, VDDC).

Treat the VDDC supply as an analog supply because the clock distribution circuitry has poor power supply rejection; therefore, noise on this supply can induce clock jitter. To ensure low noise on this sensitive supply, use a separate 1.8 V regulator powered from the 3.3 V analog supply rail that is also used to power VDDA. This supply rail can also be used to power-up VDD33 via an LC filter network. The digital 1.8 V supply, VDD, can be supplied via a well-filtered switching regulator.

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

POWER (W)

0.4

0.3

0.2

0.1

0 250 500 750 1000 1250 1500 1750 2000 2250 2500

DAC

Figure 73. Power Consumption vs. f

360

330

300

270

240

210

180

150

CURRENT (mA)

120

0 250 500 750 1000 1250 1500 1750 2000 2250 2500

DAC

Figure 74. Current Consumption vs. f

(MHz)

I_VDD

I_VDDA

I_VDD33

(MHz)

TOTAL

VDD

VDDA

VDD33

DAC

I_VDDC

DAC

VDDC

@ 25°C

07851-073

07851-074

Rev. B | Page 44 of 48

Data Sheet AD9739

RECOMMENDED START-UP SEQUENCE

Upon power-up of the AD9739, a host processor is required to initialize and configure the AD9739 via its SPI port. Figure 75 shows a flowchart of the sequential steps required, while Tab le 3 1 and Tabl e 32 provides more detail on the SPI register write/read operations required to implement the flowchart steps. Note the following:

• A software reset is optional because the AD9739 has both

an internal POR circuit and a RESET pin.

• The SYNC controller is optional because it is only required

to synchronize two or more devices. If synchronization is required, validate that DCI_DEL values between devices are sufficiently matched.

• The mu controller must be first enabled (and in track mode)

before the data receiver controller is enabled because the DCO output signal is derived from this circuitry.

• A wait period is related to f

DATA

periods.

• Limit the number of attempts to lock the controllers to

three; locks typically occur on the first attempt.

• Hardware or software interrupts can be used to monitor

the status of the controllers.

CONFIGURE

SPI PORT

SOFTWARE

RESET

SET CLK

INPUT CMV

CONFIGURE

MU CONT.

WAIT A

FEW 100µs

MU CONT. LOCKED?

YES YES YES

CONFIGURE

SYNC

CONT.

WAIT A

FEW 100µs

SYNC CONT.

VAL ID?

CONFIGURE

Rx DATA

CONT.

WAIT A

FEW 100µs

DATA CONT.

LOCKED?

COMPARE

DCI_DEL

VALU ES

RECONFIG URE

TxDAC FROM

DEFAULT SETTING

OPTIONAL

SYNC. ONLY

07851-075

Figure 75. Flowchart for Initialization and Configuration of the AD9739

Rev. B | Page 45 of 48

AD9739 Data Sheet

Table 31. Recommended SPI Initialization with SYNC Controller Disabled

Step Address (Hex) Write Value Comments

1 0x00 0x00

2 0x00 0x20 Software reset to default SPI values. 3 0x00 0x00 Clear the reset bit. 4 0x22 0x0F 5 0x23 0x0F 6 0x24 0x30 7 0x25 0x80 8 0x27 0x44 9 0x28 0x6C 10 0x29 0xCB 11 0x26 0x02 12 0x26 0x03 Enable the mu controller search and track mode. 13 Not applicable Not applicable Wait for 160 K × 1/f 14 0x2A

15 Not applicable Not applicable Ensure that the AD9739 is fed with DCI clock input from the data source. 16 0x13 0x72 Set FINE_DEL_SKEW to 2. 17 0x10 0x00 Disable the data Rx controller before enabling it. 18 0x10 0x02 Enable the data Rx controller for loop and IRQ. 19 0x10 0x03 Enable the data Rx controller for search and track mode. 20 Not applicable Not applicable Wait for 135 K × 1/f 21 0x21

22 0x06, 0x07 0x00, 0x02 Optional: modify the TxDAC I 23 0x08 0x00 Optional: modify the TxDAC operation mode (the default is normal mode).

Configure for the 4-wire SPI mode with MSB. Note that Bits[7:5] must be mirrored onto Bits[2:0] because the MSB/LSB format can be unknown at power-up.

Set the common-mode voltage of DACCLK_P and DACCLK_N inputs.

Configure the mu controller. Refer to Ta ble 28 for recommended target mu slope and phase settings vs. clock rate.

cycles.

DATA

Read back Register 0x2A and confirm that it is equal to 0x01 to ensure that the DLL loop is locked. If it is not locked, proceed to Step 10 and repeat. Limit attempts to three before breaking out of the loop and reporting a mu lock failure.

cycles.

DATA

Read back Register 0x21 and confirm that it is equal to 0x09 to ensure that the DLL loop is locked and tracking. If it is not locked and tracking, advance the CLKDIVPH[1:0] phase in Register 0x14, Bit[7:6] before proceeding to Step 17 to repeat attempt. Limit attempts to three before breaking out of the loop and reporting an Rx data lock failure.

setting (the default is 20 mA).

OUTFS

Rev. B | Page 46 of 48

Data Sheet AD9739

Table 32. Recommended SPI Initialization with SYNC Controller Enabled

Step Address (Hex) Write Value Comments

1 0x00 0x00

15 0x15 0x42 Configure sync controller. 16 0x10 0x00 Disable sync controller before enabling it. 17 0x10 0x60 or 0x40 Enable sync controller for loop and IRQ. 0x60 = master mode. 0x40 = slave mode. 18 0x10 0x70 or 0x50 Enable sync controller: 0x70 = master mode. 0x50 = slave mode. 19 Not applicable Not applicable Wait for 160 K × 1/f 20 0x21 Read back Register 0x21 to confirm proper operation: 0x90 = master mode. 0x00 = slave mode.

21 0x0D

22 Not applicable Not applicable Ensure that the AD9739 is fed with DCI clock input from the data source. 23 0x13 0x72 Set FINE_DEL_SKEW to 2. 24 0x10 0x00 Disable the data Rx controller before enabling it. 25 0x10 0x02 Enable the data Rx controller for loop and IRQ. 26 0x10 0x03 Enable the data Rx controller for search and track mode. 27 Wait for 135 K × 1/f 28 0x21

29 Not applicable Not applicable

30 0x06, 0x07 0x00, 0x02 Optional: modify the TxDAC I 31 0x08 0x00 Optional: modify the TxDAC operation mode (the default is normal mode).

Configure for the 4-wire SPI mode with MSB. Note that Bits[7:5] must be mirrored onto Bits[2:0] because the MSB/LSB format can be unknown at power-up.

Set the common-mode voltage of DACCLK_P and DACCLK_N inputs.

Configure the mu controller. Refer to Ta ble 28 for recommended target Mu slope and phase settings vs. clock rate.

cycles.

DATA

for DLL to lock.

DATA

If not, proceed to Step 15 and repeat. Limit to three attempts before breaking out of loop and reporting sync lock failure.

Read back Register 0x0D and confirm Bits[5:4] = 10. If not, proceed to Step 2 and repeat. Limit to three attempts before breaking out of loop and reporting sync lock failure.

cycles.

DATA

Read back Register 0x21 and confirm that it is equal to 0x09 to ensure that the DLL loop is locked and tracking. If it is not locked and tracking, proceed to Step 16 and repeat. Limit attempts to three before breaking out of the loop and reporting an Rx data lock failure.

Readback DCI_DEL value in Register 0x13 and Register 0x14 for master and. If slave devices are not within 40 codes of each other, re-specify target DCI_DEL value to be average between master and readback DCI_DEL value.

setting (the default is 20 mA).

OUTFS

Rev. B | Page 47 of 48

AD9739 Data Sheet

OUTLINE DIMENSIONS

12.10

A1 BALL CORNER

12.00 SQ

11.90

TOP VIEW

10.40

BSC SQ

0.80 BSC

141312

BOTTOM VIEW

10 876

3219

A B C D E F G H J K L M N P

A1 BALL CORNER

1.00 MAX

0.85 MIN

COPLANARIT Y

0.12

11-18 -2011- A

1.40 MAX

DETAIL A

COMPLI ANT WIT H JEDEC STANDARDS MO-275-GG AA-1.

0.43 MAX

0.25 MIN

SEATING

PLANE

DETAIL A

0.55

0.50

0.45

BALL DIAME TER

Figure 76. 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-160-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

AD9739BBCZ −40°C to +85°C 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-160-1 AD9739BBCZRL −40°C to +85°C 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-160-1 AD9739BBC −40°C to +85°C 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-160-1 AD9739BBCRL AD9739-R2-EBZ Evaluation Board

Z = RoHS Compliant Part.

−40°C to +85°C 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-160-1

Rev. B | Page 48 of 48

Datasheet AD9739 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

DC SPECIFICATIONS

LVDS DIGITAL SPECIFICATIONS

SERIAL PORT SPECIFICATIONS

AC SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

AC (NORMAL MODE)

AC (MIX MODE)

TERMINOLOGY

SERIAL PORT INTERFACE (SPI) REGISTER

SPI REGISTER MAP DESCRIPTION

Reset

SPI OPERATION

Instruction Header Information

SPI REGISTER MAP

SPI PORT CONFIGURATION AND SOFTWARE RESET

POWER-DOWN LVDS INTERFACE AND TXDAC®

CONTROLLER CLOCK DISABLE

INTERRUPT REQUEST (IRQ) ENABLE/STATUS

TxDAC QUAD-SWITCH MODE OF OPERATION

DCI PHASE ALIGNMENT STATUS

SYNC_IN PHASE ALIGNMENT STATUS

DATA RECEIVER CONTROLLER CONFIGURATION

DATA RECEIVER CONTROLLER_DATA SAMPLE DELAY VALUE

DATA AND SYNC RECEIVER CONTROLLER_DCI DELAY VALUE/WINDOW AND PHASE ROTATION

DATA RECEIVER CONTROLLER_DELAY LINE STATUS AND SYNC CONTROLLER SYNC_OUT STATUS

SYNC AND DATA RECEIVER CONTROLLER LOCK/TRACKING STATUS

CLK INPUT COMMON MODE

MU CONTROLLER CONFIGURATION AND STATUS

PART ID

THEORY OF OPERATION

LVDS DATA PORT INTERFACE

Data Receiver Controller Initialization Description

Data Receiver Operation at Lower Clock Rates

LVDS Driver and Receiver Input

MU CONTROLLER

Mu Controller Initialization Description

INTERRUPT REQUESTS

MULTIPLE DEVICE SYNCHRONIZATION

SYNC Controller Initialization Description

Synchronization Limitations

ANALOG INTERFACE CONSIDERATIONS

ANALOG MODES OF OPERATION

CLOCK INPUT CONSIDERATIONS

VOLTAGE REFERENCE

ANALOG OUTPUTS

Equivalent DAC Output and Transfer Function

Peak DAC Output Power Capability

Output Stage Configuration

NONIDEAL SPECTRAL ARTIFACTS

LAB EVALUATION OF THE AD9739

POWER DISSIPATION AND SUPPLY DOMAINS

RECOMMENDED START-UP SEQUENCE

OUTLINE DIMENSIONS

ORDERING GUIDE