ANALOG DEVICES AD9737A, AD9739A Service Manual

RF Digital-to-Analog Converters
AD9737A/AD9739A
Rev.
Trademarks and registered trademarks are the prop erty of their respective owner s.
Fax: 781.461.3113 ©2011-2012 Analog Devices, Inc. All rights reserved.
LVDS DDR
RECEIVER
DCI
SDO
SDIO
SCLK
CS
DACCLK
DCO
DB0[13:0]DB1[13:0]
CLK DISTRIBUTION
(DIV-BY-4)
DATA
CONTROLLER
4-TO-1
DATA ASSEMBL E R
SPI
RESET
DLL
(MU CONTRO LLER)
LVDS DDR
RECEIVER
DATA
LATCH
IOUTN
IOUTP
VREF I120
IRQ
1.2V
DAC BIAS
AD9737A/AD9739A
TxDAC
CORE
09616-001
C
Data Sheet

FEATURES

Direct RF synthesis at 2.5 GSPS update rate
DC to 1.25 GHz in baseband mode
1.25 GHz to 3.0 GHz in mix-mode Industry leading single/multicarrier IF or RF synthesis Dual-port LVDS data interface
Up to 1.25 GSPS operation
Source synchronous DDR clocking Pin compatible with the AD9739 Programmable output current: 8.7 mA to 31.7 mA Low power: 1.1 W at 2.5 GSPS

APPLICATIONS

Broadband communications systems
DOCSIS CMTS systems Military jammers Instrumentation, automatic test equipment Radar, avionics
11-/14-Bit, 2.5 GSPS,

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

GENERAL DESCRIPTION

The AD9737A/AD9739A are 11-bit and 14-bit, 2.5 GSPS high performance RF DACs that are capable of synthesizing wideband signals from dc up to 3 GHz. The AD9737A/AD9739A are pin and functionally compatible with the AD9739 with the exception that the AD9737A/AD9739A do not support synchronization or RZ mode, and are specified to operate between 1.6 GSPS and 2.5 GSPS.
By elimination of the synchronization circuitry, some nonideal artifacts such as images and discrete clock spurs remain stationary on the AD9737A/AD9739A between power-up cycles, thus allowing for possible system calibration. AC linearity and noise performance remain the same between the AD9739 and the
AD9737A/AD9739A.
The inclusion of on-chip controllers simplifies system integration. A dual-port, source synchronous, LVDS interface simplifies the digital interface with existing FGPA/ASIC technology. On-chip controllers are used to manage external and internal clock domain variations over temperature to ensure reliable data transfer from the host to the DAC core. A serial peripheral interface (SPI) is used for device configuration as well as readback of status registers.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
The AD9737A/AD9739A are manufactured on a 0.18 µm CMOS process and operate from 1.8 V and 3.3 V supplies. They are supplied in a 160-ball chip scale ball grid array for reduced package parasitics.

PRODUCT HIGHLIGHTS

1. Ability to synthesize high quality wideband signals with
bandwidths of up to 1.25 GHz in the first or second Nyquist zone.
2. A proprietary quad-switch DAC architecture provides
exceptional ac linearity performance while enabling mix­mode operation.
3. A dual-port, double data rate, LVDS interface supports the
maximum conversion rate of 2500 MSPS.
4. On-chip controllers manage external and internal clock
domain skews.
5. Programmable differential current output with an 8.66 mA
to 31.66 mA range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com
AD9737A/AD9739A Data Sheet
C
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 3
Specifications ..................................................................................... 4
DC Specifications ......................................................................... 4
LVDS Digital Specifications ........................................................ 5
Serial Port Specifications ............................................................. 6
AC Specifications .......................................................................... 7
Absolute Maximum Ratings ............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution .................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics—AD9737A ..................... 14
Static Linearity ............................................................................ 14
AC (Normal Mode) .................................................................... 15
AC (Mix-Mode) .......................................................................... 17
One-Carrier DOCSIS Performance (Normal Mode) ............ 20
Four-Carrier DOCSIS Performance (Normal Mode) ........... 21
Eight-Carrier DOCSIS Performance (Normal Mode) .......... 22
16-Carrier DOCSIS Performance (Normal Mode) ............... 23
32-Carrier DOCSIS Performance (Normal Mode) ............... 24
64- and 128-Carrier DOCSIS Performance (Normal Mode)25
Typical Performance Characteristics—AD9739A ..................... 26
Static Linearity ............................................................................ 26
AC (Normal Mode) .................................................................... 28
AC (Mix-Mode) .......................................................................... 31
One-Carrier DOCSIS Performance (Normal Mode) ............ 33
Four-Carrier DOCSIS Performance (Normal Mode) ........... 34
Eight-Carrier DOCSIS Performance (Normal Mode) .......... 35
16-Carrier DOCSIS Performance (Normal Mode) ............... 36
32-Carrier DOCSIS Performance (Normal Mode) ............... 37
64- and 128-Carrier DOCSIS Performance (Normal Mode)38
Terminology .................................................................................... 39
Serial Port Interface (SPI) Register ............................................... 40
SPI Register Map Description .................................................. 40
SPI Operation ............................................................................. 40
SPI Register Map ............................................................................ 42
SPI Port Configuration and Software Reset ........................... 43
Power-Down LVDS Interface and TxDAC® ........................... 43
Controller Clock Disable ........................................................... 43
Interrupt Request (IRQ) Enable/Status ................................... 44
TxDAC Full-Scale Current Setting (I
TxDAC Quad-Switch Mode of Operation .............................. 44
DCI Phase Alignment Status .................................................... 44
Data Receiver Controller Configuration ................................. 44
Data Receiver Controller_Data Sample Delay Value ............ 45
Data Receiver Controller_DCI Delay Value/Window and
Phase Rotation ............................................................................ 45
Data Receiver Controller_Delay Line Status .......................... 45
Data Receiver Controller Lock/Tracking Status ..................... 45
CLK Input Common Mode ...................................................... 46
Mu Controller Configuration and Status ................................ 46
Part ID ......................................................................................... 47
Theory of Operation ...................................................................... 48
LVDS Data Port Interface .......................................................... 49
Mu Controller ............................................................................. 52
Interrupt Requests ...................................................................... 54
Analog Interface Considerations .................................................. 55
Analog Modes of Operation ..................................................... 55
Clock Input Considerations ...................................................... 56
Voltage Reference ....................................................................... 57
Analog Outputs .......................................................................... 57
Output Stage Configuration ..................................................... 59
Nonideal Spectral Artifacts ....................................................... 60
Lab Evaluation of the AD9737A/AD9739A ........................... 61
Recommended Start-Up Sequence .......................................... 61
Outline Dimensions ....................................................................... 63
Ordering Guide .......................................................................... 63
) and Sleep ........... 44
OUTFS
Rev. | Page 2 of 64
Data Sheet AD9737A/AD9739A

REVISION HISTORY

2/12—Rev. B to Rev. C
Changes to Figure 5 ........................................................................... 9
Changes to Table 7 .......................................................................... 11
Changes to Ordering Guide ........................................................... 63
2/12—Rev. A to Rev. B
Added AD9737A ................................................................ Universal
Reorganized Layout ........................................................... Universal
Moved Revision History Section ..................................................... 3
Deleted ±6% from Table Summary Statement; Changes
to Table 1 ............................................................................................ 4
Deleted ±6% from Table Summary Statement, Table 2 ................ 5
Deleted ±6% from Table Summary Statement, Table 3 ................ 6
Changes to AC Specifications Section and Table 4 ....................... 7
Added Figure 5, Renumbered Sequentially ................................... 9
Added Figure 7 and Table 7, Renumbered Sequentially ............ 10
Deleted Figure 24 ............................................................................ 13
Added Typical Performance Characteristics—AD9737A
Section and Figure 9 to Figure 77 ................................................. 14
Deleted Table 9 ................................................................................ 25
Added Static Linearity Section and Figure 78 to Figure 88 ............ 26
Added Figure 106 ............................................................................ 30
Changes to Figure 116, Figure 117, Figure 118, Figure 119,
Figure 120, and Figure 121 ............................................................. 33
Changes to Figure 122, Figure 123, Figure 124, Figure 125,
Figure 126, and Figure 127 ............................................................. 34
Changes to Figure 128, Figure 129, Figure 130, Figure 131,
Figure 132, and Figure 133 ............................................................. 35
Changes to Figure 134, Figure 135, Figure 136, Figure 137,
Figure 138, and Figure 139 ............................................................. 36
Changes to Figure 140, Figure 141, Figure 142, Figure 143,
Figure 144, and Figure 145 ............................................................. 37
Changes to Figure 146, Figure 147, Figure 148, Figure 149,
and Figure 150; Added Figure 151 ................................................ 38
Added Table 10 ................................................................................ 42
Added SPI Port Configuration and Software Reset Section, Power-Down LVDS Interface and TxDAC Section, Controller
Clock Disable Section, and Table 11 to Table 13 ........................ 43
Added Interrupt Request (IRQ) Enable/Status Section, TxDAC Full-Scale Current Setting (I
) and Sleep Section, TxDAC
OUTFS
Quad-Switch Mode of Operation Section, DCI Phase Alignment Status Section, Data Receiver Controller
Configuration Section, and Table 14 to Table 18 ........................ 44
Added Data Receiver Controller_Data Sample Delay Value Section, Data Receiver Controller_DCI Delay Value/Window and Phase Rotation Section, Data Receiver Controller_Delay Line Status Section, Data Receiver Controller Lock/Tracking
Status Section, and Table 19 to Table 22 ...................................... 45
Added CLK Input Common Mode Section, and Mu Controller Configuration and Status Section, and Table 23
and Table 24 ..................................................................................... 46
Added Part ID Section, and Table 25 ........................................... 47
Changes to LVDS Data Port Interface Section ............................ 49
Changes to Data Receiver Controller Initialization
Description Section ........................................................................ 51
Changes to Mu Controller Section ............................................... 52
Added Figure 167 and Table 27, Changes to Mu Controller
Initialization Description Section ................................................. 53
Changes to Analog Modes of Operation Section, Figure 171,
and Figure 172 ................................................................................. 55
Updated Outline Dimensions ........................................................ 63
Changes to Ordering Guide ........................................................... 63
7/11—Rev. 0 to Rev. A
Changed Maximum Update Rate (DACCLK Input) Parameter
to DAC Clock Rate Parameter in Table 4 ....................................... 6
Added Adjusted DAC Update Rate Parameter and Endnote 1 in
Table 4 ................................................................................................. 6
Updated Outline Dimensions ........................................................ 43
1/11—Revision 0: Initial Version
Rev. C | Page 3 of 64
AD9737A/AD9739A Data Sheet
Parameter
Min
Typ
Max
Min
Typ
Max
Unit
Output Compliance Range
−1.0
+1.0
−1.0 +1.0
V
VDD
1.70
1.8
1.90
1.70
1.8
1.90
V
I
158
167 158
167
mA
I
215
215 mA
C

SPECIFICATIONS

DC SPECIFICATIONS

VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, I
Table 1.
AD9737A AD9739A
RESOLUTION 11 14 Bits ACCURACY
Integral Nonlinearity (INL) ±0.5 ±2.5 LSB Differential Nonlinearity (DNL) ±0.5 ±2.0 LSB
ANALOG OUTPUTS
Gain Error (with Internal Reference) 5.5 5.5 % Full-Scale Output Current 8.66 20.2 31.66 8.66 20.2 31.66 mA
Common-Mode Output Resistance 10 10 MΩ Differential Output Resistance 70 70 Ω Output Capacitance 1 1 pF
DAC CLOCK INPUT (DACCLK_P, DACCLK_N)
Differential Peak-to-Peak Voltage 1.2 1.6 2.0 1.2 1.6 2.0 V Common-Mode Voltage 900 900 mV Clock Rate 1.6 2.5 1.6 2.5 GHz
TEMPERATURE DRIFT
Gain 60 60 ppm/°C Reference Voltage 20 20 ppm/°C
REFERENCE
Internal Reference Voltage 1.15 1.2 1.25 1.15 1.2 1.25 V Output Resistance 5 5 kΩ
ANALOG SUPPLY VOLTAGES
VDDA 3.1 3.3 3.5 3.1 3.3 3.5 V VDDC 1.70 1.8 1.90 1.70 1.8 1.90 V
DIGITAL SUPPLY VOLTAGES
VDD33 3.10 3.3 3.5 3.10 3.3 3.5 V
OUTFS
= 20 mA.
SUPPLY CURRENTS AND POWER DISSIPATION, 2.0 GSPS
I
37 38 37 38 mA
VDDA
VDDC
I
14.5 16 14.5 16 mA
VDD33
I
173 183 173 183 mA
VDD
Power Dissipation 0.770 0.770 W Sleep Mode, I Power-Down Mode (All Power-Down Bits Set in Register 0x01 and
Register 0x02) I
0.02 0.02 mA
VDDA
I
6 6 mA
VDDC
I
0.6 0.6 mA
VDD33
I
0.1 0.1 mA
VDD
SUPPLY CURRENTS AND POWER DISSIPATION, 2.5 GSPS
I
223 223 mA
VDDC
I
14.5 14.5 mA
VDD33
VDD
Power Dissipation 0.960 0.960 mW
2.5 2.75 2.5 2.75 mA
VDDA
Rev. | Page 4 of 64
Data Sheet AD9737A/AD9739A
Receiver Differential Input Impedance, RIN
80 120
RO Single-Ended Mismatch
10
%
C

LVDS DIGITAL SPECIFICATIONS

VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, I 1996 reduced range link, unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit
LVDS DATA INPUTS (DB0[13:0], DB1[13:0])1
Input Common-Mode Voltage Range, V
Logic High Differential Input Threshold, V
Logic Low Differential Input Threshold, V
825 1575 mV
COM
175 400 mV
IH_DTH
−175 −400 mV
IL_DTH
Input Capacitance 1.2 pF
LVDS Input Rate 1250 MSPS
LVDS Minimum Data Valid Period (t
) (See Figure 159) 344 ps
MDE
LVDS CLOCK INPUT (DCI)2
Input Common-Mode Voltage Range, V
Logic High Differential Input Threshold, V
Logic Low Differential Input Threshold, V
825 1575 mV
COM
175 400 mV
IH_DTH
−175 −400 mV
IL_DTH
Receiver Differential Input Impedance, RIN 80 120
Input Capacitance 1.2 pF
Maximum Clock Rate 625 MHz
LVDS CLOCK OUTPUT (DCO)3
Output Voltage High (DCO_P or DCO_N) 1375 mV
Output Voltage Low (DCO_P or DCO_N) 1025 mV
Output Differential Voltage, |VOD| 150 200 250 mV
Output Offset Voltage, VOS 1150 1250 mV
Output Impedance, Single-Ended, RO 80 100 120
= 20 mA. LVDS drivers and receivers are compliant to the IEEE Standard 1596.3-
OUTFS
Maximum Clock Rate 625 MHz
1
DB0[x]P, DB0[x]N, DB1[x]P, and DB1[x]N pins.
2
DCI_P and DCI_N pins.
3
DCO_P and DCO_N pins with 100 Ω differential termination.
Rev. | Page 5 of 64
AD9737A/AD9739A Data Sheet
SCLK to SDIO Hold Time, tDH
1
ns
READ OPERATION (See Figure 155 and Figure 156)
Current Out High, IOH
4
mA
C

SERIAL PORT SPECIFICATIONS

VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V.
.
Tabl e 3
Parameter Min Typ Max Unit
WRITE OPERATION (See Figure 154)
SCLK Clock Rate, f SCLK Clock High, t SCLK Clock Low, t SDIO to SCLK Setup Time, tDS 2 ns
, 1/t
SCLK
HIGH
LOW
20 MHz
SCLK
18 ns
18 ns
CS to SCLK Setup Time, tS SCLK to CS Hold Time, tH
SCLK Clock Rate, f SCLK Clock High, t SCLK Clock Low, t
, 1/t
SCLK
18 ns
HIGH
18 ns
LOW
20 MHz
SCLK
3 ns 2 ns
SDIO to SCLK Setup Time, tDS 2 ns SCLK to SDIO Hold Time, tDH 1 ns CS to SCLK Setup Time, tS
3 ns SCLK to SDIO (or SDO) Data Valid Time, tDV 15 ns CS to SDIO (or SDO) Output Valid to High-Z, tEZ
INPUTS (SDI, SDIO, SCLK, CS)
2 ns
Voltage in High, VIH 2.0 3.3 V Voltage in Low, VIL 0 0.8 V Current in High, IIH −10 +10 µA Current in Low, IIL −10 +10 µA
OUTPUT (SDIO)
Voltage Out High, VOH 2.4 3.5 V Voltage Out Low, VOL 0 0.4 V
Current Out Low, IOL 4 mA
Rev. | Page 6 of 64
Data Sheet AD9737A/AD9739A
C

AC SPECIFICATIONS

VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, I
Table 4.
AD9737A AD9739A Parameter Min Typ Max Min Typ Max Unit
DYNAMIC PERFORMANCE
DAC Clock Rate 1600 2500 1600 2500 MSPS Adjusted DAC Update Rate1 1600 2500 1600 2500 MSPS Output Settling Time to 0.1% 13 13 ns
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
f
= 100 MHz 70 70 dBc
OUT
f
= 350 MHz 65 65 dBc
OUT
f
= 550 MHz 58 58 dBc
OUT
f
= 950 MHz 55 55 dBc
OUT
TWO-TONE INTERMODULATION DISTORTION (IMD),
f
= f
+ 1.25 MHz
OUT1
= 100 MHz 94 94 dBc = 350 MHz 78 78 dBc = 550 MHz 72 72 dBc = 950 MHz 68 68 dBc
f f f f
OUT2
OUT
OUT
OUT
OUT
NOISE SPECTRAL DENSITY (NSD), 0 dBFS SINGLE TONE
f
= 100 MHz −162 −167 dBm/Hz
OUT
f
= 350 MHz −162 −166 dBm/Hz
OUT
f
= 550 MHz −161 −164 dBm/Hz
OUT
f
= 850 MHz −161 −163 dBm/Hz
OUT
WCDMA ACLR (SINGLE CARRIER), ADJACENT/ALTERNATE
ADJACENT CHANNEL f
= 2457.6 MSPS, f
DAC
f
= 2457.6 MSPS, f
DAC
f
= 2457.6 MSPS, f
DAC
f
= 2457.6 MSPS, f
DAC
1
Adjusted DAC updated rate is calculated as f
is 1. Thus, with f
= 2500 MSPS, f
DAC
= 350 MHz 80/81 80/80 dBc
OUT
= 950 MHz 75/75 78/79 dBc
OUT
= 1700 MHz (Mix-Mode) 69/71 74/74 dBc
OUT
= 2100 MHz (Mix-Mode) 66/67 69/72 dBc
OUT
divided by the minimum required interpolation factor. For the AD9737A/AD9739A, the minimum interpolation factor
DAC
, adjusted, = 2500 MSPS.
DAC
= 20 mA, f
OUTFS
= 2400 MSPS, unless otherwise noted.
DAC
Rev. | Page 7 of 64
AD9737A/AD9739A Data Sheet
VDD33 to VSS
−0.3 V to +3.6 V
DACCLK_P, DACCLK_N to VSSC
−0.3 V to VDDC + 0.18 V
C

ABSOLUTE MAXIMUM RATINGS

Table 5.
Parameter Rating
VDDA to VSSA −0.3 V to +3.6 V

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.
VDD to VSS −0.3 V to +1.98 V VDDC to VSSC −0.3 V to +1.98 V VSSA to VSS −0.3 V to +0.3 V VSSA to VSSC −0.3 V to +0.3 V VSS to VSSC −0.3 V to +0.3 V
DCI, DCO to VSS −0.3 V to VDD33 + 0.3 V LVDS Data Inputs to VSS −0.3 V to VDD33 + 0.3 V IOUTP, IOUTN to VSSA −1.0 V to VDDA + 0.3 V I120, VREF to VSSA −0.3 V to VDDA + 0.3 V IRQ, CS, SCLK, SDO, SDIO, RESET to VSS Junction Temperature 150°C Storage Temperature Range −65°C to +150°C
−0.3 V to VDD33 + 0.3 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 6. Thermal Resistance
Package Type θJA θJC Unit
160-Ball CSP_BGA 31.2 7.0 °C/W1
1
With no airflow movement.

ESD CAUTION

Rev. | Page 8 of 64
Data Sheet AD9737A/AD9739A

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1413121110876321954
1413121110876321954
A B C D E
F G H
J K
L M N
P
VDDA, 3.3V, ANALOG S UPPLY VSSA, ANALOG SUPPLY GROUND VSSA SHIELD, ANAL OG SUPPLY GROUND SHIELD
AD9737A/AD9739A
Figure 2. Analog Supply Pins (Top View)
A B C D E F G H
J
K
L
M
N P
VDD, 1.8V, DIGITAL SUPPLY VSS DIGITAL SUPPLY GROUND VDD33, 3.3V DIGITAL SUPPLY
AD9737A/AD9739A
Figure 3. Digital Supply Pins (Top View)
A B C D E F G H
J K L M N P
VDDC, 1.8V, CLOCK S UP PLY VSSC, CLOCK SUPPLY GROUND
09616-002
1413121110876321954
DB1[0:10]P
DB0[0:10]P N DB0[0:10]N P
Figure 4. Digital LVDS Clock Supply Pins (Top View)
A
B CDACCLK_N DDACCLK_P
E
F
G
H
J K L
MDB1[0:10]N
DIFFERE NTIAL I NP UT SIGNAL (CLOCK OR DATA)
AD9737A/AD9739A
AD9737A
1413121110876321954
09616-004
DCO_P/_N DCI_P/_N
09616-036
Figure 5. AD9737A Digital LVDS Input, Clock I/O (Top View)
1413121110876321954
09616-003
DACCLK_N DACCLK_P
DB1[0:13]P
DB1[0:13]N
DB0[0:13]P
DB0[0:13]N
A B
C D E F G H
J
K
L M N P
AD9739A
DCO_P/_N DCI_P/_N
Rev. C | Page 9 of 64
DIFFERENTIAL INPUT SIGNAL (CLOCK OR DATA)
Figure 6. AD9739A Digital LVDS Input, Clock I/O (Top View)
09616-005
AD9737A/AD9739A Data Sheet
A B C D
E
F G H
J K
L M N
P
14131211106321 954
IRQ
CS
SCLK
RESET SDIO SDO
7
IOUTN
8
IOUTP
I120 VREF
09616-006
AD9737A
A10, A11, B10, B11, C10, C11, D10, D11
VDDA
3.3 V Analog Supply Input.
A8, B8, C8, D8
IOUTP
DAC Positive Current Output Source.
D14
NC
Factory Test Pin. Do not connect to this pin.
G14
SDIO
Serial Port Data Input/Output.
K13, K14
DCI_P/DCI_N
Positive/Negative Data Clock Input (DCI).
C
Table 7. AD9737A Pin Function Descriptions
Pin No. Mnemonic Description
C1, C2, D1, D2, E1, E2, E3, E4 VDDC 1.8 V Clock Supply Input. A1, A2, A3, A4, A5, B1, B2, B3, B4, B5, C4,
C5, D4, D5
A12, A13, B12, B13, C12, C13, D12, D13, VSSA Analog Supply Ground. A6, A9, B6, B9, C6, C9, D6, D9, E11, E12,
E13, E14, F1, F2, F3, F4, F11, F12 A14 NC Do not connect to this pin. A7, B7, C7, D7 IOUTN DAC Negative Current Output Source.
B14 I120
C14 VREF
C3, D3 DACCLK_N/DACCLK_P Negative/Positive DAC Clock Input (DACCLK). F13 IRQ
F14 RESET Reset Input. Active high. Tie to VSS if unused. G13
H13 SCLK Serial Port Clock Input. H14 SDO Serial Port Data Output. J3, J4, J11, J12 VDD33 3.3 V Digital Supply Input. G1, G2, G3, G4, G11, G12 VDD 1.8 V Digital Supply Input. H1, H2, H3, H4, H11, H12, K3, K4, K11, K12 VSS Digital Supply Ground. J1, J2 NC
K1, K2 NC
J13, J14 DCO_P/DCO_N Positive/Negative Data Clock Output (DCO).
Figure 7. AD9737A Analog I/O and SPI Control Pins (Top View)
VSSC Clock Supply Ground.
VSSA Shield Analog Supply Ground Shield. Tie to VSSA at the DAC.
Nominal 1.2 V Reference. Tie to analog ground via a 10 kΩ resistor to generate a 120 µA reference current.
Voltage Reference Input/Output. Decouple to VSSA with a 1 nF capacitor.
Interrupt Request Open Drain Output. Active high. Pull up to VDD33 with a 10 kΩ resistor.
CS
Serial Port Enable Input.
Differential resistor of 200 Ω exists between J1 and J2. Do not
Rev. | Page 10 of 64
connect to this pin. Differential resistor of 100 Ω exists between K1 and K2. Do not
connect to this pin.
Data Sheet AD9737A/AD9739A
Pin No. Mnemonic Description
L1, M1 NC, NC Do not connect to this pin. L2, M2 NC, NC Do not connect to this pin. L3, M3 NC, NC Do not connect to this pin. L4, M4 DB1[0]P/DB1[0]N Port 1 Positive/Negative Data Input Bit 0. L5, M5 DB1[1]P/DB1[1]N Port 1 Positive/Negative Data Input Bit 1. L6, M6 DB1[2]P/DB1[2]N Port 1 Positive/Negative Data Input Bit 2. L7, M7 DB1[3]P/DB1[3]N Port 1 Positive/Negative Data Input Bit 3. L8, M8 DB1[4]P/DB1[4]N Port 1 Positive/Negative Data Input Bit 4. L9, M9 DB1[5]P/DB1[5]N Port 1 Positive/Negative Data Input Bit 5. L10, M10 DB1[6]P/DB1[6]N Port 1 Positive/Negative Data Input Bit 6. L11, M11 DB1[7]P/DB1[7]N Port 1 Positive/Negative Data Input Bit 7. L12, M12 DB1[8]P/DB1[8]N Port 1 Positive/Negative Data Input Bit 8. L13, M13 DB1[9]P/DB1[9]N Port 1 Positive/Negative Data Input Bit 9. L14, M14 DB1[10]P/DB1[10]N Port 1 Positive/Negative Data Input Bit 10. N1, P1 NC, NC Do not connect to this pin. N2, P2 NC, NC Do not connect to this pin. N3, P3 NC, NC Do not connect to this pin. N4, P4 DB0[0]P/DB0[0]N Port 0 Positive/Negative Data Input Bit 0. N5, P5 DB0[1]P/DB0[1]N Port 0 Positive/Negative Data Input Bit 1. N6, P6 DB0[2]P/DB0[2]N Port 0 Positive/Negative Data Input Bit 2. N7, P7 DB0[3]P/DB0[3]N Port 0 Positive/Negative Data Input Bit 3. N8, P8 DB0[4]P/DB0[4]N Port 0 Positive/Negative Data Input Bit 4. N9, P9 DB0[5]P/DB0[5]N Port 0 Positive/Negative Data Input Bit 5. N10, P10 DB0[6]P/DB0[6]N Port 0 Positive/Negative Data Input Bit 6. N11, P11 DB0[7]P/DB0[7]N Port 0 Positive/Negative Data Input Bit 7. N12, P12 DB0[8]P/DB0[8]N Port 0 Positive/Negative Data Input Bit 8. N13, P13 DB0[9]P/DB0[9]N Port 0 Positive/Negative Data Input Bit 9. N14, P14 DB0[10]P/DB0[10]N Port 0 Positive/Negative Data Input Bit 10.
Rev. C | Page 11 of 64
AD9737A/AD9739A Data Sheet
IOUTN8IOUTP
7
A B C D
E
F G H
J K
L M N
P
Figure 8. AD9739A Analog I/O and SPI Control Pins (Top View)
AD9739A
14131211106321954
I120 VREF
IRQ
CS
SCLK
RESET SDIO SDO
09616-037
Table 8. AD9739A Pin Function Descriptions
Pin No. Mnemonic Description
C1, C2, D1, D2, E1, E2, E3, E4 VDDC 1.8 V Clock Supply Input. A1, A2, A3, A4, A5, B1, B2, B3, B4, B5, C4,
VSSC Clock Supply Ground.
C5, D4, D5 A10, A11, B10, B11, C10, C11, D10, D11 VDDA 3.3 V Analog Supply Input. A12, A13, B12, B13, C12, C13, D12, D13, VSSA Analog Supply Ground. A6, A9, B6, B9, C6, C9, D6, D9, E11, E12,
VSSA Shield Analog Supply Ground Shield. Tie to VSSA at the DAC.
E13, E14, F1, F2, F3, F4, F11, F12 A14 NC Do not connect to this pin. A7, B7, C7, D7 IOUTN DAC Negative Current Output Source. A8, B8, C8, D8 IOUTP DAC Positive Current Output Source. B14 I120
Nominal 1.2 V Reference. Tie to analog ground via a 10 kΩ resistor to generate a 120 μA reference current.
C14 VREF
Voltage Reference Input/Output. Decouple to VSSA with a 1 nF
capacitor. D14 NC Factory Test Pin. Do not connect to this pin. C3, D3 DACCLK_N/DACCLK_P Negative/Positive DAC Clock Input (DACCLK). F13 IRQ
Interrupt Request Open Drain Output. Active high. Pull up to
VDD33 with a 10 kΩ resistor. F14 RESET Reset Input. Active high. Tie to VSS if unused. G13
CS
Serial Port Enable Input. G14 SDIO Serial Port Data Input/Output.
H13 SCLK Serial Port Clock Input. H14 SDO Serial Port Data Output. J3, J4, J11, J12 VDD33 3.3 V Digital Supply Input. G1, G2, G3, G4, G11, G12 VDD 1.8 V Digital Supply Input. H1, H2, H3, H4, H11, H12, K3, K4, K11, K12 VSS Digital Supply Ground. J1, J2 NC
Differential resistor of 200 Ω exists between J1 and J2. Do not
connect to this pin. K1, K2 NC
Differential resistor of 100 Ω exists between K1 and K2. Do not
connect to this pin. J13, J14 DCO_P/DCO_N Positive/Negative Data Clock Output (DCO). K13, K14 DCI_P/DCI_N Positive/Negative Data Clock Input (DCI).
Rev. C | Page 12 of 64
Data Sheet AD9737A/AD9739A
Pin No. Mnemonic Description
L1, M1 DB1[0]P/DB1[0]N Port 1 Positive/Negative Data Input Bit 0. L2, M2 DB1[1]P/DB1[1]N Port 1 Positive/Negative Data Input Bit 1. L3, M3 DB1[2]P/DB1[2]N Port 1 Positive/Negative Data Input Bit 2. L4, M4 DB1[3]P/DB1[3]N Port 1 Positive/Negative Data Input Bit 3. L5, M5 DB1[4]P/DB1[4]N Port 1 Positive/Negative Data Input Bit 4. L6, M6 DB1[5]P/DB1[5]N Port 1 Positive/Negative Data Input Bit 5. L7, M7 DB1[6]P/DB1[6]N Port 1 Positive/Negative Data Input Bit 6. L8, M8 DB1[7]P/DB1[7]N Port 1 Positive/Negative Data Input Bit 7. L9, M9 DB1[8]P/DB1[8]N Port 1 Positive/Negative Data Input Bit 8. L10, M10 DB1[9]P/DB1[9]N Port 1 Positive/Negative Data Input Bit 9. L11, M11 DB1[10]P/DB1[10]N Port 1 Positive/Negative Data Input Bit 10. L12, M12 DB1[11]P/DB1[11]N Port 1 Positive/Negative Data Input Bit 11. L13, M13 DB1[12]P/DB1[12]N Port 1 Positive/Negative Data Input Bit 12. L14, M14 DB1[13]P/DB1[13]N Port 1 Positive/Negative Data Input Bit 13. N1, P1 DB0[0]P/DB0[0]N Port 0 Positive/Negative Data Input Bit 0. N2, P2 DB0[1]P/DB0[1]N Port 0 Positive/Negative Data Input Bit 1. N3, P3 DB0[2]P/DB0[2]N Port 0 Positive/Negative Data Input Bit 2. N4, P4 DB0[3]P/DB0[3]N Port 0 Positive/Negative Data Input Bit 3. N5, P5 DB0[4]P/DB0[4]N Port 0 Positive/Negative Data Input Bit 4. N6, P6 DB0[5]P/DB0[5]N Port 0 Positive/Negative Data Input Bit 5. N7, P7 DB0[6]P/DB0[6]N Port 0 Positive/Negative Data Input Bit 6. N8, P8 DB0[7]P/DB0[7]N Port 0 Positive/Negative Data Input Bit 7. N9, P9 DB0[8]P/DB0[8]N Port 0 Positive/Negative Data Input Bit 8. N10, P10 DB0[9]P/DB0[9]N Port 0 Positive/Negative Data Input Bit 9. N11, P11 DB0[10]P/DB0[10]N Port 0 Positive/Negative Data Input Bit 10. N12, P12 DB0[11]P/DB0[11]N Port 0 Positive/Negative Data Input Bit 11. N13, P13 DB0[12]P/DB0[12]N Port 0 Positive/Negative Data Input Bit 12. N14, P14 DB0[13]P/DB0[13]N Port 0 Positive/Negative Data Input Bit 13.
Rev. C | Page 13 of 64
AD9737A/AD9739A Data Sheet
0.3
–0.4
0 2048
ERROR (LSB)
CODE
–0.3
–0.2
–0.1
0
0.1
0.2
256 512 768 1024 1280 1536 1792
09616-109
0.4
–0.3
0 2048
ERROR (LSB)
CODE
–0.2
–0.1
0
0.1
0.2
0.3
256 512 768 1024 1280 1536 1792
09616-110
0.25
–0.25
0 2048
ERROR (LSB)
CODE
–0.20
–0.10
–0.15
–0.05
0
0.10
0.05
0.15
0.20
256 512 768 1024 1280 1536 1792
09616-111
0.25
–0.25
0 2048
ERROR (LSB)
CODE
–0.20
–0.10
–0.15
–0.05
0
0.10
0.05
0.15
0.20
256 512 768 1024 1280 1536 1792
09616-112
0.6
–0.6
–0.5
–0.4
–0.3
0 2048
ERROR (LSB)
CODE
–0.2
–0.1
0
0.1
0.2
0.3
0.5
0.4
256 512 768 1024 1280 1536 1792
09616-113
0.2
–0.8
–0.7
–0.6
–0.5
–0.4
–0.3
0 2048
ERROR (LSB)
CODE
–0.2
–0.1
0
0.1
256 512 768 1024 1280 1536 1792
09616-114
C

TYPICAL PERFORMANCE CHARACTERISTICS—AD9737A

STATIC LINEARITY

I
= 20 mA, nominal supplies, TA = 25°C, unless otherwise noted.
OUTFS
Figure 9. Typical INL, 20 mA at 25°C
Figure 10. Typical DNL, 20 mA at 25°C
Figure 12. Typical DNL, 10 mA at 25°C
Figure 13. Typical INL, 30 mA at 25°C
Figure 11. Typical INL, 10 mA at 25°C
Figure 14. Typical DNL, 30 mA at 25°C
Rev. | Page 14 of 64
Data Sheet AD9737A/AD9739A
10dB/DIV
STOP 2.4GHzSTART 20MHz
VBW 20kHz
09616-115
10dB/DIV
VBW 20kHz
STOP 2.4GHzSTART 20MHz
09616-116
90
80
0
10
20
30
40
50
60
70
0 12001000800600400200
SFDR (dBc)
f
OUT
(MHz)
1.6GSPS
2.4GSPS
1.2GSPS
2.0GSPS
09616-117
120
100
80
60
40
20
0
0 200 400 600 800 1000 1200 1400
IIMD (d Bc)
f
OUT
(MHz)
2.0GSPS
1.6GSPS
1.2GSPS
2.4GSPS
09616-118
–150
–170
0 200 400 600 800 1000 1200
NSD (dBm/Hz)
f
OUT
(MHz)
1.2GSPS
2.4GSPS
–168
–166
–164
–162
–160
–158
–156
–154
–152
09616-119
–150
–170
0 200 400 600 800 1000 1200
NSD (dBm/Hz)
f
OUT
(MHz)
1.2GSPS
2.4GSPS
–168
–166
–164
–162
–160
–158
–156
–154
–152
09616-120
C

AC (NORMAL MODE)

I
= 20 mA, nominal supplies, TA = 25°C, unless otherwise noted.
OUTFS
Figure 15. Single Tone Spectrum at f
Figure 16. Single-Tone Spectrum at f
= 91 MHz, f
OUT
= 1091 MHz, f
OUT
= 2.4 GSPS
DAC
= 2.4 GSPS
DAC
Figure 18. IMD vs. f
OUT
over f
DAC
Figure 19. Single-Tone NSD over f
OUT
Figure 17. SFDR vs. f
OUT
over f
DAC
Figure 20. Eight-Tone NSD over f
OUT
Rev. | Page 15 of 64
AD9737A/AD9739A Data Sheet
90
30
0 200 300100 400 600 700500 900800 1000
SFDR (dBc)
f
OUT
(MHz)
35
40
45
50
55
60
65
70
75
80
85
–3dBFS
0dBFS
–6dBFS
09616-121
90
30
0 200 400 600 800 1000
SFDR (dBc)
f
OUT
(MHz)
40
50
60
70
80
–3dBFS
0dBFS
–6dBFS
09616-122
90
30
0 200 400 600 800 1000
SFDR (dBc)
f
OUT
(MHz)
40
50
60
70
80
0dBFS
–6dBFS
–3dBFS
09616-123
100
40
0 1000
IMD (dBc)
f
OUT
(MHz)
0dBFS
45
50
55
60
65
70
75
80
85
90
95
100 200 300 400 500 600 700 800 900
–3dBFS
–6dBFS
09616-124
30
40 35
0 1000
SFDR (dBc)
f
OUT
(MHz)
45
50
55
60
65
70
75
80
85
90
100 200 300 400 500 600 700 800 900
30mA FS
10mA FS
20mA FS
09616-125
40
0 1000
IMD (dBc)
f
OUT
(MHz)
45
50
55
60
65
70
75
80
85
90
95
100
100 200 300 400 500 600 700 800 900
20mA FS
30mA FS
10mA FS
09616-126
C
f
= 2 GSPS, I
DAC
= 20 mA, nominal supplies, TA = 25°C, unless otherwise noted.
OUTFS
Figure 21. SFDR vs. f
over Digital Full Scale
OUT
Figure 22. SFDR for Second Harmonic vs. f
over Digital Full Scale
OUT
Figure 24. IMD vs. f
Figure 25. SFDR vs. f
over Digital Full Scale
OUT
over DAC I
OUT
OUTFS
Figure 23. SFDR for Third Harmonic vs. f
over Digital Full Scale
OUT
Rev. | Page 16 of 64
Figure 26. IMD vs. f
over DAC I
OUT
OUTFS
Data Sheet AD9737A/AD9739A
09616-127
30
40 35
0 1000
SFDR (dBc)
f
OUT
(MHz)
45
50
55
60
65
70
75
80
85
90
100 200 300 400 500 600 700 800 900
+85°C
–40°C
+25°C
09616-128
40
0 1000
IMD (dBc)
f
OUT
(MHz)
45
50
55
60
65
70
75
80
85
90
95
100
100 200 300 400 500 600 700 800 900
–40°C
+25°C
+85°C
09616-129
–170
–168
–166
–164
–162
–160
–158
–156
–154
–152
–150
0 200 400 600 800 1000100 300 500 700 900
f
OUT
(MHz)
NSD (dBm/Hz)
+25°C
+85°C
09616-130
–170
–168
–166
–164
–162
–160
–158
–156
–154
–152
–150
0 200 400 600 800 1000100 300 500 700 900
f
OUT
(MHz)
NSD (dBm/Hz)
+25°C
+85°C
SPAN 54.68MHz
SWEEP 1.509s
CENTER 350MHz #RES BW 30kHz
UPPER
FILTER ON ON ON ON ON
dBc –79.73 –80.21 –80.85 –81.41 –81.46
dBc –80.51 –81.11 –81.67 –81.61 –82.19
dBm –92.90 –93.38 –94.01 –94.58 –94.63
LOWER
dBm –93.67 –94.27 –94.84 –94.77 –95.35
INTEG B W
3.840MHz
3.840MHz
3.840MHz
3.840MHz
3.840MHz
OFFSET FREQ
5.000MHz
10.00MHz
15.00MHz
20.00MHz
25.00MHz
CARRIER POWER –13.167dBm/3.84MHz ACP-IBW
10dB/DIV
–35
–45
–55
–65
–75
–85
–95
–105
–115
09616-131
VBW 3kHz
–81.4dBc–81.1dBc
–80.5dBc –13.2dBm
–80.8dBc
–80.2dBc
–79.7dBc –81.5dBc
–81.6dBc–82.2dBc
–81.7dBc
–50
–55
–60
–65
–70
–75
–80
–85
–90
0 200 400 600 800 140012001000
ACLR (dBc)
f
OUT
(MHz)
09616-226
FIRST ADJ CH
FIFT H ADJ CH
SECOND ADJ CH
C

AC (MIX-MODE)

f
= 2.1 GSPS, I
DAC
= 20 mA, nominal supplies, TA = 25°C, unless otherwise noted.
OUTFS
Figure 27. SFDR vs. f
over Temperature
OUT
Figure 30. Eight-Tone NSD vs. f
over Temperature
OUT
Figure 28. IMD vs. f
Figure 29. Single-Tone NSD vs. f
over Temperature
OUT
over Temperature
OUT
Figure 31. Single-Carrier WCDMA at 350 MHz, f
Figure 32. Single-Carrier WCDMA ACLR vs. f
= 2457.6 MSPS
DAC
at 2457.6 MSPS
OUT
Rev. | Page 17 of 64
AD9737A/AD9739A Data Sheet
09616-132
10dB/DIV
STOP 2.4GHz
SWEEP 7.174s (601pts)
START 20MHz #RES BW 20kHz
VBW 20kHz
09616-133
10dB/DIV
STOP 2.4GHz
SWEEP 7.174s (601pts)
START 20MHz #RES BW 20kHz
VBW 20kHz
09616-134
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400
f
OUT
(MHz)
SFDR (dBc)
09616-135
30
40
50
60
70
90
80
100
1000 130012001100 1400 1500 1600 1700 1800 1900 2000
IMD (dBc)
f
OUT
(MHz)
09616-136
SPAN 54.68MHz
SWEEP 1.509s
CENTER 2.108MHz #RES BW 30kHz
UPPER
FILTER ON ON ON ON ON
dBc –69.84 –71.15 –71.75 –72.19 –72.70
dBc –69.82 –69.93 –71.77 –72.26 –71.90
dBm –89.36 –90.67 –91.28 –91.71 –92.22
LOWER
dBm –88.34 –89.46 –91.29 –91.79 –91.42
INTEG B W
3.840MHz
3.840MHz
3.840MHz
3.840MHz
3.840MHz
OFFSET FREQ
5.000MHz
10.00MHz
15.00MHz
20.00MHz
25.00MHz
CARRIER POWER –19.526dBm/3.84MHz ACP-IBW
10dB/DIV
–35
–45
–55
–65
–75
–85
–95
–105
–115
VBW 3kHz
–72.7dBc
–71.8dBc –69.9dBc –68.8dBc
–19.5dBm
–72.3dBc–71.9dBc –69.8dBc –71.1dBc –71.8dBc –72.2dBc
f
DAC
= 2457.6 MSPS (Second Nyquist Zone)
–90
–85
–80
–75
–70
–65
–60
–55
–50
1307.6
3557.6
1557.6
1807.6
2057.6
2307.6
2557.6
2807.6
3057.6
3307.6
SECOND NYQUI S T ZONE THIRD NYQUIST ZONE
FIRST ADJ CH
THIRD ADJ CH
ACLR (dBc)
09616-137
f
OUT
(MHz)
SECOND ADJ CH
Figure 38. Single-Carrier WCDMA ACLR vs. f
OUT
, f
DAC
= 2457.6 MSPS
C
f
= 2.1 GSPS, I
DAC
= 20 mA, nominal supplies, TA = 25°C, unless otherwise noted.
OUTFS
Figure 33. Single-Tone Spectrum at f
Figure 34. Single-Tone Spectrum at f
= 2.31 GHz, f
OUT
= 1.31 GHz, f
OUT
= 2.4 GSPS
DAC
= 2.4 GSPS
DAC
Figure 36. IMD in Mix-Mode vs. f
at 2.4 GSPS
OUT
Figure 37. Typical Single-Carrier WCDMA ACLR Performance at 2.1 GHz,
Figure 35. SFDR in Mix-mode vs. f
at 2.4 GSPS
OUT
Rev. | Page 18 of 64
Data Sheet AD9737A/AD9739A
09616-138
SPAN 54.68MHz
SWEEP 1.509s
CENTER 2.808MHz #RES BW 30kHz
UPPER
FILTER ON ON ON ON ON
dBc –65.56 –65.82 –65.98 –66.06 –66.14
dBc –65.65 –65.70 –65.81 –65.84 –65.84
dBm –94.72 –94.98 –95.14 –95.22 –95.31
LOWER
dBm –94.81 –94.86 –94.97 –95.00 –95.00
INTEG B W
3.840MHz
3.840MHz
3.840MHz
3.840MHz
3.840MHz
OFFSET FREQ
5.000MHz
10.00MHz
15.00MHz
20.00MHz
25.00MHz
CARRIER POWER –26.161dBm/3.84MHz ACP-IBW
10dB/DIV
–45
–55
–65
–75
–85
–95
–115
–105
–125
VBW 3kHz
–66.1dBc –66.1dBc–65.8dBc –65.7dBc
–65.6dBc –29.2dBm–65.8dBc –65.8dBc –65.6dBc –65.8dBc –66.0dBc
09616-139
SPAN 69.68MHz
SWEEP 1.922s
CENTER 2.108MHz #RES BW 30kHz
UPPER
FILTER ON ON ON ON ON
dBc –64.93 –64.26 –65.21 –65.74 –66.13
dBc –65.42 –64.93 –65.12 –65.24 –65.61
dBm –92.23 –91.56 –92.50 –93.04 –93.42
LOWER
dBm –92.72 –92.23 –92.42 –92.53 –92.91
INTEG B W
3.840MHz
3.840MHz
3.840MHz
3.840MHz
3.840MHz
OFFSET FREQ
5.000MHz
10.00MHz
15.00MHz
20.00MHz
25.00MHz
CARRIER POWER –21.446dBm/15.36MHz ACP-IBW
10dB/DIV
–50
–60
–70
–80
–90
–100
–120
–110
–130
VBW 3kHz
–65.2dBc
–65.4dBc
–27.6dBm
–27.6dBm
–27.3dBm
–27.4dBm
–64.9dBc–64.9dBc
–64.3dBc –65.7dBc
–66.1dBc
–65.1dBc
–65.2dBc
–65.6dBc
09616-140
SPAN 69.68MHz
SWEEP 1.922s
CENTER 2.808MHz #RES BW 30kHz
UPPER
FILTER ON ON ON ON ON
dBc –58.20 –58.15 –58.26 –58.33 –58.21
dBc –58.05 –57.95 –57.95 –57.97 –58.05
dBm –95.26 –95.21 –95.32 –95.39 –95.27
LOWER
dBm
–95.11 –95.02 –95.01 –95.04
–95.11
INTEG B W
3.840MHz
3.840MHz
3.840MHz
3.840MHz
3.840MHz
OFFSET FREQ
5.000MHz
10.00MHz
15.00MHz
20.00MHz
25.00MHz
CARRIER POWER –31.097dBm/15.36MHz ACP-IBW
10dB/DIV
–60
–70
–80
–90
–100
–110
–130
–120
–140
VBW 3kHz
–58.3dBc
–58.0dBc
–37.4dBm
–37.1dBm
–37.1dBm
–36.9dBm
–58.2dBc–58.0dBc
–58.1dBc –58.3dBc
–58.2dBc
–57.9dBc
–58.0dBc
–58.0dBc
C
f
= 2.1 GSPS, I
DAC
= 20 mA, nominal supplies, TA = 25°C, unless otherwise noted.
OUTFS
Figure 39. Typical Single-Carrier WCDMA ACLR Performance at 2.8 GHz,
f
= 2457.6 MSPS (Third Nyquist Zone)
DAC
Figure 40. Typical Four-Carrier WCDMA ACLR Performance at 2.1 GHz,
f
= 2457.6 MSPS (Second Nyquist Zone)
DAC
Figure 41. Typical Four-Carrier WCDMA ACLR Performance at 2.8 GHz,
= 2457.6 MSPS (Third Nyquist Zone)
f
DAC
Rev. | Page 19 of 64
AD9737A/AD9739A Data Sheet
09616-141
10dB/DIV
VBW 2kHz
STOP 1GHz
SWEEP 24.1s (1001pts)
START 50MHz #RES BW 20kHz
FUNCTION VALUE
FUNCTION WIDTHFUNCTION
–10.238dBm
–74.467dB –77.224dB –78.437dB –67.413dB
6MHz 6MHz 6MHz 6MHz 6MHz
BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER
(Δ) (Δ) (Δ) (Δ)
(Δ) (Δ) (Δ) (Δ)
(Δ) (Δ) (Δ) (Δ)
Y –10.238dBm
–74.467dB –77.224dB –78.437dB –67.413dB
f f f f f
1 1 1 1 1
1 2 3 4 5
X
N
Δ1 Δ1 Δ1 Δ1
MODEMKR SCLTRC
200.10MHz
199.50MHz
399.95MHz
599.45MHz
413.25MHz
–30
–40
–50
–60
–70
–80
–90
–100
–110
4Δ1
1
2Δ1
3Δ1
5Δ1
Figure 42. Low Band Wideband ACLR
09616-142
10dB/DIV
VBW 2kHz
STOP 1GHz
SWEEP 24.1s (1001pts)
START 50MHz #RES BW 20kHz
FUNCTION VALUE
FUNCTION WIDTHFUNCTION
–11.538dBm
–74.399dB –74.344dB –68.472dB –66.197dB
6MHz 6MHz 6MHz 6MHz 6MHz
BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER
(Δ) (Δ) (Δ) (Δ)
(Δ) (Δ) (Δ) (Δ)
(Δ) (Δ) (Δ) (Δ)
Y –11.538dBm
–74.421dB –76.294dB –68.472dB –66.156dB
f f f f f
1 1 1 1 1
1 2 3 4 5
X
N
Δ1 Δ1 Δ1 Δ1
MODEMKR SCLTRC
550.65MHz –487.35MHz
125.40MHz
253.65MHz
62.70MHz
–30
–40
–50
–60
–70
–80
–90
–100
–110
3Δ1
2Δ1
1
4Δ1
5Δ1
Figure 43. Mid Band Wideband ACLR
09616-143
10dB/DIV
VBW 2kHz
STOP 1GHz
SWEEP 24.1s (1001pts)
START
50MHz
#RES BW 20kHz
FUNCTION VALUE
FUNCTION WIDTHFUNCTION
–14.446dBm
–60.856dB –66.013dB –68.697dB –63.533dB –68.162dB
6MHz 6MHz 6MHz 6MHz 6MHz 6MHz
BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER BAND POWER
(Δ) (Δ) (Δ) (Δ) (Δ)
(Δ) (Δ) (Δ) (Δ) (Δ)
(Δ) (Δ) (Δ) (Δ) (Δ)
Y –14.418dBm
–60.856dB –66.000dB –68.751dB –63.533dB –66.162dB
f f f f f f
1 1 1 1 1 1
1 2 3 4 5 6
X
N
Δ1 Δ1 Δ1 Δ1 Δ1
MODEMKR SCLTRC
948.70MHz –393.30MHz –553.85MHz –612.75MHz –335.35MHz –57.95MHz
–30
–40
–50
–60
–70
–80
–90
–100
–110
3Δ1
5Δ1
4Δ1
2Δ1
6Δ1
1
Figure 44. High Band Wideband ACLR
09616-144
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
CENTER 200MHz #RES BW 30kHz
UPPER
FILTER OFF OFF OFF OFF OFF
dBc –57.47 –79.87 –78.96 –78.69 –78.68
dBc –58.34 –79.27 –78.44 –78.59 –78.41
dBm –67.70 –90.10 –89.19 –88.92 –88.90
LOWER
dBm –68.57 –89.50 –88.66 –88.82 –88.63
INTEG B W
750.0kHz
5.250MHz
6.000MHz
6.000MHz
6.000MHz
OFFSET FREQ
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
CARRIER POWER – 1 0 .226dBm/6MHz ACP-IBW
10dB/DIV
–30
–40
–50
–60
–70
–80
–90
–100
–110
–78.4dBc
–78.6dBc –78.4dBc
–79.3dBc –10.2dBm
–79.9dBc –79.0dBc
–78.7dBc–78.7dBc
Figure 45. Low Band Narrow-Band ACLR
09616-145
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
CENTER 550MHz #RES BW 30kHz
UPPER
FILTER OFF OFF OFF OFF OFF
dBc –60.92 –74.14 –74.68 –74.91 –75.34
dBc –59.37 –74.02 –74.53 –75.00 –75.97
dBm –73.03 –86.25 –86.79 –87.01 –87.44
LOWER
dBm –71.48 –86.12 –86.63 –87.11 –88.08
INTEG B W
750.0kHz
5.250MHz
6.000MHz
6.000MHz
6.000MHz
OFFSET FREQ
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
CARRIER POWER – 1 2 .104dBm/6MHz ACP-IBW
10dB/DIV
–30
–40
–50
–60
–70
–80
–90
–100
–110
–76.0dBc –75.0dBc –74.5dBc –74.0dBc –12.1dBm –74.1dBc –74.7dBc –75.3dBc–78.9dBc
Figure 46. Mid Band Narrow-Band ACLR
09616-146
SPAN 54MHz
SWEEP 1.49s
VBW 3kHz
CENTER 950MHz #RES BW 30kHz
UPPER
FILTER OFF OFF OFF OFF OFF
dBc –61.30 –69.39 –70.50 –71.02 –71.75
dBc –57.84 –69.02 –70.01 –70.89 –71.94
dBm –74.89 –82.98 –84.09 –84.61 –85.34
LOWER
dBm –71.43 –82.61 –83.60 –84.48 –85.53
INTEG B W
750.0kHz
5.250MHz
6.000MHz
6.000MHz
6.000MHz
OFFSET FREQ
3.375MHz
6.375MHz
12.00MHz
18.00MHz
24.00MHz
CARRIER POWER – 1 3 .589dBm/6MHz ACP-IBW
10dB/DIV
–30
–40
–50
–60
–70
–80
–90
–100
–110
–71.9dBc –70.9dBc –70.0dBc
–69.0dBc –13.6dBm –69.4dBc –70.5dBc –71.7dBc–71.0dBc
Figure 47. High Band Narrow-Band ACLR
C

ONE-CARRIER DOCSIS PERFORMANCE (NORMAL MODE)

I
= 20 mA, f
OUTFS
= 2.4576 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
DAC
Rev. | Page 20 of 64
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