1.25 GHz to 3.0 GHz in mix-mode
Industry leading single/multicarrier IF or RF synthesis
Dual-port LVDS data interface
Up to 1.25 GSPS operation
Source synchronous DDR clocking
Pin compatible with the AD9739
Programmable output current: 8.7 mA to 31.7 mA
Low power: 1.1 W at 2.5 GSPS
APPLICATIONS
Broadband communications systems
DOCSIS CMTS systems
Military jammers
Instrumentation, automatic test equipment
Radar, avionics
11-/14-Bit, 2.5 GSPS,
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
GENERAL DESCRIPTION
The AD9737A/AD9739A are 11-bit and 14-bit, 2.5 GSPS high
performance RF DACs that are capable of synthesizing wideband
signals from dc up to 3 GHz. The AD9737A/AD9739A are pin
and functionally compatible with the AD9739 with the
exception that the AD9737A/AD9739A do not support
synchronization or RZ mode, and are specified to operate
between 1.6 GSPS and 2.5 GSPS.
By elimination of the synchronization circuitry, some nonideal
artifacts such as images and discrete clock spurs remain stationary
on the AD9737A/AD9739A between power-up cycles, thus
allowing for possible system calibration. AC linearity and noise
performance remain the same between the AD9739 and the
AD9737A/AD9739A.
The inclusion of on-chip controllers simplifies system integration.
A dual-port, source synchronous, LVDS interface simplifies the
digital interface with existing FGPA/ASIC technology. On-chip
controllers are used to manage external and internal clock domain
variations over temperature to ensure reliable data transfer from
the host to the DAC core. A serial peripheral interface (SPI) is
used for device configuration as well as readback of status
registers.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
The AD9737A/AD9739A are manufactured on a 0.18 µm
CMOS process and operate from 1.8 V and 3.3 V supplies.
They are supplied in a 160-ball chip scale ball grid array for
reduced package parasitics.
PRODUCT HIGHLIGHTS
1. Ability to synthesize high quality wideband signals with
bandwidths of up to 1.25 GHz in the first or second
Nyquist zone.
2. A proprietary quad-switch DAC architecture provides
exceptional ac linearity performance while enabling mixmode operation.
3. A dual-port, double data rate, LVDS interface supports the
maximum conversion rate of 2500 MSPS.
4. On-chip controllers manage external and internal clock
domain skews.
5. Programmable differential current output with an 8.66 mA
to 31.66 mA range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
AD9737A/AD9739A Data Sheet
C
TABLE OF CONTENTS
Features .............................................................................................. 1
Added SPI Port Configuration and Software Reset Section,
Power-Down LVDS Interface and TxDAC Section, Controller
Clock Disable Section, and Table 11 to Table 13 ........................ 43
Added Interrupt Request (IRQ) Enable/Status Section, TxDAC
Full-Scale Current Setting (I
) and Sleep Section, TxDAC
OUTFS
Quad-Switch Mode of Operation Section, DCI Phase
Alignment Status Section, Data Receiver Controller
Configuration Section, and Table 14 to Table 18 ........................ 44
Added Data Receiver Controller_Data Sample Delay Value
Section, Data Receiver Controller_DCI Delay Value/Window
and Phase Rotation Section, Data Receiver Controller_Delay
Line Status Section, Data Receiver Controller Lock/Tracking
Status Section, and Table 19 to Table 22 ...................................... 45
Added CLK Input Common Mode Section, and Mu
Controller Configuration and Status Section, and Table 23
and Table 24 ..................................................................................... 46
Added Part ID Section, and Table 25 ........................................... 47
Changes to LVDS Data Port Interface Section ............................ 49
Changes to Data Receiver Controller Initialization
divided by the minimum required interpolation factor. For the AD9737A/AD9739A, the minimum interpolation factor
DAC
, adjusted, = 2500 MSPS.
DAC
= 20 mA, f
OUTFS
= 2400 MSPS, unless otherwise noted.
DAC
Rev. | Page 7 of 64
AD9737A/AD9739A Data Sheet
VDD33 to VSS
−0.3 V to +3.6 V
DACCLK_P, DACCLK_N to VSSC
−0.3 V to VDDC + 0.18 V
C
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
VDDA to VSSA −0.3 V to +3.6 V
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
VDD to VSS −0.3 V to +1.98 V
VDDC to VSSC −0.3 V to +1.98 V
VSSA to VSS −0.3 V to +0.3 V
VSSA to VSSC −0.3 V to +0.3 V
VSS to VSSC −0.3 V to +0.3 V
DCI, DCO to VSS −0.3 V to VDD33 + 0.3 V
LVDS Data Inputs to VSS −0.3 V to VDD33 + 0.3 V
IOUTP, IOUTN to VSSA −1.0 V to VDDA + 0.3 V
I120, VREF to VSSA −0.3 V to VDDA + 0.3 V
IRQ, CS, SCLK, SDO, SDIO, RESET to VSS
Junction Temperature 150°C
Storage Temperature Range −65°C to +150°C
−0.3 V to VDD33 + 0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 6. Thermal Resistance
Package Type θJA θJC Unit
160-Ball CSP_BGA 31.2 7.0 °C/W1
1
With no airflow movement.
ESD CAUTION
Rev. | Page 8 of 64
Data Sheet AD9737A/AD9739A
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1413121110876321954
1413121110876321954
A
B
C
D
E
F
G
H
J
K
L
M
N
P
VDDA, 3.3V, ANALOG S UPPLY
VSSA, ANALOG SUPPLY GROUND
VSSA SHIELD, ANAL OG SUPPLY GROUND SHIELD
AD9737A/AD9739A
Figure 2. Analog Supply Pins (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
VDD, 1.8V, DIGITAL SUPPLY
VSS DIGITAL SUPPLY GROUND
VDD33, 3.3V DIGITAL SUPPLY
AD9737A/AD9739A
Figure 3. Digital Supply Pins (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
VDDC, 1.8V, CLOCK S UP PLY
VSSC, CLOCK SUPPLY GROUND
09616-002
1413121110876321954
DB1[0:10]P
DB0[0:10]P N
DB0[0:10]N P
Figure 4. Digital LVDS Clock Supply Pins (Top View)
A
B
CDACCLK_N
DDACCLK_P
E
F
G
H
J
K
L
MDB1[0:10]N
DIFFERE NTIAL I NP UT SIGNAL (CLOCK OR DATA)
AD9737A/AD9739A
AD9737A
1413121110876321954
09616-004
DCO_P/_N
DCI_P/_N
09616-036
Figure 5. AD9737A Digital LVDS Input, Clock I/O (Top View)
1413121110876321954
09616-003
DACCLK_N
DACCLK_P
DB1[0:13]P
DB1[0:13]N
DB0[0:13]P
DB0[0:13]N
A
B
C
D
E
F
G
H
J
K
L
M
N
P
AD9739A
DCO_P/_N
DCI_P/_N
Rev. C | Page 9 of 64
DIFFERENTIAL INPUT SIGNAL (CLOCK OR DATA)
Figure 6. AD9739A Digital LVDS Input, Clock I/O (Top View)
F14 RESET Reset Input. Active high. Tie to VSS if unused.
G13
H13 SCLK Serial Port Clock Input.
H14 SDO Serial Port Data Output.
J3, J4, J11, J12 VDD33 3.3 V Digital Supply Input.
G1, G2, G3, G4, G11, G12 VDD 1.8 V Digital Supply Input.
H1, H2, H3, H4, H11, H12, K3, K4, K11, K12 VSS Digital Supply Ground.
J1, J2 NC
K1, K2 NC
J13, J14 DCO_P/DCO_N Positive/Negative Data Clock Output (DCO).
Figure 7. AD9737A Analog I/O and SPI Control Pins (Top View)
VSSC Clock Supply Ground.
VSSA Shield Analog Supply Ground Shield. Tie to VSSA at the DAC.
Nominal 1.2 V Reference. Tie to analog ground via a 10 kΩ
resistor to generate a 120 µA reference current.
Voltage Reference Input/Output. Decouple to VSSA with a 1 nF
capacitor.
Interrupt Request Open Drain Output. Active high. Pull up to
VDD33 with a 10 kΩ resistor.
CS
Serial Port Enable Input.
Differential resistor of 200 Ω exists between J1 and J2. Do not
Rev. | Page 10 of 64
connect to this pin.
Differential resistor of 100 Ω exists between K1 and K2. Do not
connect to this pin.
Data Sheet AD9737A/AD9739A
Pin No. Mnemonic Description
L1, M1 NC, NC Do not connect to this pin.
L2, M2 NC, NC Do not connect to this pin.
L3, M3 NC, NC Do not connect to this pin.
L4, M4 DB1[0]P/DB1[0]N Port 1 Positive/Negative Data Input Bit 0.
L5, M5 DB1[1]P/DB1[1]N Port 1 Positive/Negative Data Input Bit 1.
L6, M6 DB1[2]P/DB1[2]N Port 1 Positive/Negative Data Input Bit 2.
L7, M7 DB1[3]P/DB1[3]N Port 1 Positive/Negative Data Input Bit 3.
L8, M8 DB1[4]P/DB1[4]N Port 1 Positive/Negative Data Input Bit 4.
L9, M9 DB1[5]P/DB1[5]N Port 1 Positive/Negative Data Input Bit 5.
L10, M10 DB1[6]P/DB1[6]N Port 1 Positive/Negative Data Input Bit 6.
L11, M11 DB1[7]P/DB1[7]N Port 1 Positive/Negative Data Input Bit 7.
L12, M12 DB1[8]P/DB1[8]N Port 1 Positive/Negative Data Input Bit 8.
L13, M13 DB1[9]P/DB1[9]N Port 1 Positive/Negative Data Input Bit 9.
L14, M14 DB1[10]P/DB1[10]N Port 1 Positive/Negative Data Input Bit 10.
N1, P1 NC, NC Do not connect to this pin.
N2, P2 NC, NC Do not connect to this pin.
N3, P3 NC, NC Do not connect to this pin.
N4, P4 DB0[0]P/DB0[0]N Port 0 Positive/Negative Data Input Bit 0.
N5, P5 DB0[1]P/DB0[1]N Port 0 Positive/Negative Data Input Bit 1.
N6, P6 DB0[2]P/DB0[2]N Port 0 Positive/Negative Data Input Bit 2.
N7, P7 DB0[3]P/DB0[3]N Port 0 Positive/Negative Data Input Bit 3.
N8, P8 DB0[4]P/DB0[4]N Port 0 Positive/Negative Data Input Bit 4.
N9, P9 DB0[5]P/DB0[5]N Port 0 Positive/Negative Data Input Bit 5.
N10, P10 DB0[6]P/DB0[6]N Port 0 Positive/Negative Data Input Bit 6.
N11, P11 DB0[7]P/DB0[7]N Port 0 Positive/Negative Data Input Bit 7.
N12, P12 DB0[8]P/DB0[8]N Port 0 Positive/Negative Data Input Bit 8.
N13, P13 DB0[9]P/DB0[9]N Port 0 Positive/Negative Data Input Bit 9.
N14, P14 DB0[10]P/DB0[10]N Port 0 Positive/Negative Data Input Bit 10.
Rev. C | Page 11 of 64
AD9737A/AD9739A Data Sheet
IOUTN8IOUTP
7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Figure 8. AD9739A Analog I/O and SPI Control Pins (Top View)
VSSA Shield Analog Supply Ground Shield. Tie to VSSA at the DAC.
E13, E14, F1, F2, F3, F4, F11, F12
A14 NC Do not connect to this pin.
A7, B7, C7, D7 IOUTN DAC Negative Current Output Source.
A8, B8, C8, D8 IOUTP DAC Positive Current Output Source.
B14 I120
Nominal 1.2 V Reference. Tie to analog ground via a 10 kΩ
resistor to generate a 120 μA reference current.
C14 VREF
Voltage Reference Input/Output. Decouple to VSSA with a 1 nF
capacitor.
D14 NC Factory Test Pin. Do not connect to this pin.
C3, D3 DACCLK_N/DACCLK_P Negative/Positive DAC Clock Input (DACCLK).
F13 IRQ
Interrupt Request Open Drain Output. Active high. Pull up to
VDD33 with a 10 kΩ resistor.
F14 RESET Reset Input. Active high. Tie to VSS if unused.
G13
CS
Serial Port Enable Input.
G14 SDIO Serial Port Data Input/Output.
H13 SCLK Serial Port Clock Input.
H14 SDO Serial Port Data Output.
J3, J4, J11, J12 VDD33 3.3 V Digital Supply Input.
G1, G2, G3, G4, G11, G12 VDD 1.8 V Digital Supply Input.
H1, H2, H3, H4, H11, H12, K3, K4, K11, K12 VSS Digital Supply Ground.
J1, J2 NC
Differential resistor of 200 Ω exists between J1 and J2. Do not
connect to this pin.
K1, K2 NC
Differential resistor of 100 Ω exists between K1 and K2. Do not
connect to this pin.
J13, J14 DCO_P/DCO_N Positive/Negative Data Clock Output (DCO).
K13, K14 DCI_P/DCI_N Positive/Negative Data Clock Input (DCI).
Rev. C | Page 12 of 64
Data Sheet AD9737A/AD9739A
Pin No. Mnemonic Description
L1, M1 DB1[0]P/DB1[0]N Port 1 Positive/Negative Data Input Bit 0.
L2, M2 DB1[1]P/DB1[1]N Port 1 Positive/Negative Data Input Bit 1.
L3, M3 DB1[2]P/DB1[2]N Port 1 Positive/Negative Data Input Bit 2.
L4, M4 DB1[3]P/DB1[3]N Port 1 Positive/Negative Data Input Bit 3.
L5, M5 DB1[4]P/DB1[4]N Port 1 Positive/Negative Data Input Bit 4.
L6, M6 DB1[5]P/DB1[5]N Port 1 Positive/Negative Data Input Bit 5.
L7, M7 DB1[6]P/DB1[6]N Port 1 Positive/Negative Data Input Bit 6.
L8, M8 DB1[7]P/DB1[7]N Port 1 Positive/Negative Data Input Bit 7.
L9, M9 DB1[8]P/DB1[8]N Port 1 Positive/Negative Data Input Bit 8.
L10, M10 DB1[9]P/DB1[9]N Port 1 Positive/Negative Data Input Bit 9.
L11, M11 DB1[10]P/DB1[10]N Port 1 Positive/Negative Data Input Bit 10.
L12, M12 DB1[11]P/DB1[11]N Port 1 Positive/Negative Data Input Bit 11.
L13, M13 DB1[12]P/DB1[12]N Port 1 Positive/Negative Data Input Bit 12.
L14, M14 DB1[13]P/DB1[13]N Port 1 Positive/Negative Data Input Bit 13.
N1, P1 DB0[0]P/DB0[0]N Port 0 Positive/Negative Data Input Bit 0.
N2, P2 DB0[1]P/DB0[1]N Port 0 Positive/Negative Data Input Bit 1.
N3, P3 DB0[2]P/DB0[2]N Port 0 Positive/Negative Data Input Bit 2.
N4, P4 DB0[3]P/DB0[3]N Port 0 Positive/Negative Data Input Bit 3.
N5, P5 DB0[4]P/DB0[4]N Port 0 Positive/Negative Data Input Bit 4.
N6, P6 DB0[5]P/DB0[5]N Port 0 Positive/Negative Data Input Bit 5.
N7, P7 DB0[6]P/DB0[6]N Port 0 Positive/Negative Data Input Bit 6.
N8, P8 DB0[7]P/DB0[7]N Port 0 Positive/Negative Data Input Bit 7.
N9, P9 DB0[8]P/DB0[8]N Port 0 Positive/Negative Data Input Bit 8.
N10, P10 DB0[9]P/DB0[9]N Port 0 Positive/Negative Data Input Bit 9.
N11, P11 DB0[10]P/DB0[10]N Port 0 Positive/Negative Data Input Bit 10.
N12, P12 DB0[11]P/DB0[11]N Port 0 Positive/Negative Data Input Bit 11.
N13, P13 DB0[12]P/DB0[12]N Port 0 Positive/Negative Data Input Bit 12.
N14, P14 DB0[13]P/DB0[13]N Port 0 Positive/Negative Data Input Bit 13.