Analog Devices AD9736 35 34 prj Datasheet

14/12/10-Bit, 1200 MSPS

D/A Converters

Preliminary Technical Data AD9736/AD9735/AD9734

FEATURES

• 1.8/3.3 V Dual Supply Operation

• AD9736 SFDR > 53 dBc to f

• AD9736 IMD > 65 dBc to f

= 600 MHz

OUT

= 600 MHz

OUT

• AD9736 DNL = ± 1.0 LSB

• AD9736 INL = ± 2.0 LSB

• Low power: 380 mW (I

= 20 mA; f

OUTFS

= 330 MHz)

OUT

• LVDS data interface with on-chip 100 Ω terminations

• Analog Output: Adjustable 10-30mA (RL=25 Ω to 50 Ω)

• On-Chip 1.2 V Reference

• 160 pin BGA Package

APPLICATIONS

• Instrumentation

• Automatic Test Equipment

• RADAR

• Avionics

• Wideband Communications Systems:

Point-to-Point Wireless LMDS PA Linearization

PRODUCT DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

CLK-

CLK+

14,12,10-Bit

DAC

Reference

Current

RSET

C3

S2

SDO CSB

SCLK

DATACLK_OUT+

DATACLK_OUT-

DATACLK_IN+

DATACLK_IN-

DB[13:0]+

DB[13:0]-

RESET

S1 S2 S3

SDI

SPI

LVDS

Driver

LVDSReceiver

C2 C1 S1

Controller

Clock Distribution

Synchronization

Figure 1. Functional Block Diagram

C1 C2 C3

S3

2X

Bandgap

VREF

PRODUCT HIGHLIGHTS

Ultra-low Noise and Intermodulation Distortion (IMD) enable high quality synthesis of wideband signals at intermediate frequencies up to 600 MHz.

IOUTA

IOUTB

The AD9736, AD9735, and AD9734 are high performance, high frequency DACs that provide sample rates of up to 1200 MSPS, permitting multi-carrier generation up to their Nyquist frequency. The AD9736 is the 14 bit member of the family, while the AD9735 and the AD9734 are the 12 and 10 bit members, respectively. They include a serial peripheral interface (SPI) port that provides for programming many internal parameters and also enables read-back of status registers. They use a reduced specification LVDS interface to minimize data interface noise that may degrade performance. The output current can be programmed over a range of 10mA to 30mA. The AD9736 family is manufactured on a 0.18µm CMOS process and operates from 1.8V and 3.3V supplies for a total power consumption of 380mW in bypass mode. It is supplied in a 160 pin BGA package for reduced package parasitics.

Rev. PrJ 9/7/2004

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.

Double Data Rate (DDR) LVDS data receivers support the maximum conversion rate of 1200 MSPS.

Direct pin programmability of basic functions or SPI port access for complete control of all AD9736 family functions.

Manufactured on a CMOS process, the AD9736 family uses a proprietary switching technique that enhances dynamic performance.

The current output(s) of the AD9736 family can be easily configured for various single-ended or differential circuit topologies.

AD9736/AD9735/AD9734 Preliminary Technical Data

TABLE OF CONTENTS

AD9736/AD9735/AD9734—Specifications ........................................3

DC SPECIFICATIONS ......................................................................3

DIGITAL SPECIFICATIONS............................................................4

AC SPECIFICATIONS....................................................................... 5

EXPLANATION OF TEST LEVELS................................................ 5

PIN FUNCTION DESCRIPTIONS...................................................... 6

PIN CONFIGURATION........................................................................ 7

PACKAGE OUTLINE.............................................................................9

Ordering Guide ...................................................................................9

TYPICAL PERFORMANCE CHARACTERISTICS........................10

SPI REGISTER MAP ............................................................................14

SPI REGISTER DESCRIPTIONS........................................................15

General Description ..............................................................................19

Serial Peripheral Interface................................................................19

AD9736 Data Interface Controllers ....................................................22

AD9736 LVDS Sample Logic...........................................................23

AD9736 SYNC Logic and Controller.............................................25

AD9736 Digital Built-In Self Test........................................................27

AD9736 Analog Control Register .......................................................28

Voltage Reference...................................................................................29

Applications Information .....................................................................30

AD9736 Evaluation Board Schematics...............................................31

AD9736 Evaluation Board PCB Layout..............................................36

REVISION HISTORY

Revision PrA: Initial Version

Revision PrB: Updated data based on initial evaluation results

Revision PrC: Updated data for web display and ongoing evaluation results

Revision PrD: Added SPI port information

Revision PrE: Cleaned up SPI port tables, added AD9736 rev A evaluation board schematics

Revision PrF: Added BGA Package Outline Drawing

Revision PrG: Added Package Pinout

Revision PrH: Added SPI Port Description

Revision PrI: Edits for readability and clarity, Added Idd typical values and plots, Updated SPI register tables, Added LVDS and SYNC controller

sections, Added pin function table, Added BIST description, Added Analog control section, Added Vref section, Updated eval board schematic and PCB layout

Revision PrJ: Update BIST information, Update SPI definition to include SCLK edge change for read operation, Add SPI timing, Annotate

schematic to show component values for output circuit, Update ACLR plots, Add PCB fabrication details.

Rev. PrJ | Page 2 of 42

Preliminary Technical Data AD9736/AD9735/AD9734

AD9736/AD9735/AD9734—SPECIFICATIONS1

DC SPECIFICATIONS

(VDDA33 = VDDD33 = 3.3 V, VDDA18 = VDDD18 = VDDCLK = 1.8 V, MAXIMUM SAMPLE RATE, FS = 20MA, 1X MODE, 25 OHM 1% BALANCED LOAD, UNLESS OTHERWISE NOTED)

AD9736 AD9735 AD9734

Parameter Temp Test Level

RESOLUTION 14 12 10 Bits

ACCURACY

ANALOG OUTPUTS

TEMPERATURE DRIFT

REFERENCE

ANALOG SUPPLY VOLTAGES

DIGITAL SUPPLY VOLTAGES

POWER CONSUMPTION

SUPPLY CURRENTS 1X Mode

SUPPLY CURRENTS 2x Mode, Interpoation Enabled

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

Offset Error TBD TBD TBD % FSR

Gain Error (With Internal Reference)

Gain Error (Without Internal Reference)

Full Scale Output Current 10 20 30 10 20 30 10 20 30 mA

Output Compliance Range 1.0 1.0 1.0 V

Output Resistance TBD TBD TBD

Output Capacitance TBD TBD TBD pF

Offset TBD TBD TBD

Gain TBD TBD TBD

Reference Voltage TBD TBD TBD

Internal Reference Voltage 1.2 1.2 1.2 V

Output Current 100 100 100 nA

VDDA33 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 V

VDDA18 1.70 1.8 1.90 1.70 1.8 1.90 1.70 1.8 1.90 V

VDDD33 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 V

VDDD18 1.70 1.8 1.90 1.70 1.8 1.90 1.70 1.8 1.90 V

Bypass Mode 380 380 380 mW

FIR Interpolation Filter Enabled 550 550 550 mW

Standby Power TBD TBD TBD mW

IDDA33 25 TBD TBD mA

IDDA18 47 TBD TBD mA

IDDD33 10 TBD TBD mA

IDDD18 122 TBD TBD mA

IDDA33 25 TBD TBD mA

IDDA18 47 TBD TBD mA

IDDD33 10 TBD TBD mA

IDDD18 234 TBD TBD mA

Min Typ Max Min Typ Max Min Typ Max

TBD TBD LSB

± 2.0

TBD TBD LSB

± 1.0

± 0.5 ± 0.5

Table 1: DC Specifications

Unit

% FSR

kΩ

ppm/°C ppm/°C ppm/°C

1

Specifications subject to change without notice

Rev. PrJ | Page 3 of 42

AD9736/AD9735/AD9734 Preliminary Technical Data

DIGITAL SPECIFICATIONS1

(VDDA33 = VDDD33 = 3.3 V, VDDA18 = VDDD18 = VDDCLK = 1.8 V, MAXIMUM SAMPLE RATE, FS = 20MA, 1X MODE, 25 OHM 1% BALANCED LOAD, UNLESS OTHERWISE NOTED)

LVDS DATA INPUTS (DB[13:0]+, DB[13:0]-) DB+ = Via, DB- = Vib

LVDS CLOCK INPUT (DATACLK_IN+, DATACLK_IN-) DATACLK+ = Via, DATACLK- = Vib

LVDS CLOCK OUTPUT (DATACLK_OUT+, DATACLK_ OUT-) DATACLK_OUT+ = Voa, DATACLK_OUT- = Vob 100 ohm termination

DAC CLOCK INPUT (CLK+, CLK-)

SERIAL PERIPHERAL INTERFACE

AD9736,35,34 Parameter Temp Test Level

Min Typ Max

Input voltage range, Via or Vib 825 1575 mV Input differential threshold -100 100 mV Input differential hysteresis 20 mV Receiver differential input impedance 80 120

LVDS input rate 1200 MSPS LVDS data Bit Error Rate TBD Err/Bit Input voltage range, Via or Vib 825 1575 mV Input differential threshold -100 100 mV Input differential hysteresis 20 mV Receiver differential input impedance 80 120

Maximum Clock Rate 600 MHz Output voltage high, Voa or Vob 1375 mV Output voltage low, Voa or Vob 1025 mV Output differential voltage 150 200 250 mV Output offset voltage 1150 1250 mV Output impedance, single ended 80 100 120

Ro mismatch between A & B 10 % Change in |Vod| between ‘0’ and ‘1’ 25 mV Change in Vos between ‘0’ and ‘1’ 25 mV Output current – Driver shorted to ground 20 mA Output current – Drivers shorted together 4 mA Power-off output leakage TBD mA Maximum Clock Rate 600 MHz Differential peak-to-peak Voltage 800 mV Common Mode Voltage 400 mV Maximum Clock Rate 1200 MHz Maximum Clock Rate (SCLK, 1/t Minimum pulse width high, t Minimum pulse width low, t Minimum SDIO and CSB to SCLK setup, tDS 10 ns Minimum SCLK to SDIO hold, tDH 5 ns Maximum SCLK to valid SDIO and SDO, tDV 20 ns Minimum SCLK to invalid SDIO and SDO, t

) 20 MHz

SCLK

20 ns

PWH

20 ns

PWL

5 ns

DNV

Table 2: Digital Specifications

Unit

Ω

1

LVDS Drivers and Receivers are compliant to the IEEE-1596 Reduced Range Link, unless otherwise noted

Rev. PrJ | Page 4 of 42

Preliminary Technical Data AD9736/AD9735/AD9734

AC SPECIFICATIONS

(VDDA33 = VDDD33 = 3.3 V, VDDA18 = VDDD18 = VDDCLK = 1.8 V, MAXIMUM SAMPLE RATE, FS = 20MA, 1X MODE, 25 OHM 1% BALANCED LOAD, UNLESS OTHERWISE NOTED)

AD9736 AD9735 AD9734

Parameter Temp Test Level

DYNAMIC PERFORMANCE

SPURIOUS FREE DYNAMIC RANGE (SFDR)

Two Tone Intermodulation Distortion (IMD)

Noise Spectral Density (NSD)

Maximum Update Rate 1200 1200 1200 MSPS

Output Settling Time (tst) (to 0.025%) TBD TBD TBD ns

Output Rise Time (10% to 90%) TBD TBD TBD ns

Output Fall Time (90% to 10%) TBD TBD TBD ns

Output Noise (IoutFS=20mA) TBD TBD TBD pA/rtHz

f

= 1200 MSPS, f

DAC

f

= 1200 MSPS, f

DAC

f

= 1200 MSPS, f

DAC

f

= 1200 MSPS, f

DAC

f

= 1200 MSPS, f

DAC

f

= 1200 MSPS, f

DAC

f

= 1200 MSPS, f

DAC

f

= 1200 MSPS, f

DAC

f

= 1200 MSPS, f

DAC

f

= 1200 MSPS, f

DAC

f

= 1200 MSPS, f

DAC

f

= 1200 MSPS, f

DAC

= 50 MHz 80 dBc

OUT

= 100 MHz 77 dBc

OUT

= 316 MHz 63 dBc

OUT

= 550 MHz 55 dBc

OUT

= 50 MHz 85 dBc

OUT

= 100 MHz 84 dBc

OUT

= 316 MHz 74 dBc

OUT

= 550 MHz 65 dBc

OUT

= 50 MHz -165 dBm/Hz

OUT

= 100 MHz -164 dBm/Hz

OUT

= 316 MHz -158 dBm/Hz

OUT

= 550 MHz -155 dBm/Hz

OUT

Table 3: AC Specifications

Min Typ Max Min Typ Max Min Typ Max Unit

EXPLANATION OF TEST LEVELS

TEST LEVEL

I 100% production tested.

II 100% production tested at +25°C and guaranteed by design and characterization at specified temperatures.

III Sample Tested Only

IV Parameter is guaranteed by design and characterization testing.

V Parameter is a typical value only.

VI 100% production tested at +25°C and guaranteed by design and characterization for industrial temperature range.

Rev. PrJ | Page 5 of 42

AD9736/AD9735/AD9734 Preliminary Technical Data

PIN FUNCTION DESCRIPTIONS

Pin No. Name Description

A1, A2, A3, B1, B2, B3, C1, C2, C3, D2, D3 VDDC 1.8V, Clock supply A4, A5, A6, A9, A10, A11, B4, B5, B6, B9,

B10, B11, C4, C5, C6, C9, C10, C11, D4, D5, D6, D9, D10, D11

A7, B7, C7, D7 IOUTB DAC negative output, 10mA to 30mA full scale output current A8, B8, C8, D8 IOUTA DAC positive output, 10mA to 30mA full scale output current A12, A13, B12, B13, C12, C13, D12, D13 VDDA 3.3V Analog supply A14, K1 DNC Do Not Connect

B14 I120

C14 VREF

D1, E2, E3, E4, F2, F3, F4, G1, G2, G3, G4 VSSC Clock supply ground

D14 IPTAT

E1, F1 CLK-, CLK+ Negative, Positive DAC clock input (DACCLK) E11, E12, F11, F12, G11, G12 VSSA Analog supply ground shield

E13 IRQ / UNSIGNED

E14 RESET / PD

F13 CSB / 2x See SPI and PIN Mode sections for pin description F14 SDIO / FIFO See SPI and PIN Mode sections for pin description G13 SCLK / FSC0 See SPI and PIN Mode sections for pin description G14 SDO / FSC1 See SPI and PIN Mode sections for pin description H1, H2, H3, H4, H11, H12, H13, H14, J1, J2,

J3, J4, J11, J12, J13, J14 K2, K3, K4, K11, K12, L2, L3, L4, L5, L6, L9,

L10, L11, L12, M3, M4, M5, M6, M9, M10, M11, M12

K13, K14 DB<13> -, + Negative, Positive data input bit 13 (MSB), reduced swing LVDS

L1 PIN_MODE

L7, L8, M7, M8, N7, N8, P7, P8 VDD33 3.3V Digital supply L13, L14 DB<12> -, + Negative, Positive data input bit 12, reduced swing LVDS M2, M1 DB<0> -, + Negative, Positive data input bit 0 (LSB), reduced swing LVDS M13, M14 DB<11> -, + Negative, Positive data input bit 11, reduced swing LVDS N1, P1 DB<1> -, + Negative, Positive data input bit 1, reduced swing LVDS N2, P2 DB<2> -, + Negative, Positive data input bit 2, reduced swing LVDS N3, P3 DB<3> -, + Negative, Positive data input bit 3, reduced swing LVDS N4, P4 DB<4> -, + Negative, Positive data input bit 4, reduced swing LVDS N5, P5 DB<5> -, + Negative, Positive data input bit 5, reduced swing LVDS N6, P6 DATACLK_OUT -, + Negative, Positive output clock, reduced swing LVDS N9, P9 DATACLK_IN -, + Negative, Positive data input clock, reduced swing LVDS N10, P10 DB<6> -, + Negative, Positive data input bit 6, reduced swing LVDS N11, P11 DB<7> -, + Negative, Positive data input bit 7, reduced swing LVDS N12, P12 DB<8> -, + Negative, Positive data input bit 8, reduced swing LVDS N13, P13 DB<9> -, + Negative, Positive data input bit 9, reduced swing LVDS N14, P14 DB<10> -, + Negative, Positive data input bit 10, reduced swing LVDS

VSSA Analog supply ground

Nominal 1.2V reference tied to analog ground via 10kohm resistor to generate a 120uA reference current

Bandgap voltage reference I/O, tie to analog ground via 1nF capacitor, output impedance approximately 5kohms

Factory test, output current proportional to absolute temperature, approximately 10uA at 25C with approximately 20nA/C slope

If PIN_MODE = 0, IRQ: Active low open-drain interrupt request output, pull up to VDD3.3 with 10kohm resistor If PIN_MODE = 1, UNSIGNED: Digital input pin where 0 = two’s complement input data format, 1 = unsigned

If PIN_MODE = 0, RESET: 1 resets the AD9736 If PIN_MODE = 1, PD: 1 puts the AD9736 in the power down state

VDD 1.8V Digital supply

VSS Digital supply ground

0, SPI Mode, SPI enabled 1, PIN Mode, SPI disabled, direct pin control

Rev. PrJ | Page 6 of 42

Preliminary Technical Data AD9736/AD9735/AD9734

S

PIN CONFIGURATION

1234567891011121314

A B C D

E

F G H

J

K

L

M

N P

1 2 3 4 5 6 7 8 9 10 11 12 13 14

A

B C D

E

F G H

J K L

M

N

P

VDDA, 3.3V, Analog Supply VSSA, Analog Supply Ground

VSSA, Analog Supply Ground Shield

Figure 2. AD9736 Analog Supply Pins ( TOP view)

1234567891011121314

A B C D

E

F G H

J

K

L

M

N P

VDD, 1.8V Digital Supply VDD33, 3.3V Digital Supply VSS Digital Supply Ground

Figure 4. AD9736 Digital Supply Pins ( TOP view)

VDDC, 1.8V, Clock Supply VSSC, Clock Supply Ground

CLKN

LVDS0 (LSB)

Figure 3. AD9736 Clock Supply Pins ( TOP view)

1 2 3 4 5 6 7 8 9 10 11 12 13 14

A B C D

E F

CLKP

G H

J

K

L

M

N P

LVDS

LVDS1

LVDS3

LVDS4

LVDS5

LVDSCLKP,N OUT

DCLKP,N IN

LVDS6

LVDS7

LVDS8

LVDS9

LVDS10

LVDS13 (M LVDS12 LVDS11

Figure 5. AD9736 Digital LVDS Inputs, Clock I/O (TOP view)

Rev. PrJ | Page 7 of 42

AD9736/AD9735/AD9734 Preliminary Technical Data

IOUTN

IOUTP

PIN_MODE=0,

I120 VREF IPTAT

UNSIGNED

SPI ENABLED

IRQ

CSB

SCLK

PIN_MODE=1, SPI DISABLED

2x

FSCO

RESET SDIO SDO

PD FIFO FSC1

PIN_MODE

1 2 3 4 5 6 7 8 9 1011121314

A

B C

D

E

F G H

J K L

M

N

P

Figure 6. AD9736 Analog I/O and SPI Control Pins ( TOP view)

Rev. PrJ | Page 8 of 42

Preliminary Technical Data AD9736/AD9735/AD9734

a

PACKAGE OUTLINE

160-Lead Chip Scale Ball Grid Array [CSPBGA]

(BC-160)

Dimensions shown in millimeters

A1 CORNER INDEX AREA

95

BOTTOM

VIEW

0.80 BSC

DETAIL A

4

321

A B C D E F G H J K L M N P

1.00

0.85

1.40 MAX

12.00

BSC SQ

BALL A1 INDICATOR

TOP VIEW

DETAIL A

10.40 BSC

1413121110 876

0.25 MIN

0.55

0.50

0.45 BALL DIAMETER

COMPLIANT WITH JEDEC STANDARDS MO-205-AE.

SEATING PLANE

0.12 MAX COPLANARITY

Figure 7. AD9736 BGA Package Outline Drawing

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Ordering Guide

Model Temperature Range Description

AD9736BBC

-40°C to +85°C (Ambient)

AD9736-EB 25°C (Ambient) Evaluation Board

160-Lead Chip Scale BGA

Table 4: Ordering Guide

Rev. PrJ | Page 9 of 42

AD9736/AD9735/AD9734 Preliminary Technical Data

TYPICAL PERFORMANCE CHARACTERISTICS

1

0.8

0.6

0.4

0.2

0

Error - LSB

-0.2

-0.4

-0.6

-0.8

-1 0 2048 4096 6144 8192 10240 12288 14336 16384

Code

Figure 8. AD9736, Typical INL

0.5

0.3

0.1

-0.1

Error - LSB

-0.3

-0.5

-0.7 0 2048 4096 6144 8192 10240 12288 14336 16384

Code

Figure 9. AD9736, Typical DNL

3rd Order IM D With Respect t o Fout ( 20 mA FS)

800MSPS 1GSPS 1.2GSPS

90

85

80

75

70

IMD - [dBc]

65

60

55

50

0 50 100 150 200 250 300 350 400 450 500 550 600

Fout - [ MHz ]

Figure 10. AD9736, 3rd Order IMD vs. Fout and Sample Rate

Rev. PrJ | Page 10 of 42

Preliminary Technical Data AD9736/AD9735/AD9734

NSD Comparison With 1-Tone and 8-Tones at 1.2GSPS

1 Tone 8 Tones

-150

-152

-154

-156

-158

-160

-162

NSD - dBm / Hz

-164

-166

-168

-170 0 100 200 300 400 500 600 700

Figure 11. AD9736, Noise Spectral Density (NSD) vs. Fout at 1.2GSPS

In- Band SFDR With Respect to Fout (2 0mA FS)

Fout - Mhz

90 85 80 75 70 65

SFDR - [dBc]

60 55 50

0 50 100 150 200 250 300 350 400 450 500 550 600

800MSPS 1GSPS 1.2GSPS

Fout - [MHz]

Figure 12. AD9736, In Band SFDR vs. Fout and Sample Rate

Rev. PrJ | Page 11 of 42

AD9736/AD9735/AD9734 Preliminary Technical Data

Figure 13. AD9736, WCDMA carrier at 134.83MHz, fdata=491.52MSPS

Figure 14. AD9735, WCDMA carrier at 134.83MHz, fdata=491.52MSPS

Figure 15. AD9734, WCDMA carrier at 134.83MHz, fdata=491.52MSPS

Rev. PrJ | Page 12 of 42

Preliminary Technical Data AD9736/AD9735/AD9734

AD9736 Power Co nsu mpti o n 1x Mode Wi t h R espect to Clock Sp ee d

VDDD_1.8 VDDD_33 VDDA_1.8 VDDA_3.3 total

0.5

0.45

0.4

0.35

0.3

0.25

0.2

Power - W

0.15

0.1

0.05 0

0 250 500 750 1000 1250 1500

FCLK- MHz

Figure 16. AD9736 Power vs. Clock Frequency

AD9736 Power Co nsu mpti o n 2x Mode Wi t h R espect to Clock Sp ee d

VDDD_1.8 VDDD_33 VDDA_1.8 VDDA_3.3 total

0.7

0.6

0.5

0.4

0.3

Power - W

0.2

0.1 0

0 250 500 750 1000 1250 1500

FCLK- MHz

Figure 17. AD9736 Power vs. Clock Frequency in 2x Mode

Rev. PrJ | Page 13 of 42