Analog Devices AD9732 a Datasheet
10-Bit, 200 MSPS
CONTROL
AMP
INTERNAL
VOLTAGE
REFERENCE
SWITCH NETWORK
DECODERS AND DRIVERS
REGISTER
AD9732
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
CLOCK
R
SET
DIGITAL
+V
S
CONTROL
AMP IN
REF
OUT
CONTROL
AMP OUT
REF
IN
I
OUT
I
OUT
ANALOG
RETURN
TTL
DRIVE
LOGIC
a
FEATURES
200 MSPS Throughput Rate
3.3 V PECL Digital Input
65 dB SFDR @ 2 MHz A
A
, 200 MSPS
OUT
Low Power: 305 mW
Fast Settling: 5 ns to 1/2 LSB
Low Glitch Energy: 6 pVs
Internal Reference
28-Lead SSOP Packaging
APPLICATIONS
Digital Communications
Direct Digital Synthesis
Waveform Reconstruction
High Speed Imaging
GENERAL DESCRIPTION
The AD9732 is a 10-bit, 200 MSPS, bipolar D/A converter that
is optimized to provide high dynamic performance, yet offers
lower power dissipation and a more economical price than pre-
vious high speed DAC solutions. The AD9732 was primarily
designed for demanding communications systems applications
where maximum spurious-free dynamic range (SFDR) is required
at high throughput rates. The proliferation of digital communi-
cations into base station and high volume subscriber-end mar-
kets has created a demand for high performance bipolar DACs
delivered at CMOS associated levels of power dissipation and
cost. The AD9732 is the answer to that demand.
Optimized for direct digital synthesis (DDS) and digital modu-
lator waveform reconstruction, the AD9732 provides >50 dB of
wideband harmonic suppression over the dc to 80 MHz analog
output bandwidth. This signal bandwidth addresses the transmit
, 200 MSPS/54 dB @ 40 MHz
OUT
D/A Converter
AD9732
FUNCTIONAL BLOCK DIAGRAM
spectrum in many of the emerging digital communications ap-
plications where signal purity is critical. Narrowband (±1 MHz
window), the AD9732 provides an SFDR of greater than 75 dB.
This level of wideband and narrowband ac performance, coupled
with its 200 MSPS throughput rate, enables the AD9732 to
present outstanding value in the high speed DAC function.
The AD9732 is packaged in a 28-lead SSOP and is specified to
operate over the extended industrial temperature range of –40°C
to +85°C. Digital inputs and clock are positive-ECL compatible.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1999
AD9732–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(+VS = +5 V, ENCODE = 125 MSPS, R
= 1.95 k⍀ (for 20 mA I
SET
) unless otherwise noted)
OUT
Test AD9732BRS
Parameter Temp Level Min Typ Max Units
THROUGHPUT RATE +25°C IV 165 200 MHz
RESOLUTION 10 Bits
DC ACCURACY
Differential Nonlinearity +25°C I 0.25 1 LSB
Full VI 0.36 1 LSB
Integral Nonlinearity +25°C I 0.6 1.5 LSB
Full VI 0.7 1.5 LSB
INITIAL OFFSET ERROR
Zero-Scale Offset Error +25°C I 35 70 µA
Full VI 40 100 µA
+25°C I 2.5 5 % FS
Full-Scale Gain Error
1
Full VI 2.5 5 % FS
Offset Drift Coefficient V 0.04 µA/°C
REFERENCE/CONTROL AMP
Internal Reference Voltage
Internal Reference Voltage Drift Full IV 150 µV/°C
Internal Reference Output Current
2
3
+25°C I 3.65 3.75 3.85 V
Full VI –50 +500 µA
Amplifier Input Impedance +25°CI 50 kΩ
Amplifier Bandwidth +25°C I 2.5 MHz
4, 6
4
5
+25°C V 75 MHz
Full V 20 mA
REFERENCE INPUT
Reference Input Impedance +25°C V 4.6 kΩ
Reference Multiplying Bandwidth
OUTPUT PERFORMANCE
Output Current
Output Compliance Full IV 2 5.75 V
Output Resistance +25°C V 240 Ω
Output Capacitance +25°CV 5 pF
Voltage Settling Time to 1/2 LSB (t
Propagation Delay (t
Glitch Impulse
9
Output Slew Rate
Output Rise Time
Output Fall Time
8
)
PD
10
10
10
ST
7
)
+25°C V 4.75 ns
+25°C V 2.7 ns
Full V 5.9 pVs
Full V 450 V/µs
Full V 1 ns
Full V 1 ns
DIGITAL INPUTS
Logic “1” Voltage Full VI 2.4 V
Logic “0” Voltage Full VI 1.6 V
Logic “1” Current +25°C I 1.7 10 µA
Logic “0” Current +25°C I –1 0.01 1 µA
Input Capacitance Full V 2 pF
Minimum Data Setup Time (t
Minimum Data Hold Time (t
11
)
S
12
)
H
+25°C IV 0.7 1.5 ns
Full IV 1 1.5 ns
+25°C IV 0.7 1.5 ns
Full IV 1 1.5 ns
Clock Pulsewidth Low (pw
Clock Pulsewidth High (pw
POWER SUPPLY
13
) +25°CIV 2 ns
MIN
) +25°CIV 2 ns
MAX
Digital +V Supply Current +25°C I 15 25 35 mA
Full VI 10 40 mA
Analog +V Supply Current +25°C I 10 20 30 mA
Full VI 10 30 mA
+25°C V 305 mW
Power Dissipation
14
Full V 350 mW
Power Supply Rejection Ratio (PSRR) +25°C V 200 µA/V
–2– REV. A
AD9732
Test AD9732BRS
Parameter Temp Level Min Typ Max Units
SFDR PERFORMANCE (Wideband)
2 MHz A
10 MHz A
20 MHz A
40 MHz A
2 MHz A
10 MHz A
20 MHz A
40 MHz A
65 MHz A
65 MHz A
80 MHz A
OUT
OUT
OUT
OUT
(Clock = 165 MHz) +25°CV 63 dB
OUT
(Clock = 165 MHz) +25°CV 62 dB
OUT
(Clock = 165 MHz) +25°CV 56 dB
OUT
(Clock = 165 MHz) +25°CV 51 dB
OUT
(Clock = 165 MHz) +25°CV 48 dB
OUT
(Clock = 200 MHz) +25°CV 45 dB
OUT
(Clock = 200 MHz) +25°CV 43 dB
OUT
SFDR PERFORMANCE (Narrowband)
2 MHz; 2 MHz Span +25°CV 77 dB
25 MHz; 2 MHz Span +25°CV 65 dB
10 MHz; 5 MHz Span (Clock = 200 MHz) +25°CV 70 dB
INTERMODULATION DISTORTION
F1 = 800 kHz, F2 = 900 kHz to Nyquist +25°CV 69 dB
F1 = 800 kHz, F2 = 900 kHz, Narrowband
(2 MHz) +25°CV 61 dB
NOTES
1
Measured as an error in ratio of full-scale current to current through R
2
Internal reference voltage is tested under load conditions specified in Internal Reference Output Current specification.
3
Internal reference output current defines load conditions applied during Internal Reference Voltage test.
4
Full-scale current variations among devices are higher when driving REFERENCE IN directly.
5
Frequency at which a 3 dB change in output of DAC is observed; R
6
Based on IFS = 32 ([CONTROL AMP IN – (+VS)]/R
7
Measured as voltage settling at midscale transition to 0.1%; R
8
Measured from 50% point of rising edge of CLOCK signal to 1/2 LSB change in output signal.
9
Peak glitch impulse is measured as the largest area under a single positive or negative transient.
10
Measured with R
11
Data must remain stable for a specified time prior to rising edge of CLOCK.
12
Data must remain stable for a specified time after rising edge of CLOCK.
13
Supply voltages should remain stable with ±5% for nominal operation.
14
Power dissipation calculation includes current through a 50 Ω load.
15
SFDR is defined as the difference in signal energy between the full-scale fundamental signal and worst case spurious frequencies in the output spectrum window.
The frequency span dc to Nyquist unless otherwise noted.
16
Intermodulation distortion is the measure of the sum and difference products produced when a two-tone input is driven into the DAC. The distortion products
created will manifest themselves at sum and difference frequencies of the two tones.
Specifications subject to change without notice.
= 50 Ω and DAC operating in latched mode.
L
15
+25°CV 66 dB
+25°CV 63 dB
+25°CV 57 dB
+25°CV 52 dB
15
16
(640 µA nominal); ratio is nominally 32. DAC load is virtual ground.
SET
= 50 Ω; 100 mV modulation at midscale.
= 50 Ω.
L
L
) when using internal control amplifier. DAC load is virtual ground.
SET
EXPLANATION OF TEST LEVELS
Test Level
I 100% production tested.
II 100% production tested at +25°C and sample tested at
specified temperatures.
III Sample tested only.
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
AD9732BRS –40°C to +85°C 28-Lead Small Outline (SSOP) RS-28
AD9732/PCB +25°C Evaluation Board
IV Parameter is guaranteed by design and characterization
testing.
V Parameter is a typical value only.
VI 100% production tested at +25°C; guaranteed by design
and characterization testing for industrial temperature
range.
–3–REV. A
AD9732
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS*
Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+V
S
+VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . –0.7 V to +V
S
Analog Output Current . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Control Amplifier Input Voltage Range . . . . . . . . . 0 V to +V
Reference Input Voltage Range . . . . . . . . . . . . . . . 0 V to +V
S
S
Internal Reference Output Current . . . . . . . . . . . . . . . 500 µA
Control Amplifier Output Current . . . . . . . . . . . . . . ±2.5 mA
Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . +175°C
Lead Temperature (10 sec) Soldering . . . . . . . . . . . . +300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
PIN CONFIGURATION
D8
D7
D6
D5
D4
D3
D2
D1
CLOCK
NC
NC
S
1
2
3
4
5
6
AD9732
7
TOP VIEW
(Not to Scale)
8
9
10
11
12
13
14
NC = NO CONNECT
D9 (MSB)
D0 (LSB)
DIGITAL +V
DIGITAL +V
28
27
GND
26
CONTROL AMP IN
25
REF OUT
24
CONTROL AMP OUT
23
REF IN
22
GND
21
I
OUTB
I
20
OUT
19
ANALOG RETURN
18
ANALOG +V
17
R
SET
16
GND
15
DIGITAL +V
S
S
S
PIN FUNCTION DESCRIPTIONS
Pin Number Name Function
1 D9 (MSB) Most significant data bit of digital input word.
2–9 D8–D1 Eight bits of 10-bit digital input word.
10 D0 (LSB) Least significant data bit of digital input word.
11 CLOCK TTL-compatible edge-triggered latch enable signal for on-board registers.
12, 13 NC No internal connection to this pin. Recommend tie to ground.
14, 15, 28 DIGITAL +V
S
+5 V supply voltage for digital circuitry.
16, 22, 27 GND Converter Ground.
18 ANALOG +V
17 R
SET
S
+5 V supply voltage for analog circuitry.
Connection for external reference set resistor; nominal 1.96 kΩ. Full-scale output
current = 32 [Control Amp + V
] (Reset).
S
19 ANALOG RETURN Analog Return. This point and the reference side of the DAC load resistors should be
20 I
OUT
connected to the same potential (Analog +V
Analog current output; full-scale current occurs with a digital word input of all “1s”
with external load resistor, output voltage = I
).
S
OUT
(R
LOAD储RINTERNAL
). R
INTERNAL
is
nominally 240 Ω.
21 I
OUTB
Complementary analog current output; full-scale current occurs with a digital word
input of all “0s.”
23 REF IN Normally connected to CONTROL AMP OUT (Pin 24). Direct line to DAC current
source network. Voltage changes (noise) at this point have a direct effect on the full-
scale output current of the DAC. Full-scale current output = 32 (CONTROL AMP IN/
R
) when using internal amplifier. DAC load is virtual ground.
SET
24 CONTROL AMP OUT Normally connected to REF IN (Pin 23). Output of internal control amplifier, which
provides a reference for the current switch network.
25 REF OUT Normally connected to CONTROL AMP IN (Pin 26). Internal voltage reference,
nominally 3.75 V.
26 CONTROL AMP IN Normally connected to REF OUT (Pin 25) if not connected to external reference.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9732 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4– REV. A
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