Analog Devices AD9708 Datasheet

a

+1.20V REF

REFLO

REF IO

FS ADJ

50pF

COMP1

0.1mF

CURRENT

SOURCE

ARRAY

+5V

AVDD

SEGMENTED

SWITCHES

LATCHES

DIGITAL DATA INPUTS (DB7–DB0)

DVDD
DCOM

CLOCK

SLEEP

IOUTA
IOUTB

COMP2

ACOM

0.1mF

+5V

R

SET

CLOCK

0.1mF

AD9708

8-Bit, 100 MSPS+

TxDAC

®

D/A Converter

AD9708*

FEATURES
Member of Pin-Compatible TxDAC Product Family
125 MSPS Update Rate
8-Bit Resolution
Linearity: 1/4 LSB DNL

Linearity: 1/4 LSB INL

Differential Current Outputs
SINAD @ 5 MHz Output: 50 dB
Power Dissipation: 175 mW @ 5 V to 45 mW @ 3 V
Power-Down Mode: 20 mW @ 5 V
On-Chip 1.20 V Reference
Single +5 V or +3 V Supply Operation
Packages: 28-Lead SOIC and 28-Lead TSSOP
Edge-Triggered Latches
Fast Settling: 35 ns Full-Scale Settling to 0.1%

APPLICATIONS
Communications
Signal Reconstruction
Instrumentation

PRODUCT DESCRIPTION

The AD9708 is the 8-bit resolution member of the TxDAC
series of high performance, low power CMOS digital-to-analog
converters (DACs). The TxDAC family, which consists of pin
compatible 8-, 10-, 12-, and 14-bit DACs, was specifically opti­mized for the transmit signal path of communication systems. All
of the devices share the same interface options, small outline
package and pinout, thus providing an upward or downward
component selection path based on performance, resolution and
cost. The AD9708 offers exceptional ac and dc performance
while supporting update rates up to 125 MSPS.

The AD9708’s flexible single-supply operating range of +2.7 V
to +5.5 V and low power dissipation are well suited for portable
and low power applications. Its power dissipation can be
further reduced to 45 mW, without a significant degradation in
performance, by lowering the full-scale current output. In addi­tion, a power-down mode reduces the standby power dissipa­tion to approximately 20 mW.

The AD9708 is manufactured on an advanced CMOS process.
A segmented current source architecture is combined with a
proprietary switching technique to reduce spurious components
and enhance dynamic performance. Edge-triggered input latches
and a temperature compensated bandgap reference have been inte­grated to provide a complete monolithic DAC solution. Flexible
supply options support +3 V and +5 V CMOS logic families.

The AD9708 is a current-output DAC with a nominal full-scale

output current of 20 mA and > 100 kΩ output impedance.

TxDAC is a registered trademark of Analog Devices, Inc.
*Patent pending.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

FUNCTIONAL BLOCK DIAGRAM

Differential current outputs are provided to support single­ended or differential applications. The current outputs may be
directly tied to an output resistor to provide two complemen­tary, single-ended voltage outputs. The output voltage compliance
range is 1.25 V.

The AD9708 contains a 1.2 V on-chip reference and reference
control amplifier, which allows the full-scale output current to
be simply set by a single resistor. The AD9708 can be driven by
a variety of external reference voltages. The AD9708’s full-scale
current can be adjusted over a 2 mA to 20 mA range without
any degradation in dynamic performance. Thus, the AD9708
may operate at reduced power levels or be adjusted over a 20 dB
range to provide additional gain ranging capabilities.

The AD9708 is available in 28-lead SOIC and 28-lead TSSOP
packages. It is specified for operation over the industrial tem­perature range.

PRODUCT HIGHLIGHTS

1. The AD9708 is a member of the TxDAC product family, which
provides an upward or downward component selection path
based on resolution (8 to 14 bits), performance and cost.

2. Manufactured on a CMOS process, the AD9708 uses a pro­prietary switching technique that enhances dynamic perfor­mance well beyond 8- and 10-bit video DACs.

3. On-chip, edge-triggered input CMOS latches readily interface
to +3 V and +5 V CMOS logic families. The AD9708 can
support update rates up to 125 MSPS.

4. A flexible single-supply operating range of +2.7 V to +5.5 V
and a wide full-scale current adjustment span of 2 mA to
20 mA allows the AD9708 to operate at reduced power levels
(i.e., 45 mW) without any degradation in dynamic performance.

5. A temperature compensated, 1.20 V bandgap reference is
included on-chip providing a complete DAC solution. An
external reference may be used.

6. The current output(s) of the AD9708 can easily be config­ured for various single-ended or differential applications.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

AD9708–SPECIFICATIONS

DC SPECIFICATIONS

(T

to T

MIN

, AVDD = +5 V, DVDD = +5 V, I

MAX

= 20 mA, unless otherwise noted)

OUTFS

Parameter Min Typ Max Units

RESOLUTION 8 Bits

MONOTONICITY GUARANTEED OVER SPECIFIED TEMPERATURE RANGE

DC ACCURACY

1

Integral Linearity Error (INL) –1/2 ±1/4 +1/2 LSB
Differential Nonlinearity (DNL) –1/2 ±1/4 +1/2 LSB

ANALOG OUTPUT

Offset Error –0.025 +0.025 % of FSR
Gain Error
Gain Error
Full-Scale Output Current

(Without Internal Reference) –10 ±2 +10 % of FSR
(With Internal Reference) –10 ±1 +10 % of FSR

2

2.0 20.0 mA

Output Compliance Range –1.0 1.25 V

Output Resistance 100 kΩ

Output Capacitance 5 pF

REFERENCE OUTPUT

Reference Voltage 1.08 1.20 1.32 V
Reference Output Current

3

100 nA

REFERENCE INPUT

Input Compliance Range 0.1 1.25 V

Reference Input Resistance 1 MΩ

Small Signal Bandwidth (w/o C

COMP1

4

)

1.4 MHz

TEMPERATURE COEFFICIENTS

Offset Drift 0 ppm of FSR/°C

Gain Drift
Gain Drift

(Without Internal Reference) ±50 ppm of FSR/°C
(With Internal Reference) ±100 ppm of FSR/°C

Reference Voltage Drift ±50 ppm/°C

POWER SUPPLY

Supply Voltages

AVDD

5

2.7 5.0 5.5 V

DVDD 2.7 5.0 5.5 V
Analog Supply Current (I
Digital Supply Current (I
Supply Current Sleep Mode (I
Power Dissipation
Power Dissipation
Power Dissipation

6

(5 V, I

7

(5 V, I

7

(3 V, I

)2530mA

AVDD

6

)

DVDD

OUTFS

OUTFS

OUTFS

) 8.5 mA

AVDD

= 20 mA) 140 175 mW
= 20 mA) 190 mW
= 2 mA) 45 mW

36mA

Power Supply Rejection Ratio—AVDD –0.4 +0.4 % of FSR/V
Power Supply Rejection Ratio—DVDD –0.025 +0.025 % of FSR/V

OPERATING RANGE –40 +85 °C

NOTES

1

Measured at IOUTA, driving a virtual ground.

2

Nominal full-scale current, I

3

Use an external buffer amplifier to drive any external load.

4

Reference bandwidth is a function of external cap at COMP1 pin.

5

For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance.

6

Measured at f

7

Measured as unbuffered voltage output into 50 Ω R

Specifications subject to change without notice.

= 50 MSPS and f

CLOCK

, is 32 × the I

OUTFS

= 1.0 MHz.

OUT

current.

REF

at IOUTA and IOUTB, f

LOAD

= 100 MSPS and f

CLOCK

= 40 MHz.

OUT

–2–

REV. B

AD9708

(T

to T

MIN

DYNAMIC SPECIFICATIONS

P

arameter Min Typ Max Units

Terminated, unless otherwise noted)

, AVDD = +5 V, DVDD = +5 V, I

MAX

DYNAMIC PERFORMANCE

Maximum Output Update Rate (f
Output Settling Time (t
Output Propagation Delay (t

) (to 0.1%)

ST

)1ns

PD

Glitch Impulse 5 pV-s
Output Rise Time (10% to 90%)
Output Fall Time (10% to 90%)
Output Noise (I
Output Noise (I

= 20 mA) 50 pA/√Hz

OUTFS

= 2 mA) 30 pA/√Hz

OUTFS

) 100 125 MSPS

CLOCK

1

1

1

AC LINEARITY TO NYQUIST

Signal-to-Noise and Distortion Ratio

f

= 10 MSPS; f

CLOCK

f

= 50 MSPS; f

CLOCK

f

= 50 MSPS; f

CLOCK

f

= 100 MSPS; f

CLOCK

f

= 100 MSPS; f

CLOCK

= 1.00 MHz 50 dB

OUT

= 1.00 MHz 50 dB

OUT

= 12.51 MHz 48 dB

OUT

= 5.01 MHz 50 dB

OUT

= 25.01 MHz 45 dB

OUT

Total Harmonic Distortion

f

= 10 MSPS; f

CLOCK

f

= 50 MSPS; f

CLOCK

f

= 50 MSPS; f

CLOCK

f

= 100 MSPS; f

CLOCK

f

= 100 MSPS; f

CLOCK

= 1.00 MHz –67 dBc

OUT

= 1.00 MHz –67 –62 dBc

OUT

= 12.51 MHz –59 dBc

OUT

= 5.01 MHz –64 dBc

OUT

= 25.01 MHz –48 dBc

OUT

Spurious-Free Dynamic Range to Nyquist

f

= 10 MSPS; f

CLOCK

f

= 50 MSPS; f

CLOCK

f

= 50 MSPS; f

CLOCK

f

= 100 MSPS; f

CLOCK

f

= 100 MSPS; f

CLOCK

NOTES

1

Measured single ended into 50 Ω load.

Specifications subject to change without notice.

= 1.00 MHz 68 dBc

OUT

= 1.00 MHz 62 68 dBc

OUT

= 12.51 MHz 63 dBc

OUT

= 5.01 MHz 67 dBc

OUT

= 25.01 MHz 50 dBc

OUT

= 20 mA, Single-Ended Output, IOUTA, 50 ⍀ Doubly

OUTFS

35 ns

2.5 ns

2.5 ns

DIGITAL SPECIFICATIONS

P

arameter Min Typ Max Units

(T

to T

MIN

, AVDD = +5 V, DVDD = +5 V, I

MAX

= 20 mA unless otherwise noted)

OUTFS

DIGITAL INPUTS

Logic “1” Voltage @ DVDD = +5 V 3.5 5 V
Logic “1” Voltage @ DVDD = +3 V 2.1 3 V
Logic “0” Voltage @ DVDD = +5 V 0 1.3 V
Logic “0” Voltage @ DVDD = +3 V 0 0.9 V

Logic “1” Current –10 +10 µA
Logic “0” Current –10 +10 µA

Input Capacitance 5pF
Input Setup Time (t
Input Hold Time (t

Latch Pulsewidth (t

Specifications subject to change without notice.

)2.0ns

S

)1.5ns

H

LPW

)

DB0–DB7

t

S

CLOCK

t

PD

IOUTA

OR

IOUTB

3.5 ns

t

H

t

LPW

t

ST

0.1%

0.1%

Figure 1. Timing Diagram

REV. B

–3–

AD9708

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

With

Parameter Respect to Min Max Units

AVDD ACOM –0.3 +6.5 V
DVDD DCOM –0.3 +6.5 V
ACOM DCOM –0.3 +0.3 V
AVDD DVDD –6.5 +6.5 V
CLOCK, SLEEP DCOM –0.3 DVDD + 0.3 V
Digital Inputs DCOM –0.3 DVDD + 0.3 V
IOUTA, IOUTB ACOM –1.0 AVDD + 0.3 V
COMP1, COMP2 ACOM –0.3 AVDD + 0.3 V
REFIO, FSADJ ACOM –0.3 AVDD + 0.3 V
REFLO ACOM –0.3 +0.3 V

Junction Temperature +150 °C
Storage Temperature –65 +150 °C

Lead Temperature

(10 sec) +300 °C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may effect device reliability.

THERMAL CHARACTERISTICS
Thermal Resistance

28-Lead 300 mil SOIC

= 71.4°C/W

θ

JA

= 23°C/W

θ

JC

28-Lead TSSOP

θ

= 97.9°C/W

JA

= 14.0°C/W

θ

JC

PIN CONFIGURATION

(MSB) DB7

DB6
DB5
DB4
DB3
DB2

DB1

DB0

NC
NC
NC
NC
NC

NC

1
2
3
4
5

AD9708

6

TOP VIEW

(Not to Scale)

7
8

9
10
11
12
13
14

NC = NO CONNECT

28
27
26
25
24
23
22

21

20
19
18
17
16
15

CLOCK
DVDD
DCOM
NC
AVDD
COMP2
IOUTA
IOUTB
ACOM
COMP1
FS ADJ
REFIO
REFLO
SLEEP

PIN FUNCTION DESCRIPTIONS

Pin No. Name Description

1 DB7 Most Significant Data Bit (MSB).
2–7 DB6–DB1 Data Bits 1–6.
8 DB0 Least Significant Data Bit (LSB).
9–14, 25 NC No Internal Connection.
15 SLEEP Power-Down Control Input. Active

High. Contains active pull-down circuit,
thus may be left unterminated if not
used.

16 REFLO Reference Ground when Internal 1.2 V

Reference Used. Connect to AVDD to
disable internal reference.

17 REFIO Reference Input/Output. Serves as

reference input when internal reference
disabled (i.e., Tie REFLO to AVDD).
Serves as 1.2 V reference output when
internal reference activated (i.e., Tie

REFLO to ACOM). Requires 0.1 µF

capacitor to ACOM when internal

reference activated.
18 FS ADJ Full-Scale Current Output Adjust.
19 COMP1 Bandwidth/Noise Reduction Node.

Add 0.1 µF to AVDD for optimum

performance.
20 ACOM Analog Common.
21 IOUTB Complementary DAC Current Output.

Full-scale current when all data bits

are 0s.
22 IOUTA DAC Current Output. Full-scale

current when all data bits are 1s.
23 COMP2 Internal Bias Node for Switch Driver

Circuitry. Decouple to ACOM with

0.1 µF capacitor.

24 AVDD Analog Supply Voltage (+2.7 V to

+5.5 V).
26 DCOM Digital Common.
27 DVDD Digital Supply Voltage (+2.7 V to

+5.5 V).
28 CLOCK Clock Input. Data latched on positive

edge of clock.

ORDERING GUIDE

Temperature Package Package

Model Range Descriptions Options*

AD9708AR –40°C to +85°C 28-Lead 300 Mil SOIC R-28
AD9708ARU –40°C to +85°C 28-Lead TSSOP RU-28

AD9708-EB Evaluation Board

*R = Small Outline IC; RU = Thin Small Outline IC.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9708 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–4–

REV. B

AD9708

DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)

Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.

Differential Nonlinearity (or DNL)

DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.

Monotonicity

A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.

Offset Error

The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when
the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.

Gain Error

The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.

Output Compliance Range

The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown resulting in
nonlinear performance.

Temperature Drift

Temperature drift is specified as the maximum change from the

ambient (+25°C) value to the value at either T

MIN

or T

MAX

. For

offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree C. For reference drift, the drift is
reported in ppm per degree C.

Power Supply Rejection

The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.

Settling Time

The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.

Glitch Impulse

Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.

Spurious-Free Dynamic Range

The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.

Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio

S/N+D is the ratio of the rms value of the measured output
signal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/N+D is expressed in decibels.

Total Harmonic Distortion

THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured output signal. It is
expressed as a percentage or in decibels (dB).

DVDD

DCOM

0.1mF

R

SET

2kV

50V

RETIMED

CLOCK

OUTPUT*

LECROY 9210

PULSE GENERATOR

+5V

+5V

0.1mF

AVDD

CURRENT

SOURCE

ARRAY

SEGMENTED

SWITCHES

LATCHES

DIGITAL

DATA

TEKTRONIX

AWG-2021

ACOM

AD9708

COMP2

IOUTA
IOUTB

50V

+1.20V REF

REF IO
FS ADJ

DVDD
DCOM

CLOCK

SLEEP

REFLO

CLOCK

OUTPUT

COMP1

50pF

Figure 2. Basic AC Characterization Test Setup

0.1mF

50V

20pF

20pF

* AWG2021 CLOCK RETIMED
SUCH THAT DIGITAL DATA
TRANSITIONS ON FALLING EDGE
OF 50% DUTY CYCLE CLOCK.

TO HP3589A
SPECTRUM/
NETWORK
ANALYZER
50V INPUT

REV. B

–5–