ANALOG DEVICES AD9640 Service Manual

14-Bit, 80/105/125/150 MSPS, 1.8 V

FEATURES

SNR = 71.8 dBc (72.8 dBFS) to 70 MHz @ 125 MSPS SFDR = 85 dBc to 70 MHz @ 125 MSPS Low power: 750 mW @ 125 MSPS SNR = 71.6 dBc (72.6 dBFS) to 70 MHz @ 150 MSPS SFDR = 84 dBc to 70 MHz @ 150 MSPS Low power: 820 mW @ 150 MSPS

1.8 V analog supply operation

1.8 V to 3.3V CMOS output supply or 1.8 V LVDS output supply

Integer 1 to 8 input clock divider IF sampling frequencies to 450 MHz Internal ADC voltage reference Integrated ADC sample-and-hold inputs Flexible analog input range: 1 V p-p to 2 V p-p Differential analog inputs with 650 MHz bandwidth ADC clock duty cycle stabilizer 95 dB channel isolation/crosstalk Serial port control User-configurable, built-in self-test (BIST) capability Energy-saving power-down modes Integrated receive features

Fast detect/threshold bits Composite signal monitor

APPLICATIONS

Communications Diversity radio systems Multimode digital receivers

GSM, EDGE, WCDMA, LTE, CDMA2000, WiMAX, TD-SCDMA

I/Q demodulation systems Smart antenna systems General-purpose software radios Broadband data applications

Dual Analog-to-Digital Converter

AD9640

FUNCTIONAL BLOCK DIAGRAM

SCLK/

AVDD

FD BITS/THRESHOLD

VIN+A

VIN–A

VREF

SENSE

CML

RBIAS

VIN–B

VIN+B

SHA

REF

SELECT

SHA

MULTICHIP

SYNC

AGND SYNC FD(0:3)B

FD(0:3)A

DVDD

DETECT

ADC

FD BITS/T HRE SHO LD

PRODUCT HIGHLIGHTS

1. Integrated dual 14-bit, 80/105/125/150 MSPS ADC.

2. Fast overrange detect and signal monitor with serial output.

3. Signal monitor block with dedicated serial output mode.

4. Proprietary differential input that maintains excellent SNR

performance for input frequencies up to 450 MHz.

5. Operation from a single 1.8 V supply and a separate digital

output driver supply to accommodate 1.8 V to 3.3 V logic families.

6. A standard serial port interface that supports various

product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, and voltage reference mode.

7. Pin compatibility with the AD9627, AD9627-11, and the

AD9600 for a simple migration from 14 bits to 12 bits, 11

bits, or 10 bits.

SDIO/

DCS

PROGRAMMING DATA

SIGNAL

MONITOR

DIVIDE

1TO 8

DUTY CYCLE

STABILIZER

ADC

DETECT

Figure 1.

DFS

CSB

SPI

DCO

GENERATION

SIGNAL MONITOR

DATA

SIGNAL MONITOR

INTERFACE

SMI

SCLK/

SDFS

PDWN

DRVDD

CMOS

SMI

SDO/

OEB

D13A

D0A

OUTPUT BUFFE R

CLK+

CLK– DCOA

DCOB

D13B

D0B

OUTPUT BUFFER

DRGND

06547-001

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD9640

REVISION HISTORY

12/09—Rev. A to Rev. B

Added CP-64-6 Package .................................................... Universal

Changes to Ordering Guide ........................................................... 51

6/09—Rev. 0 to Rev. A

Changes to Applications Section and Product

Highlights Section ............................................................................. 1

Changes to General Description Section ....................................... 3

Changes to Specifications Section ................................................... 4

Changes to Figure 2 ......................................................................... 11

Changes to Figure 3 ......................................................................... 12

Changes to Pin Configurations and Functional

Descriptions Section ....................................................................... 12

Changes to Figure 11, Figure 12, Figure 14 ................................. 18

Change to Table 15 .......................................................................... 30

Changes to ADC Overrange and Gain Control Section ............ 31

Changes to Signal Monitor Section .............................................. 34

Changes to Table 25 ........................................................................ 42

Changes to Signal Monitor Period (Register 0x113 to

Register 0x115) Section .................................................................. 47

Added LVDS Operation Section ................................................... 48

Added Exposed Pad Notation to Outline Dimensions .............. 49

6/07—Revision 0: Initial Version

Rev. B | Page 3 of 52

AD9640

GENERAL DESCRIPTION

The AD9640 is a dual 14-bit, 80/105/125/150 MSPS analog-todigital converter (ADC). The AD9640 is designed to support communications applications where low cost, small size, and versatility are desired.

The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.

The AD9640 has several functions that simplify the automatic gain control (AGC) function in the system receiver. The fast detect feature allows fast overrange detection by outputting four bits of input level information with very short latency.

In addition, the programmable threshold detector allows monitoring of the incoming signal power using the four fast detect bits of the ADC with very low latency. If the input signal level exceeds the programmable threshold, the fine upper threshold indicator goes high. Because this threshold is set from the four MSBs, the user can quickly turn down the system gain to avoid an overrange condition.

The second AGC-related function is the signal monitor. This block allows the user to monitor the composite magnitude of the incoming signal, which aids in setting the gain to optimize the dynamic range of the overall system.

The ADC output data can be routed directly to the two external 14-bit output ports. These outputs can be set from 1.8 V to 3.3 V CMOS or 1.8 V LVDS.

Flexible power-down options allow significant power savings, when desired.

Programming for setup and control is accomplished using a 3-bit SPI-compatible serial interface.

The AD9640 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.

Rev. B | Page 4 of 52

AD9640

SPECIFICATIONS

ADC DC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND AD9640BCPZ-105

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted.

Table 1.

AD9640ABCPZ-

80/AD9640BCPZ-80

Parameter Temperature

Min Typ Max Min Typ Max

RESOLUTION Full 14 14 Bits ACCURACY

No Missing Codes Full Guaranteed Guaranteed Offset Error Full ±0.3 ±0.6 ±0.3 ±0.6 % FSR Gain Error Full ±0.2 ±3.0 ±0.2 ±3.0 % FSR Differential Nonlinearity (DNL)1 Full ±0.9 ±0.9 LSB 25°C ±0.4 ±0.4 LSB Integral Nonlinearity (INL)1

Full ±5.0 ±5.0 LSB 25°C ±2.0 ±2.0 LSB MATCHING CHARACTERISTIC

Offset Error Full ±0.3 ±0.6 ±0.4 ±0.7 % FSR Gain Error Full ±0.1 ±0.5 ±0.1 ±0.5 % FSR

TEMPERATURE DRIFT

Offset Error Full ±15 ±15 ppm/°C Gain Error Full ±95 ±95 ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage Error (1 V Mode) Full ±2 ±15 ±2 ±15 mV Load Regulation @ 1.0 mA Full 7 7 mV

INPUT REFERRED NOISE

VREF = 1.0 V 25°C 1.3 1.3 LSB rms

ANALOG INPUT

Input Span, VREF = 1.0 V Full 2 2 V p-p

Input Capacitance2 Full 8 8 pF VREF INPUT RESISTANCE Full 6 6 kΩ POWER SUPPLIES

Supply Voltage

AVDD, DVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD (CMOS Mode) Full 1.7 3.3 3.6 1.7 3.3 3.6 V DRVDD (LVDS Mode) Full 1.7 1.8 1.9 1.7 1.8 1.9 V

Supply Current

1, 3

I

AVDD

1, 3

I

DVDD

1

I

(3.3 V CMOS)

DRVDD

1

I

(1.8 V CMOS)

DRVDD

1

I

(1.8 V LVDS)

DRVDD

Full 233 Full 26 34 mA

277

Full 27 35 mA Full 12 18 mA Full 54 55 mA

POWER CONSUMPTION

DC Input Full 452 492 603 657 mW

Sine Wave Input1 (DRVDD = 1.8 V)

Sine Wave Input1 (DRVDD = 3.3 V)

Full 487 645 mW

Full 550 730 mW Standby Power4 Full 52 68 mW Power-Down Power Full 2.5 6 2.5 6 mW

1

Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.

2

Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 8 for the equivalent analog input structure.

3

The maximum limit applies to the combination of I

4

Standby power is measured with a dc input and with the CLK pins (CLK+, CLK−) inactive (set to AVDD or AGND).

AVDD

and I

DVDD

currents.

AD9640ABCPZ-

105/AD9640BCPZ-105

310

371

Unit

mA

Rev. B | Page 5 of 52

AD9640

ADC DC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND AD9640BCPZ-150

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted.

Table 2.

AD9640ABCPZ-125/

AD9640BCPZ-125

Parameter Temperature

Min Typ Max Min Typ Max

RESOLUTION Full 14 14 Bits ACCURACY

No Missing Codes Full Guaranteed Guaranteed Offset Error Full ±0.3 ±0.6 ±0.3 ±0.6 % FSR Gain Error Full ±0.2 ±3.0 ±0.2 ±3.0 % FSR Differential Nonlinearity (DNL)1 Full ±0.9 −0.95/+1.5 LSB

25°C ±0.4 −0.4/+0.6 LSB

Integral Nonlinearity (INL)1

Full ±5.0 ±5.0 LSB 25°C ±2 ±2 LSB MATCHING CHARACTERISTIC

Offset Error 25°C ±0.4 ±0.7 ±0.4 ±0.7 % FSR Gain Error 25°C ±0.1 ±0.6 ±0.2 ±0.6 % FSR

TEMPERATURE DRIFT

Offset Error Full ±15 ±15 ppm/°C Gain Error Full ±95 ±95 ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage Error (1 V Mode) Full ±2 ±15 ±3 ±15 mV Load Regulation @ 1.0 mA Full 7 7 mV

INPUT REFERRED NOISE

VREF = 1.0 V 25°C 1.3 1.3 LSB rms

ANALOG INPUT

Input Span, VREF = 1.0 V Full 2 2 V p-p Input Capacitance2

Full 8 8 pF VREF INPUT RESISTANCE Full 6 6 kΩ POWER SUPPLIES

Supply Voltage

AVDD, DVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD (CMOS Mode) Full 1.7 3.3 3.6 1.7 3.3 3.6 V DRVDD (LVDS Mode) Full 1.7 1.8 1.9 1.7 1.8 1.9 V

Supply Current

I

AVDD

I

DVDD

I

DRVDD

I

DRVDD

I

DRVDD

1, 3

1

(3.3 V CMOS) (1.8 V CMOS) (1.8 V LVDS)

Full 385

Full 42 50 mA

470

Full 44 53 mA

Full 22 27 mA

56 57 POWER CONSUMPTION

DC Input Full 750 846 820 938 mW Sine Wave Input1 (DRVDD = 1.8 V) Sine Wave Input1 (DRVDD = 3.3 V)

Full 810 895 mW

Full 910 1000 mW

Standby Power4 Full 77 77 mW Power-Down Power Full 2.5 6 2.5 6 mW

1

Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.

2

Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 8 for the equivalent analog input structure.

3

The maximum limit applies to the combination of I

4

Standby power is measured with a dc input and with the CLK pins (CLK+, CLK−) inactive (set to AVDD or AGND).

AVDD

and

IDVDD

currents.

AD9640ABCPZ-150/

AD9640BCPZ-150

419

517

Unit

mA

Rev. B | Page 6 of 52

AD9640

ADC AC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND AD9640BCPZ-105

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted.

Table 3.

AD9640ABCPZ-80/

AD9640BCPZ-80

Parameter1 Temperature

SIGNAL-TO-NOISE RATIO (SNR)

fIN = 2.3 MHz 25°C 72.5 72.3 dB fIN = 70 MHz 25°C 72.1 71.9 dB Full 70.5 70.2 dB fIN = 140 MHz 25°C 71.6 71.3 dB fIN = 200 MHz 25°C 71.0 70.3 dB

SIGNAL-TO-NOISE AND DISTORTION (SINAD)

fIN = 2.3 MHz 25°C 72.2 72.0 dB fIN = 70 MHz 25°C 71.6 71.6 dB Full 69 69.5 dB fIN = 140 MHz 25°C 71.1 70.9 dB fIN = 200 MHz 25°C 70.4 70.0 dB

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 2.3 MHz 25°C 11.9 11.8 Bits fIN = 70 MHz 25°C 11.8 11.8 Bits fIN = 140 MHz 25°C 11.7 11.7 Bits fIN = 200 MHz 25°C 11.6 11.5 Bits

WORST SECOND OR THIRD HARMONIC

fIN = 2.3 MHz 25°C −87 −87 dBc fIN = 70 MHz 25°C −85 −85 dBc Full −75 −74 dBc fIN = 140 MHz 25°C −84 −84 dBc fIN = 200 MHz 25°C −83 −83 dBc

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 2.3 MHz 25°C 87 87 dBc fIN = 70 MHz 25°C 85 85 dBc Full 75 74 dBc fIN = 140 MHz 25°C 84 84 dBc fIN = 200 MHz 25°C 83 83 dBc

WORST OTHER HARMONIC OR SPUR

fIN = 2.3 MHz 25°C −93 −93 dBc fIN = 70 MHz 25°C −89 −89 dBc Full −82 −81 dBc fIN = 140 MHz 25°C −89 −89 dBc fIN = 200 MHz 25°C −89 −89 dBc

TWO TONE SFDR

fIN = 29.1 MHz, 32.1 MHz (−7 dBFS) 25°C 85 85 dBc

fIN = 169.1 MHz, 172.1 MHz (−7 dBFS) 25°C 82 82 dBc CROSSTALK2 Full −95 −95 dB ANALOG INPUT BANDWIDTH 25°C 650 650 MHz

1

See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

2

Crosstalk is measured at 100 MHz with −1 dBFS on one channel and no input on the alternate channel.

Min Typ Max Min Typ Max

AD9640ABCPZ-105/

AD9640BCPZ-105

Unit

Rev. B | Page 7 of 52

AD9640

ADC AC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND AD9640BCPZ 150

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted.

Table 4.

AD9640ABCPZ-125

AD9640BCPZ-125

Parameter1 Temperature

SIGNAL-TO-NOISE RATIO (SNR)

fIN = 2.3 MHz 25°C 72.1 71.9 dB fIN = 70 MHz 25°C 71.8 71.6 dB Full 70.2 69.5 dB fIN = 140 MHz 25°C 71.4 70.9 dB fIN = 200 MHz 25°C 70.8 70.0 dB

SIGNAL-TO-NOISE AND DISTORTION (SINAD)

fIN = 2.3 MHz 25°C 71.8 71.6 dB fIN = 70 MHz 25°C 71.4 71.0 dB Full 69.5 67.5 dB fIN = 140 MHz 25°C 71.0 70.5 dB fIN = 200 MHz 25°C 70.3 69.9 dB

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 2.3 MHz 25°C 11.8 11.8 Bits fIN = 70 MHz 25°C 11.7 11.8 Bits fIN = 140 MHz 25°C 11.7 11.6 Bits fIN = 200 MHz 25°C 11.6 11.5 Bits

WORST SECOND OR THIRD HARMONIC

fIN = 2.3 MHz 25°C −86.5 −86.5 dBc fIN = 70 MHz 25°C −85 −84 dBc Full −74 −73 dBc fIN = 140 MHz 25°C −84 −83.5 dBc fIN = 200 MHz 25°C −83 −77 dBc

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 2.3 MHz 25°C 86.5 86.5 dBc fIN = 70 MHz 25°C 85 84 dBc Full 74 73 dBc fIN = 140 MHz 25°C 84 83.5 dBc fIN = 200 MHz 25°C 83 77 dBc

WORST OTHER HARMONIC OR SPUR

fIN = 2.3 MHz 25°C −92 −92 dBc fIN = 70 MHz 25°C −89 −90 dBc Full −80 −80 dBc fIN = 140 MHz 25°C −89 −90 dBc fIN = 200 MHz 25°C −89 −90 dBc

TWO TONE SFDR

fIN = 29.1 MHz, 32.1 MHz (−7 dBFS) 25°C 85 85 dBc

fIN = 169.1 MHz, 172.1 MHz (−7 dBFS) 25°C 82 82 dBc CROSSTALK2 Full −95 −95 dB ANALOG INPUT BANDWIDTH 25°C 650 650 MHz

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

2

Crosstalk is measured at 100 MHz with −1 dBFS on one channel and no input on the alternate channel.

Min Typ Max Min Typ Max

AD9640ABCPZ-150/

AD9640BCPZ-150

Unit

Rev. B | Page 8 of 52

AD9640

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted.

Table 5.

Parameter Temperature Min Typ Max Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 1.2 V Differential Input Voltage Full 0.2 6 V p-p Input Voltage Range Full Input Common-Mode Range Full 1.1 AVDD V High Level Input Voltage Full 1.2 3.6 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full −10 +10 μA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ

SYNC INPUT

Logic Compliance CMOS Internal Bias Full 1.2 V Input Voltage Range Full AGND − 0.3 AVDD + 1.6 V High Level Input Voltage Full 1.2 3.6 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full −10 +10 μA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ

LOGIC INPUT (CSB)1

High Level Input Voltage Full 1.22 3.6 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 40 132 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF

LOGIC INPUT (SCLK/DFS)2

High Level Input Voltage Full 1.22 3.6 V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 3.3 V) Full −92 −135 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF

LOGIC INPUTS/OUTPUTS (SDIO/DCS, SMI SDFS)1

High Level Input Voltage Full 1.22 3.6 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 38 128 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF

LOGIC INPUTS/OUTPUTS (SMI SDO/OEB, SMI SCLK/PDWN)2

High Level Input Voltage Full 1.22 3.6 V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 3.3 V) Full −90 −134 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF

AGND − 0.3

AVDD + 1.6 V

Rev. B | Page 9 of 52

AD9640

Parameter Temperature Min Typ Max Unit

DIGITAL OUTPUTS

CMOS Mode—DRVDD = 3.3 V

High Level Output Voltage (IOH = 50 μA) Full 3.29 V High Level Output Voltage (IOH = 0.5 mA) Full 3.25 V Low Level Output Voltage (IOL = 1.6 mA) Full 0.2 V Low Level Output Voltage (IOL = 50 μA) Full 0.05 V

CMOS Mode—DRVDD = 1.8 V

High Level Output Voltage (IOH = 50 μA) Full 1.79 V High Level Output Voltage (IOH = 0.5 mA) Full 1.75 V Low Level Output Voltage (IOL = 1.6 mA) Full 0.2 V Low Level Output Voltage (IOL = 50 μA) Full 0.05 V

LVDS Mode—DRVDD = 1.8 V

Differential Output Voltage (VOD), ANSI Mode Full 250 350 450 mV Output Offset Voltage (VOS), ANSI Mode Full 1.15 1.25 1.35 V Differential Output Voltage (VOD), Reduced Swing Mode Full 150 200 280 mV Output Offset Voltage (VOS), Reduced Swing Mode Full 1.15 1.25 1.35 V

1

Pull up.

2

Pull down.

SWITCHING SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND AD9640BCPZ-105

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted.

Table 6.

AD9640ABCPZ-80

AD9640BCPZ-80

Parameter Temp

Min Typ Max Min Typ Max

CLOCK INPUT PARAMETERS

Input Clock Rate Full 625 625 MHz

Conversion Rate

DCS Enabled1 Full 20 80 20 105 MSPS DCS Disabled1

CLK Period—Divide by 1 Mode (t

CLK

Full 10 80 10 105 MSPS

) Full 12.5 9.5 ns

CLK Pulse Width High

Divide by 1 Mode, DCS Enabled Full 3.75 6.25 8.75 2.85 4.75 6.65 ns Divide by 1 Mode, DCS Disabled Full 5.63 6.25 6.88 4.28 4.75 5.23 ns Divide by 2 Mode, DCS Enabled Full 1.6 1.6 ns Divide by 3 Through 8, DCS Enabled Full 0.8 0.8 ns

DATA OUTPUT PARAMETERS (DATA, FD)

CMOS Mode—DRVDD = 3.3 V

Data Propagation Delay (tPD)2 Full 2.2 4.5 6.4 2.2 4.5 6.4 ns DCO Propagation Delay (t

) Full 3.8 5.0 6.8 3.8 5.0 6.8 ns

DCO

Setup Time (tS) Full 6.25 5.25 ns Hold Time (tH) Full 5.75 4.25 ns

CMOS Mode—DRVDD = 1.8 V

Data Propagation Delay (tPD)2 DCO Propagation Delay (t

DCO

) Full 4.0 5.6 7.3 4.0 5.6 7.3 ns

Full 2.4 5.2 6.9 2.4 5.2 6.9 ns

LVDS Mode—DRVDD = 1.8 V

Data Propagation Delay (tPD)2 DCO Propagation Delay (t

DCO

) Full 5.4 7.0 8.4 5.2 6.4 7.6 ns

Full 3.0 3.7 4.4 3.0 3.7 4.4 ns

AD9640ABCPZ-105/

AD9640BCPZ-105

Unit

Rev. B | Page 10 of 52

AD9640

AD9640ABCPZ-80

AD9640BCPZ-80

Parameter Temp

Min Typ Max Min Typ Max

CMOS Mode Pipeline Delay (Latency) Full 12 12 Cycles LVDS Mode Pipeline Delay (Latency)

12/12.5 12/12.5 Cycles

Channel A/Channel B Aperture Delay (tA) Full 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 ps rms Wake-Up Time3 Full 350 350 μs

OUT-OF-RANGE RECOVERY TIME Full 2 2 Cycles

1

Conversion rate is the clock rate after the divider.

2

Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.

3

Wake-up time is dependent on the value of the decoupling capacitors.

SWITCHING SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND AD9640BCPZ-150

AVDD = 1.8 V, DVDD = 1.8V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted.

Table 7.

AD9640ABCPZ-125/

AD9640BCPZ-125

Parameter Temperature

CLOCK INPUT PARAMETERS

Input Clock Rate Full 625 625 MHz Conversion Rate

DCS Enabled1 Full 20 125 20 150 MSPS

DCS Disabled1 CLK Period—Divide by 1 Mode (t

Full 10 125 10 150 MSPS

) Full 8 6.66 ns

CLK

CLK Pulse Width High

Divide by 1 Mode, DCS Enabled Full 2.4 4 5.6 2.0 3.33 4.66 ns

Divide by 1 Mode, DCS Disabled Full 3.6 4 4.4 3.0 3.33 3.66 ns

Divide by 2 Mode, DCS Enabled Full 1.6 1.6 ns

Divide by 3 Through 8, DCS Enabled Full 0.8 0.8 ns

DATA OUTPUT PARAMETERS (DATA, FD)

CMOS Mode—DRVDD = 3.3 V

Data Propagation Delay (tPD)2 Full 2.2 4.5 6.4 2.2 4.5 6.4 ns

DCO Propagation Delay (t

) Full 3.8 5.0 6.8 3.8 5.0 6.8 ns

DCO

Setup Time (tS) Full 4.5 3.83 ns

Hold Time (tH) Full 3.5 2.83 ns CMOS Mode—DRVDD = 1.8 V

Data Propagation Delay (tPD)2 DCO Propagation Delay (t

DCO

) Full 4.0 5.6 7.3 4.0 5.6 7.3 ns

Full 2.4 5.2 6.9 2.4 5.2 6.9 ns

LVDS Mode—DRVDD = 1.8 V

Data Propagation Delay (tPD)2

DCO Propagation Delay (t

DCO

) Full 5.0 6.2 7.4 4.8 5.9 7.3 ns

Full 3.0 3.8 4.5 3.0 3.8 4.5 ns

CMOS Mode Pipeline Delay (Latency) Full 12 12 Cycles LVDS Mode Pipeline Delay (Latency)

12/12.5 12/12.5 Cycles

Channel A/Channel B Aperture Delay (tA) Full 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 ps rms Wake-Up Time3 Full 350 350 μs

OUT-OF-RANGE RECOVERY TIME Full 3 3 Cycles

1

Conversion rate is the clock rate after the divider.

2

Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.

3

Wake-up time is dependent on the value of the decoupling capacitors.

Min Typ Max Min Typ Max

AD9640ABCPZ-105/

AD9640BCPZ-105

Unit

AD9640ABCPZ-150/

AD9640BCPZ-150

Unit

Rev. B | Page 11 of 52

AD9640

C

A

TIMING SPECIFICATIONS

Table 8.

Parameter Conditions Min Typ Max Unit

SYNC TIMING REQUIREMENTS

t

SYNC to rising edge of CLK setup time 0.24 ns

SSYNC

t

SYNC to rising edge of CLK hold time 0.40 ns

HSYNC

SPI TIMING REQUIREMENTS

tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns t

Period of the SCLK 40 ns

CLK

tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns t

SCLK pulse width high 10 ns

HIGH

t

SCLK pulse width low 10 ns

LOW

t

EN_SDIO

Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge

t

DIS_SDIO

Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge

SPORT TIMING REQUIREMENTS

t

Delay from rising edge of CLK+ to rising edge of SMI SCLK 3.2 4.5 6.2 ns

CSSCLK

t

Delay from rising edge of SMI SCLK to SMI SDO −0.4 0 +0.4 ns

SSCLKSDO

t

Delay from rising edge of SMI SCLK to SMI SDFS −0.4 0 +0.4 ns

SSCLKSDFS

Timing Diagrams

N+2

CLK+

CLK–

H A/B DAT

N+ 1

N

t

A

t

CLK

t

PD

N – 12 N – 11 N – 9 N – 8 N – 7 N – 6 N – 5 N – 4

N – 13

N+ 3

N – 10

N+ 4

N+ 5

N+ 6

10 ns

N+ 8

N+ 7

CH A/B FAST

DETECT

DCOA/DCOB

t

S

N – 1 N + 2 N + 3 N + 4 N + 5 N + 6N – 3 N – 2

t

H

N

N + 1

t

DCO

t

CLK

06547-021

Figure 2. CMOS Output Mode Data and Fast Detect Output Timing (Fast Detect Mode 0)

Rev. B | Page 12 of 52

AD9640

C

A

N

t

A

CLK+

CLK–

H A/CH B DAT

CH A/CH B FAST

DETECT

DCO+

DCO–

t

PD

ABABABABABABABABA AB

N – 12 N – 11 N – 9 N – 8 N – 7 N – 6 N – 5 N – 4

N – 13

ABABABABABABABABA AB

N – 6 N – 5 N – 3 N – 2 N – 1 N N + 1 N + 2N – 7

N + 1

N + 2

t

CLK

N + 3

N – 10

N – 4

N + 4

t

DCO

N + 5

N + 6

t

CLK

N + 7

N + 8

06547-089

Figure 3. LVDS Mode Data and Fast Detect Output Timing (Fast Detect Mode 1 Through Fast Detect Mode 5)

CLK+

CLK–

SMI SCLK

SMI SDFS

t

CSSCLK

t

HSYNC

SYNC

t

SSYNC

Figure 4. SYNC Input Timing Requirements

t

SSCLKSDFS

t

SSCLKSDO

DATA DATASMI SDO

Figure 5. Signal Monitor SPORT Output Timing (Divide by 2 Mode)

06547-072

06547-082

Rev. B | Page 13 of 52

AD9640

ABSOLUTE MAXIMUM RATINGS

Table 9.

Parameter Rating

ELECTRICAL

AVDD, DVDD to AGND −0.3 V to +2.0 V DRVDD to DRGND −0.3 V to +3.9 V AGND to DRGND −0.3 V to +0.3 V AVDD to DRVDD −3.9 V to +2.0 V VIN+A/VIN+B, VIN−A/VIN−B to AGND −0.3 V to AVDD + 0.2 V CLK+, CLK− to AGND −0.3 V to +3.9 V SYNC to AGND −0.3 V to +3.9 V VREF to AGND −0.3 V to AVDD + 0.2 V SENSE to AGND −0.3 V to AVDD + 0.2 V CML to AGND −0.3 V to AVDD + 0.2 V RBIAS to AGND −0.3 V to AVDD + 0.2 V CSB to AGND −0.3 V to +3.9 V SCLK/DFS to DRGND −0.3 V to +3.9 V SDIO/DCS to DRGND −0.3 V to DRVDD + 0.3 V SMI SDO/OEB −0.3 V to DRVDD + 0.3 V SMI SCLK/PDWN −0.3 V to DRVDD + 0.3 V SMI SDFS −0.3 V to DRVDD + 0.3 V D0A/D0B through D13A/D13B to

DRGND

FD0A/FD0B through FD3A/FD3B to

DRGND

DCOA/DCOB to DRGND

−0.3 V to DRVDD + 0.3 V

ENVIRONMENTAL

Operating Temperature Range

−40°C to +85°C

(Ambient)

Maximum Junction Temperature

150°C

Under Bias

Storage Temperature Range

−65°C to +150°C

(Ambient)

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the customer board increases the reliability of the solder joints and maximizes the thermal capability of the package.

Table 10. Thermal Resistance

Airflow Package Typ e

64-lead LFCSP 9 mm × 9 mm

Veloc ity

(m/s)

1, 2

θ

JA

1, 3

θ

JC

1, 4

θ

Unit

JB

0 18.8 0.6 6.0 °C/W

1.0 16.5 °C/W

2.0 15.8 °C/W

1

JEDEC 51-7, plus JEDEC 25-5 2S2P test board.

2

Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

3

Per MIL-Std 883, Method 1012.1.

4

Per JEDEC JESD51-8 (still air).

Typical θJA is specified for a 4-layer PCB with a solid ground plane. As shown, airflow improves heat dissipation, which reduces θ

. In addition, metal in direct contact with the

JA

package leads from metal traces, through holes, ground, and power planes, reduces the θ

.

JA

ESD CAUTION

Rev. B | Page 14 of 52

AD9640

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

DRGND

D5B

D4B

D3B

D2B

D1B

D0B (LSB)

DVDD

FD3B

FD2B

FD1B

FD0B

SYNC

CSB

CLK–

646362616059585756555453525150

CLK+ 49

DRVDD

D6B D7B D8B

D9B D10B D11B D12B

D13B (MSB)

DCOB

10

DCOA

D1A D2A D3A D4A

11 12 13 14 15 16

D0A (LSB)

NOTES

1. NC = NO CONNEC T.

2. THE EXPOSED THERMAL PAD ON THE BO TTO M OF THE PACKAGE PROVIDES T HE ANALOG GROUND FOR THE PART. THIS EXPOSE D PAD MUST BE CONNECT ED TO

GROUND FOR PROPER OPERATION.

PIN 1

1

INDICATOR

2 3 4 5 6 7 8 9

EXPOSED PADDL E , PIN 0 (BOTTO M OF PACKAGE)

AD9640

PARALLEL CMOS

TOP VIEW

(Not to S cale)

171819202122232425262728293031

D5A

D6A

D7A

D8A

D9A

D11A

D10A

D12A

FD0A

DRGND

DVDD

DRVDD

FD1A

D13A (MSB)

48

SCLK/DFS

47

SDIO/DCS

46

AVDD

45

AVDD

44

VIN+B

43

VIN–B

42

RBIAS

41

CML

40

SENSE

39

VREF

38

VIN–A

37

VIN+A

36

AVDD

35

SMI SDFS

34

SMI SCLK/PDWN

33

SMI SDO/OEB

32

FD2A

FD3A

06547-002

Figure 6. Pin Configuration, LFCSP Parallel CMOS (Top View)

Table 11. Pin Function Descriptions (Parallel CMOS Mode)

Pin No. Mnemonic Type Description

ADC Power Supplies 20, 64 DRGND Ground Digital Output Ground. 1, 21 DRVDD Supply Digital Output Driver Supply (1.8 V to 3.3 V). 24, 57 DVDD Supply Digital Power Supply (1.8 V Nominal). 36, 45, 46 AVDD Supply Analog Power Supply (1.8 V Nominal). 0

AGND, Exposed Pad

Ground

The exposed thermal pad on the bottom of the package provides the analog ground

for the part. This exposed pad must be connected to ground for proper operation. ADC Analog 37 VIN+A Input Differential Analog Input Pin (+) for Channel A. 38 VIN−A Input Differential Analog Input Pin (−) for Channel A. 44 VIN+B Input Differential Analog Input Pin (+) for Channel B. 43 VIN−B Input Differential Analog Input Pin (−) for Channel B. 39 VREF Input/Output Voltage Reference Input/Output. 40 SENSE Input Voltage Reference Mode Select. See Table 14 for details. 42 RBIAS Input/Output External Reference Bias Resistor. 41 CML Output Common Mode Level Bias Output for Analog Inputs. 49 CLK+ Input ADC Clock Input—True. 50 CLK− Input ADC Clock Input—Complement.

Rev. B | Page 15 of 52

AD9640

Pin No. Mnemonic Type Description

ADC Fast Detect Outputs 29 FD0A Output Channel A Fast Detect Indicator. See Tabl e 18 for details. 30 FD1A Output Channel A Fast Detect Indicator. See Tabl e 18 for details. 31 FD2A Output Channel A Fast Detect Indicator. See Tabl e 18 for details. 32 FD3A Output Channel A Fast Detect Indicator. See Tabl e 18 for details. 53 FD0B Output Channel B Fast Detect Indicator. See Tabl e 18 for details. 54 FD1B Output Channel B Fast Detect Indicator. See Tabl e 18 for details. 55 FD2B Output Channel B Fast Detect Indicator. See Tabl e 18 for details. 56 FD3B Output Channel B Fast Detect Indicator. See Tabl e 18 for details. Digital Inputs 52 SYNC Input Digital Synchronization Pin. Slave mode only. Digital Outputs 12 D0A (LSB) Output Channel A CMOS Output Data. 13 D1A Output Channel A CMOS Output Data. 14 D2A Output Channel A CMOS Output Data. 15 D3A Output Channel A CMOS Output Data. 16 D4A Output Channel A CMOS Output Data. 17 D5A Output Channel A CMOS Output Data. 18 D6A Output Channel A CMOS Output Data. 19 D7A Output Channel A CMOS Output Data. 22 D8A Output Channel A CMOS Output Data. 23 D9A Output Channel A CMOS Output Data. 25 D10A Output Channel A CMOS Output Data. 26 D11A Output Channel A CMOS Output Data. 27 D12A Output Channel A CMOS Output Data. 28 D13A (MSB) Output Channel A CMOS Output Data. 58 D0B (LSB) Output Channel B CMOS Output Data. 59 D1B Output Channel B CMOS Output Data. 60 D2B Output Channel B CMOS Output Data. 61 D3B Output Channel B CMOS Output Data. 62 D4B Output Channel B CMOS Output Data. 63 D5B Output Channel B CMOS Output Data. 2 D6B Output Channel B CMOS Output Data. 3 D7B Output Channel B CMOS Output Data. 4 D8B Output Channel B CMOS Output Data. 5 D9B Output Channel B CMOS Output Data. 6 D10B Output Channel B CMOS Output Data. 7 D11B Output Channel B CMOS Output Data. 8 D12B Output Channel B CMOS Output Data. 9 D13B (MSB) Output Channel B CMOS Output Data. 11 DCOA Output Channel A Data Clock Output. 10 DCOB Output Channel B Data Clock Output. SPI Control 48 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. 47 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer in External Pin Mode. 51 CSB Input SPI Chip Select (Active Low). Serial Port 33 SMI SDO/OEB Input/Output Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External Pin Mode.

35 SMI SDFS Output Signal Monitor Serial Data Frame Sync. 34 SMI SCLK/PDWN Input/Output Signal Monitor Serial Clock Output/Power-Down Input in External Pin Mode.

Rev. B | Page 16 of 52

ANALOG DEVICES AD9640 Service Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

SPECIFICATIONS

DIGITAL SPECIFICATIONS

TIMING SPECIFICATIONS

Timing Diagrams

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS