ANALOG DEVICES AD9600 Service Manual

10-Bit, 105 MSPS/125 MSPS/150 MSPS,

www.BDTIC.com/ADI

1.8 V Dual Analog-to-Digital Converter

FEATURES

SNR = 60.6 dBc (61.6 dBFS) to 70 MHz at 150 MSPS SFDR = 81 dBc to 70 MHz at 150 MSPS Low power: 825 mW at 150 MSPS

1.8 V analog supply operation

1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS supply Integer 1 to 8 input clock divider Intermediate frequency (IF) sampling frequenci Internal analog-to-digital converter (ADC) voltage reference Integrated ADC sample-and-hold inputs Flexible analog input: 1 V p-p to 2 V p-p range Differential analog inputs with 650 MHz bandwidth ADC clock duty cycle stabilizer 95 dB channel isolation/crosstalk Serial port control User-configurable built-in self-test (BIST) capability Energy-saving power-down modes Integrated receive features

Fast detect/threshold bits Composite signal monitor

APPLICATIONS

Point-to-point radio receivers (GPSK, QAM) Diversity radio systems

es up to 450 MHz

FUNCTIONAL BLOCK DIAGRAM

FD[0:3]A

AD9600

I/Q demodulation systems Smart antenna systems Digital predistortion General-purpose software radios Broadband data applications Data acquisition Nondestructive testing

PRODUCT HIGHLIGHTS

1. Integrated dual, 10-bit, 150 MSPS/125 MSPS/105 MSPS ADC.

ast overrange detect and signal monitor with serial output.

2. F

3. Si

gnal monitor block with dedicated serial output mode.

4. P

roprietary differential input maintains excellent SNR

performance for input frequencies up to 450 MHz.

5. The AD9600 op

features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families.

6. A st

andard serial port interface supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down mode, and voltage reference mode.

7. Th

e AD9600 is pin compatible with the AD9627-11, AD9627,

AD9640, allowing a simple migration from 10 bits to

and 11 b

its, 12 bits, or 14 bits.

SCLK/

SDIO/

DFS

DCS

erates from a single 1.8 V supply and

DRVDDDVDDAVDD CSB

FD BITS/THRESHOLD

AD9600

VIN + A

VIN – A

VREF

SENSE

CML

VIN – B

VIN + B

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

SHA ADC

–+

REFERENCE

SELECT

SHA

MULTICHIP

SYNC

NOTES

1. PIN NAMES ARE F OR THE CMOS PIN CONFIGURATION O NLY; SEE FIGURE 7 FOR LVDS PIN NAMES.

DETECT

SIGNAL

MONITOR

ADC

FD BITS/THRESHOLD

DETECT

FD[0:3]B

SPI

D9A

PROGRAMMING DATA

DIVIDE 1

TO 8

DUTY CYCLE

STABLIZER

SERIAL MONITOR

DATA

SERIAL MONITOR

INTERFACE

SMI

SDFS

Figure 1.

SCLK/ PDWN

SDO/

OEB

CMOS/LV DS

DCO

GENERATION

CMOS/ LVDS

DRGNDSYNCAGND SMI

D0A

OUTPUT BUFFER

CLK+

CLK–

DCOA

DCOB

D9B

D0B

OUTPUT BUFF ER

6909-001

AD9600

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REVISION HISTORY

11/07—Revision 0: Initial Version

Rev. 0 | Page 2 of 72

AD9600

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GENERAL DESCRIPTION

The AD9600 is a dual, 10-bit, 105 MSPS/125 MSPS/150 MSPS ADC. It is designed to support communications applications where low cost, small size, and versatility are desired.

The dual ADC core features a multistage, differential pipelined

rchitecture with integrated output error correction logic. Each

a ADC features wide bandwidth, differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.

The AD9600 has several functions that simplify the automated ga

in control (AGC) function in a communications receiver. For example, the fast detect feature allows fast overrange detection by outputting four bits of input level information with very short latency.

In addition, the programmable threshold detector allows monit

oring the amplitude of the incoming signal with short latency, using the four fast detect bits of the ADC. If the input signal level exceeds the programmable threshold, the fine upper threshold indicator goes high. Because this threshold is set from the four MSBs, the user can quickly adjust the system gain to avoid an overrange condition.

Another AGC-related function of the AD9600 is the signal

onitor. This block allows the user to monitor the composite

m magnitude of the incoming signal, which aids in setting the gain to optimize the dynamic range of the overall system.

The ADC output data can be routed directly to the two external 10-b

it output ports. These outputs can be set from 1.8 V to 3.3 V CMOS or 1.8 V LVDS. In addition, flexible power-down options allow significant power savings.

Rev. 0 | Page 3 of 72

AD9600

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SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect output pins disabled, signal monitor disabled, unless otherwise noted.

Table 1.

AD9600BCPZ-105 AD9600BCPZ-125 AD9600BCPZ-150

Parameter Temp

RESOLUTION Full 10 10 10 Bits ACCURACY

No Missing Codes Full Guaranteed Guaranteed Guaranteed Offset Error Full ±0.3 ±0.7 ±0.3 ±0.7 ±0.3 ±0.7 % FSR Gain Error Full −3.6 −2.2 −1.0 −4.0 −2.5 −1.3 −4.3 −3.0 −1.6 % FSR Differential Nonlinearity (DNL)

1

Full ±0.2 ±0.2 ±0.2 LSB

25°C ±0.1 ±0.1 ±0.1 LSB

Integral Nonlinearity (INL)

1

Full ±0.3 ±0.3 ±0.4 LSB 25°C ±0.1 ±0.1 ±0.1 LSB MATCHING CHARACTERISTICS

Offset Error Full ±0.3 ±0.7 ±0.3 ±0.7 ±0.2 ±0.7 % FSR Gain Error Full ±0.2 ±0.8 ±0.3 ±0.8 ±0.2 ±0.8 % FSR

TEMPERATURE DRIFT

Offset Error Full ±15 ±15 ±15 ppm/°C Gain Error Full ±95 ±95 ±95 ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage Error (1 V Mode) Full ±5 ±16 ±5 ±16 ±5 ±16 mV Load Regulation @ 1.0 mA Full 7 7 7 mV

INPUT-REFERRED NOISE

VREF = 1.0 V 25°C 0.1 0.1 0.1 LSB rms

ANALOG INPUT

Input Span, VREF = 1.0 V Full Input Capacitance

2

Full VREF INPUT RESISTANCE Full 6 6 6 kΩ POWER SUPPLIES

Supply Voltage

AVDD, DVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD (CMOS Mode) Full 1.7 3.3 3.6 1.7 3.3 3.6 1.7 3.3 3.6 V

Supply Current

1, 3

I

AVDD

4

1, 3,

I

DVDD

I

(3.3 V CMOS) Full

DRVDD

I

(1.8 V CMOS) Full

DRVDD

I

(1.8 V LVDS)

DRVDD

Full

POWER CONSUMPTION

DC Input Full Sine Wave Input

1

DRVDD = 1.8 V Full DRVDD = 3.3 V Full

Standby Power

4

Full

Power-Down Power Full

1

Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.

2

Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 8 for the equivalent analog input structure.

3

The maximum limit applies to the combination of I

4

Standby power is measured with a dc input and the CLK+ and CLK− pins inactive (set to AVDD or AGND).

Min Typ Max Min Typ Max Min Typ Max Unit

and I

DVDD

currents.

AVDD

2 8

310 365 385 455 419 495 mA 34 365 42 455 50 495 mA 35 15 42

600 650 750 800 825 890 mW

645 740 68

2.5 6 2.5 6 2.5 6 mW

Rev. 0 | Page 4 of 72

2 2 V p-p 8 8 pF

36 42 mA 18 22 mA 44 46 mA

813 892 mW 900 990 mW 77 77 mW

AD9600

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AC SPECIFICATIONS

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect output pins disabled, signal monitor disabled, unless otherwise noted.

Table 2.

Parameter

SIGNAL-TO-NOISE RATIO (SNR)

fIN = 2.3 MHz 25°C 60.7 60.6 60.6 dB fIN = 70 MHz 25°C 60.6 60.6 60.6 dB Full 60.3 60.3 fIN = 140 MHz 25°C 60.6 60.6 60.5 dB fIN = 220 MHz 25°C

SIGNAL-TO-NOISE AND DISTORTION (SINAD)

fIN = 2.3 MHz 25°C 60.6 fIN = 70 MHz 25°C 60.5 Full 60.2 fIN = 140 MHz 25°C 60.5 fIN = 220 MHz 25°C 60.4 60.4 60.3 dB

EFFECTIVE NUMBER OF BITS (ENOB)

fIN = 2.3 MHz 25°C fIN = 70 MHz 25°C fIN = 140 MHz 25°C fIN = 220 MHz 25°C

WORST SECOND OR THIRD HARMONIC

fIN = 2.3 MHz 25°C fIN = 70 MHz 25°C Full fIN = 140 MHz 25°C fIN = 220 MHz 25°C

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

fIN = 2.3 MHz 25°C fIN = 70 MHz 25°C Full 72.0 fIN = 140 MHz 25°C fIN = 220 MHz 25°C

WORST OTHER HARMONIC OR SPUR

fIN = 2.3 MHz 25°C fIN = 70 MHz 25°C Full fIN = 140 MHz 25°C fIN = 220 MHz 25°C

TWO-TONE SFDR

fIN = 29.1 MHz, 32.1 MHz (−7 dBFS ) 25°C

fIN = 169.1 MHz, 172.1 MHz (−7 dBFS ) 25°C CROSSTALK ANALOG INPUT BANDWIDTH 25°C

1

See AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

2

Crosstalk is measured at 100 MHz with −1 dBFS on one channel and no input on the alternate channel.

1

2

Temp

Full

AD9600BCPZ-105 AD9600BCPZ-125 AD9600BCPZ-150

Min Typ Max Min Typ Max Min Typ Max

60.5

9.9

−87.0

−85.0

−84.0

−83.0

85.5

85.0

83.0

81.0

−92

−88

−86

84 82 95 650

−72.0

−81

60.5 60.4 dB

60.5 60.5 dB

60.2

60.5 60.4 dB

9.9

−86.5

−85.0

−84.0

−83.0

85.5

85.0

72.0

84.0

81.0

−92

-88

−86

84 82 95 650

60.3 dB

60.1 dB

−72.0

72.0

−81

9.9

−88.5

−84.0

−83.5

−77

85.5

84.0

83.5 77

−92

−88

−86

84 82 95 650

−72.0 dBc

−80 dBc

Unit

Bits Bits Bits Bits

dBc dBc

dBc dBc dBc dBc dBc

dBc dBc

dBc dBc dB MHz

Rev. 0 | Page 5 of 72

AD9600

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DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted.

Table 3.

Parameter Temperature Min Typ Max Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 1.2 V Differential Input Voltage Full 0.2 6 V p-p Input Voltage Range Full GND − 0.3 AVDD + 1.6 V Input Common-Mode Range Full 1.1 AVDD V High Level Input Voltage Full 1.2 3.6 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full −10 +10 μA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ

SYNC INPUT

Logic Compliance CMOS Internal Bias Full 1.2 V Input Voltage Range Full GND − 0.3 AVDD + 1.6 V High Level Input Voltage Full 1.2 3.6 V Low Level Input Voltage Full 0 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full −10 +10 μA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ

LOGIC INPUT (CSB)1

High Level Input Voltage Full 1.22 3.6 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 40 132 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF

LOGIC INPUT (SCLK/DFS)2

High Level Input Voltage Full 1.22 3.6 V Low Level Input Voltage Full 0 0.6 V High Level Input Current (VIN = 3.3 V) Full −92 −135 μA Low Level Input Current Full −10 +10 μA Input Resistance Full 26 kΩ Input Capacitance Full 2 pF

LOGIC INPUTS/OUTPUTS (SDIO/DCS, SMI SDFS)

High Level Input Voltage Full 1.22 3.6 V Low Level Input Voltage Full 0 0.6 V High Level Input Current Full −10 +10 μA Low Level Input Current Full 38 128 μA Input Resistance Full 26 kΩ Input Capacitance Full 5 pF

1

Rev. 0 | Page 6 of 72

AD9600

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Parameter Temperature Min Typ Max Unit

LOGIC INPUTS/OUTPUTS (SMI SDO/OEB, SMI SCLK/PDWN)

High Level Input Voltage Full 1.22 3.6 V

Low Level Input Voltage Full 0 0.6 V

High Level Input Current (VIN = 3.3 V) Full −90 −134 μA

Low Level Input Current Full −10 +10 μA

Input Resistance Full 26 kΩ

Input Capacitance Full 5 pF DIGITAL OUTPUTS

CMOS Mode—DRVDD = 3.3 V

High Level Output Voltage (IOH = 50 μA) Full 3.29 V High Level Output Voltage (IOH = 0.5 mA) Full 3.25 V Low Level Output Voltage (IOL = 1.6 mA) Full 0.2 V Low Level Output Voltage (IOL = 50 μA) Full 0.05 V

CMOS Mode—DRVDD = 1.8 V

High Level Output Voltage (IOH = 50 μA) Full 1.79 V High Level Output Voltage (IOH = 0.5 mA) Full 1.75 V Low Level Output Voltage (IOL = 1.6 mA) Full 0.2 V Low Level Output Voltage (IOL = 50 μA) Full 0.05 V

LVDS Mode—DRVDD = 1.8 V

Differential Output Voltage (VOD), ANSI Mode Full 250 350 450 mV Output Offset Voltage (VOS), ANSI Mode Full 1.15 1.25 1.35 V Differential Output Voltage (VOD), Reduced Swing Mode Full 150 200 280 mV Output Offset Voltage (VOS), Reduced Swing Mode Full 1.15 1.25 1.35 V

1

Pull up.

2

Pull down.

2

Rev. 0 | Page 7 of 72

AD9600

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SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted.

Table 4.

AD9600BCPZ-105 AD9600BCPZ-125 AD9600BCPZ-150

Parameter Temp

CLOCK INPUT PARAMETERS

Input Clock Rate Full 625 625 625 MHz Conversion Rate

DCS Enabled Full 20 105 20 125 20 150 MSPS DCS Disabled Full 10 105 10 125 10 150 MSPS

CLK Period (t CLK Pulse Width High

Divide-by-1 Mode,

DCS Enabled

Divide-by-1 Mode,

DCS Disabled

Divide-by-2 Mode,

DCS Enabled

Divide-by-3 Through Divide-

by-8 Modes, DCS Enabled

DATA OUTPUT PARAMETERS

CMOS Mode—DRVDD = 3.3 V

Data Propagation Delay (tPD)1Full 2.2 4.5 6.4 2.2 4.5 6.4 2.2 4.5 6.4 ns DCO Propagation Delay (t Setup Time (tS) Full 5.25 4.5 3.83 ns Hold Time (tH) Full 4.25 3.5 2.83 ns

CMOS Mode—DRVDD = 1.8 V

Data Propagation Delay (tPD)1 DCO Propagation Delay (t Setup Time (tS) Full 5.25 4.5 3.83 ns Hold Time (tH) Full 4.25 3.5 2.83 ns

LVDS Mode—DRVDD = 1.8 V Full

Data Propagation Delay (tPD)1 DCO Propagation Delay (t

CMOS Mode Pipeline Delay

(Latency)

LVDS Mode Pipeline Delay

(Latency) Channel A/Channel B Aperture Delay (tA) Full 1.0 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 0.1 ps rms Wake-Up Time

OUT-OF-RANGE RECOVERY TIME Full 2 3 3 Cycles

1

Output propagation delay is measured from the CLK+ and CLK− pins 50% transition to the output data pins 50% transition, with 5 pF load.

2

Wake-up time is dependent on the value of the decoupling capacitors.

) Full 9.5 8 6.66 ns

CLK

Full 2.85 4.75 6.65 2.4 4 5.6 2.0 3.33 4.66 ns

Full 4.28 4.75 5.23 3.6 4 4.4 3.0 3.33 3.66 ns

Full 1.6 1.6 1.6 ns

Full 0.8 0.8 0.8 ns

) Full 3.8 5.0 6.8 3.8 5.0 6.8 3.8 5.0 6.8 ns

DCO

Full 2.4 5.2 6.9 2.4 5.2 6.9 2.4 5.2 6.9 ns

) Full 4.0 5.6 7.3 4.0 5.6 7.3 4.0 5.6 7.3 ns

DCO

2.0 4.8 6.3 2.0 4.8 6.3 2.0 4.8 6.3 ns

) Full 5.2 7.3 9.0 5.2 7.3 9.0 5.2 7.3 9.0 ns

DCO

Full 12 12 12 Cycles

Full 12/12.5 12/12.5 12/12.5 Cycles

2

Full 350 350 350 μs

Min Typ Max Min Typ Max Min Typ Max Unit

Rev. 0 | Page 8 of 72

AD9600

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TIMING CHARACTERISTICS

Table 5.

Parameter Conditions Min Typ Max Unit

SYNC TIMING REQUIREMENTS

t

SSYNC

t

HSYNC

SPI TIMING REQUIREMENTS

t

DS

t

DH

t

CLK

t

S

t

H

t

HIGH

t

LOW

t

EN_SDIO

t

DIS_SDIO

SPORT TIMING REQUIREMENTS

t

CSSCLK

t

SSCLKSDO

t

SSCLKSDFS

Setup time between SYNC and the rising edge of CLK+ 0.24 ns Hold time between SYNC and the rising edge of CLK+ 0.40 ns

Setup time between the data and the rising edge of SCLK 2 ns Hold time between the data and the rising edge of SCLK 2 ns Period of the SCLK 40 ns Setup time between CSB and SCLK 2 ns Hold time between CSB and SCLK 2 ns SCLK pulse width high 10 ns SCLK pulse width low 10 ns Time required for the SDIO pin to switch from an input to an output

10 ns

relative to the SCLK falling edge Time required for the SDIO pin to switch from an output to an input

10 ns

relative to the SCLK rising edge

Delay from the rising edge of CLK+ to the rising edge of SMI SCLK 3.2 4.5 6.2 ns Delay from the rising edge of SMI SCLK to SMI SDO −0.4 0 0.4 ns Delay from the rising edge of SMI SCLK to SMI SDFS −0.4 0 0.4 ns

TIMING DIAGRAMS

CH A/CH B DAT

CH A/CH B FAST

CLK+

CLK–

DETECT

DCOA/DCOB

N+2

N+ 1

N

t

A

t

CLK

t

PD

N – 12 N – 11 N – 9 N – 8 N – 7 N – 6 N – 5 N – 4

N – 13

N – 1 N + 2 N + 3 N + 4 N + 5 N + 6N – 3 N – 2

t

S

t

H

N+ 3

N – 10

N

t

N + 1

DCO

N+ 4

N+ 5

N+ 6

t

CLK

N+ 7

Figure 2. CMOS Output Mode Data and Fast Detect Output Timing

N+ 8

06909-012

Rev. 0 | Page 9 of 72

AD9600

S

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N

t

A

CLK+

CLK–

CH A/CH B DATA

CH A/CH B FAS T

DETECT

DCO+

DCO–

t

PD

ABABABABABABABABA AB

N – 12 N – 11 N – 9 N – 8 N – 7 N – 6 N – 5 N – 4

N – 13

ABABABABABABABABA AB

N – 6 N – 5 N – 3 N – 2 N – 1 N N + 1 N + 2N – 7

Figure 3. LVDS Mode Data and Fast Detect Output T

N+ 1

t

CLK

N+2

N+ 3

N – 10

N – 4

N+ 4

t

DCO

N+ 5

t

CLK

N+ 6

N+ 7

iming (Fast Detect Mode Select Bits = 000)

N+ 8

06909-089

CLK+

CLK–

MI SCLK/PDWN

SMI SDFS

t

SSYNC

SYNC

Figure 4. SYNC Input Timing Requirements

t

CSSCLK

t

SSCLKSDFS

Figure 5. Signal Monitor SPORT Outpu

t

HSYNC

t

SSCLKSDO

DATA DATASMI SDO/OEB

t Timing (Divide-by-2 Mode)

06909-072

06909-082

Rev. 0 | Page 10 of 72

AD9600

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ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

ELECTRICAL

AVDD, DVDD to AGND −0.3 V to +2.0 V DRVDD to DRGND −0.3 V to +3.9 V AGND to DRGND −0.3 V to +0.3 V AVDD to DRVDD −3.9 V to +2.0 V VIN + A/VIN + B, VIN − A/VIN − B to

−0.3 V to AVDD + 0.2 V

AGND CLK+, CLK− to AGND −0.3 V to +3.9 V SYNC to AGND −0.3 V to +3.9 V VREF to AGND −0.3 V to AVDD + 0.2 V SENSE to AGND −0.3 V to AVDD + 0.2 V CML to AGND −0.3 V to AVDD + 0.2 V RBIAS to AGND −0.3 V to AVDD + 0.2 V CSB to AGND −0.3 V to +3.9 V SCLK/DFS to DRGND −0.3 V to +3.9 V SDIO/DCS to DRGND −0.3 V to DRVDD + 0.3 V SMI SDO/OEB −0.3 V to DRVDD + 0.3 V SMI SCLK/PDWN −0.3 V to DRVDD + 0.3 V SMI SDFS −0.3 V to DRVDD + 0.3 V Output Data Pins to DRGND Fast Detect Output Pins to DRGND Data Clock Output Pins to DRGND

1

−0.3 V to DRVDD + 0.3 V

2

−0.3 V to DRVDD + 0.3 V

3

−0.3 V to DRVDD + 0.3 V

ENVIRONMENTAL

Operating Temperature Range

−40°C to +85°C

(Ambient)

Maximum Junction Temperature

150°C

Under Bias

Storage Temperature Range

−65°C to +150°C

(Ambient)

1

The output data pins are D0A/D0B to D9A/D9B for the CMOS configuration

and D0+/D0− to D9+/D9− for the LVDS configuration.

2 The fast detect output pins are FD0A/FD0B to FD3A/FD3B for the CMOS

configuration and FD0+/FD0− to FD3+/FD3−.

3

The data clock output pins are DCOA and DCOB for the CMOS configuration

and DCO+ and DCO− for the LVDS configuration.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the customer board increases the reliability of the solder joints, maximizing the thermal capability of the package.

Table 7. Thermal Resistance

Airflow

locity

Package Type

64 Lead, 9 mm × 9 mm

LFCSP (CP-64-3)

Ve (m/s)

0 18.8 0.6 6.0 °C/W

1.0 16.5 °C/W

1, 2

1, 3

θ

JA

JC

1, 4

θ

Unit

JB

2.0 15.8 °C/W

1

Per JEDEC 51-7 standard and JEDEC 25-5 2S2P test board.

2

Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

3

Per MIL-Std 883, Method 1012.1.

4

Per JEDEC JESD51-8 (still air).

Typical θJA and θJC are specified for a 4-layer board in still air. Airflow increases heat dissipation, effectively reducing θ

JA

. In addition, metal (such as metal traces through holes, ground, and power planes) that is in direct contact with the package leads reduces the θ

.

JA

ESD CAUTION

Rev. 0 | Page 11 of 72

AD9600

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DRGND

D1B

D0B (LSB)

DNC

DVDD

FD3B

FD2B

FD1B

FD0B

SYNC

CSB

CLK–

CLK+

49

48

SCLK/DFS

47

SDIO/DCS

46

AVDD

45

AVDD

44

VIN + B

43

VIN – B

42

RBIAS

41

CML

40

SENSE

39

VREF

38

VIN – A

37

VIN + A

36

AVDD

35

SMI SDFS

34

SMI SCLK/PDWN

33

SMI SDO/OEB

DRVDD

D2B D3B D4B D5B D6B D7B D8B

(MSB) D9B

DCOB DCOA

DNC DNC DNC DNC

(LSB) D0A

646362616059585756555453525150

PIN 1

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

INDICATO R

EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE)

AD9600

PARALLEL CMOS

TOP VIEW

(Not to Scale)

DNC = DO NOT CONNECT

171819202122232425262728293031

D1A

D2A

D3A

D4A

D5A

D6A

D7A

D8A

FD0A

DRGND

DVDD

DRVDD

FD1A

(MSB) D9A

32

FD2A

FD3A

06909-002

Figure 6. Parallel CMOS Mode Pin Configuration (Top View)

Table 8. Parallel CMOS Mode Pin Function Descriptions

Pin No. Mnemonic Type Description

ADC Power Supplies

20, 64 DRGND Ground Digital Output Ground. 1, 21 DRVDD Supply Digital Output Driver Supply (1.8 V to 3.3 V). 24, 57 DVDD Supply Digital Power Supply (1.8 V Nominal). 36, 45, 46 AVDD Supply Analog Power Supply (1.8 V Nominal). 0 AGND Ground Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package.

ADC Inputs

37 VIN + A Input Differential Analog Input Pin (+) for Channel A. 38 VIN − A Input Differential Analog Input Pin (−) for Channel A. 44 VIN + B Input Differential Analog Input Pin (+) for Channel B. 43 VIN − B Input Differential Analog Input Pin (−) for Channel B. 39 VREF I/O Voltage Reference Input/Output. 40 SENSE Input Voltage Reference Mode Select (see Tab le 11 for details). 42 RBIAS Input External Reference Bias Resistor. 41 CML Output Common-Mode Level Bias Output for Analog Inputs. 49 CLK+ Input

ADC Master Clock True. The ADC clock can be driven using a single-ended CMOS (see Figure 60 and Figure 61 for the recommended connection).

50 CLK− Input

ADC Master Clock Complement. The ADC clock can be driven using a single-

nded CMOS (see Figure 60 and Figure 61 for the recommended connection).

e

ADC Fast Detect Outputs

29 FD0A Output Channel A Fast Detect Indicator (see Tab le 14 for details). 30 FD1A Output Channel A Fast Detect Indicator (see Tab le 14 for details). 31 FD2A Output Channel A Fast Detect Indicator (see Tab le 14 for details). 32 FD3A Output Channel A Fast Detect Indicator (see Tab le 14 for details). 53 FD0B Output Channel B Fast Detect Indicator (see Tab le 14 for details). 54 FD1B Output Channel B Fast Detect Indicator (see Tab le 14 for details). 55 FD2B Output Channel B Fast Detect Indicator (see Tab le 14 for details). 56 FD3B Output Channel B Fast Detect Indicator (see Tab le 14 for details).

Rev. 0 | Page 12 of 72

AD9600

www.BDTIC.com/ADI

Pin No. Mnemonic Type Description

Digital Inputs

52 SYNC Input Digital Synchronization Pin (Slave Mode Only).

Digital Outputs

16 to 19, 22, 23, 25 to 28

62, 63, 2 to 9 D0B to D9B Output Channel B CMOS Output Data. 11 DCOA Output Channel A Data Clock Output. 10 DCOB Output Channel B Data Clock Output.

SPI Control

48 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. 47 SDIO/DCS I/O SPI Serial Data Input and Output/Duty Cycle Stabilizer in External Pin Mode. 51 CSB Input SPI Chip Select (Active Low).

Signal Monitor Port

33 SMI SDO/OEB I/O

35 SMI SDFS Output Signal Monitor Serial Data Frame Sync. 34 SMI SCLK/PDWN I/O Signal Monitor Serial Clock Output/Power-Down Input in External Pin Mode.

Do Not Connect

12 to 15, 58 to 61 DNC N/A Do Not Connect.

D0A to D9A Output Channel A CMOS Output Data.

Signal Monitor Serial Data Output/Output Enable I External Pin Mode.

nput (Active Low) in

Rev. 0 | Page 13 of 72

AD9600

www.BDTIC.com/ADI

DRGND

DNC

FD3+

FD3–

FD2+

FD2–

DVDD

FD1+

FD1–

FD0+

FD0–

SYNC

CSB

CLK–

CLK+

49

48

SCLK/DFS

47

SDIO/DCS

46

AVDD

45

AVDD

44

VIN + B

43

VIN – B

42

RBIAS

41

CML

40

SENSE

39

VREF

38

VIN – A

37

VIN + A

36

AVDD

35

SMI SDFS

34

SMI SCLK/PDWN

33

SMI SDO/OEB

DRVDD

DNC DNC DNC DNC DNC DNC

(LSB) D0–

D0+ DCO– DCO+

D1–

D1+

D2–

D2+

D3–

646362616059585756555453525150

PIN 1

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

INDICATO R

EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE)

AD9600

PARALLEL LVDS

TOP VIEW

(Not to Scale)

DNC = DO NOT CONNECT

Figure 7. Interleaved Parallel LVDS M

171819202122232425262728293031

D5–

D6–

D7–

D4–

D3+

D5+

D4+

DRGND

DRVDD

DVDD

D8–

D6+

D7+

D8+

ode Pin Configuration (Top View)

32

D9–

(MSB) D9+

06909-003

Table 9. Interleaved Parallel LVDS Mode Pin Function Descriptions

Pin No. Mnemonic Type Description

ADC Power Supplies

20, 64 DRGND Ground Digital Output Ground. 1, 21 DRVDD Supply Digital Output Driver Supply (1.8 V to 3.3 V). 24, 57 DVDD Supply Digital Power Supply (1.8 V Nominal). 36, 45, 46 AVDD Supply Analog Power Supply (1.8 V Nominal). 0 AGND Ground Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package.

ADC Inputs

37 VIN + A Input Differential Analog Input Pin (+) for Channel A. 38 VIN − A Input Differential Analog Input Pin (−) for Channel A. 44 VIN + B Input Differential Analog Input Pin (+) for Channel B. 43 VIN − B Input Differential Analog Input Pin (−) for Channel B. 39 VREF I/O Voltage Reference Input/Output. 40 SENSE Input Voltage Reference Mode Select (see Table 11 for details). 42 RBIAS Input External Reference Bias Resistor. 41 CML Output Common-Mode Level Bias Output for Analog Inputs. 49 CLK+ Input

ADC Master Clock True. The ADC clock can be driven using a single-ended CMOS (see Figure 60 and Figure 61 for the recommended connection).

50 CLK− Input

ADC Master Clock Complement. The ADC clock can be driven using a single-ended CMOS (see Figure 60 and Figure 61 for the recommended connection).

ADC Fast Detect Outputs

54 FD0+ Output Channel A/Channel B LVDS Fast Detect Indicator 0 True (see Table 1 4 for full details). 53 FD0− Output

Channel A/Channel B LVDS Fast Detect Indicator 0 Complement (see Tabl e 14

or details).

f 56 FD1+ Output Channel A/Channel B LVDS Fast Detect Indicator 1 True (see Table 1 4 for details). 55 FD1− Output

Channel A/Channel B LVDS Fast Detect Indicator 1 Complement (see Table 14

or details).

f 59 FD2+ Output Channel A/Channel B LVDS Fast Detect Indicator 2 True (see Table 1 4 for details). 58 FD2− Output

Channel A/Channel B LVDS Fast Detect Indicator 2 Complement (see Table 14

or details).

f 61 FD3+ Output Channel A/Channel B LVDS Fast Detect Indicator 3 True (see Table 1 4 for details). 60 FD3− Output

Channel A/Channel B LVDS Fast Detect Indicator 3 Complement (see Tabl e 14

or details).

f

Rev. 0 | Page 14 of 72

AD9600

www.BDTIC.com/ADI

Pin No. Mnemonic Type Description

Digital Inputs

52 SYNC Input Digital Synchronization Pin (Slave Mode Only).

Digital Outputs

9 D0+ Output Channel A/Channel B LVDS Output Data 0 True. 8 D0− Output Channel A/Channel B LVDS Output Data 0 Complement. 13 D1+ Output Channel A/Channel B LVDS Output Data 1 True. 12 D1− Output Channel A/Channel B LVDS Output Data 1 Complement. 15 D2+ Output Channel A/Channel B LVDS Output Data 2 True. 14 D2− Output Channel A/Channel B LVDS Output Data 2 Complement. 17 D3+ Output Channel A/Channel B LVDS Output Data 3 True. 16 D3− Output Channel A/Channel B LVDS Output Data 3 Complement. 19 D4+ Output Channel A/Channel B LVDS Output Data 4 True. 18 D4− Output Channel A/Channel B LVDS Output Data 4 Complement. 23 D5+ Output Channel A/Channel B LVDS Output Data 5 True. 22 D5− Output Channel A/Channel B LVDS Output Data 5 Complement. 26 D6+ Output Channel A/Channel B LVDS Output Data 6 True. 25 D6− Output Channel A/Channel B LVDS Output Data 6 Complement. 28 D7+ Output Channel A/Channel B LVDS Output Data 7 True. 27 D7− Output Channel A/Channel B LVDS Output Data 7 Complement. 30 D8+ Output Channel A/Channel B LVDS Output Data 8 True. 29 D8− Output Channel A/Channel B LVDS Output Data 8 Complement. 32 D9+ Output Channel A/Channel B LVDS Output Data 9 True. 31 D9− Output Channel A/Channel B LVDS Output Data 9 Complement. 11 DCO+ Output Channel A/Channel B LVDS Data Clock Output True. 10 DCO− Output Channel A/Channel B LVDS Data Clock Output Complement.

SPI Control

48 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. 47 SDIO/DCS I/O SPI Serial Data Input and Output/Duty Cycle Stabilizer in External Pin Mode. 51 CSB Input SPI Chip Select (Active Low).

Signal Monitor Port

33 SMI SDO/OEB I/O

35 SMI SDFS Output Signal Monitor Serial Data Frame Sync. 34 SMI SCLK/PDWN I/O Signal Monitor Serial Clock Output/Power-Down Input in External Pin Mode.

Do Not Connect

2 to 7, 62, 63 DNC N/A Do Not Connect.

Signal Monitor Serial Data Output/Output Enable I External Pin Mode.

nput (Active Low) in

Rev. 0 | Page 15 of 72

AD9600

V

C

A

V

www.BDTIC.com/ADI

EQUIVALENT CIRCUITS

26kΩ

1kΩ

06909-008

LK+

IN

Figure 8. Analog Input Circuit

AVDD

1.2V

10kΩ 10kΩ

SCLK/DFS

06909-004

Figure 12. Equivalent SCLK/DFS Input Circuit

SENSE

CLK–

Figure 9. Equivalent Clock Input Circu

DRVDD

DRGND

Figure 10. Digital Output

DRVDD

26kΩ

SDIO/DCS

1kΩ

6909-005

it

6909-081

Figure 13. Equivalent SENSE Circuit

VDD

26kΩ

CSB

1kΩ

06909-009

06909-010

Figure 14. Equivalent CSB Input Circuit

AVDD

REF

06909-007

Figure 11. Equivalent SDIO/DCS Input Circuit

Rev. 0 | Page 16 of 72

6kΩ

Figure 15. Equivalent VREF Circuit

06909-011

AD9600

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, sample rate = 150 MSPS, DCS enabled, 1 V internal reference, 2 V p-p differential input, VIN = −1.0 dBFS, 64k sample, and T

0

–20

–40

= 25°C, unless otherwise noted.

A

150MSPS

2.3MHz @ –1dBFS SNR = 60.6dB (61. 6dBFS) ENOB = 9.9 BITS SFDR = 85.5dBc

–20

–40

0

150MSPS 140MHz @ –1dBFS SNR = 60.5dB (61. 5dBFS) ENOB = 9.8 BITS SFDR = 83.5d Bc

–60

SECOND HARMONIC

–80

AMPLITUDE ( dBFS)

–100

–120

Figure 16. AD9600-150 Single-Tone FFT with f

0

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

–120

Figure 17. AD9600-150 Single-Tone FFT with f

THIRD HARMONIC

0 10203040506070

FREQUENCY (MHz)

150MSPS

30.3MHz @ –1dBFS SNR = 60.6dB (61. 6dBFS) ENOB = 9.9 BITS SFDR = 84.0dBc

THIRD HARMONIC

FREQUENCY (MHz)

= 2.3 MHz

IN

= 30.3 MHz

IN

SECOND

HARMONIC

–60

–80

AMPLITUDE ( dBFS)

–100

–120

06909-029

Figure 19. AD9600-150 Single-Tone FFT with f

0

–20

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

06909-030

Figure 20. AD9600-150 Single-Tone FFT with f

SECOND HARMONIC

0 10203040506070

150MSPS 220MHz @ –1dBFS SNR = 60.4dB (61. 4dBFS) ENOB = 9.7 BITS SFDR = 77.0dBc

SECOND HARMONIC

0 10203040506070

THIRD HARMONIC

FREQUE NCY (MHz )

= 140 MHz

IN

THIRD HARMONIC

= 220 MHz

IN

06909-119

06909-120

0

150MSPS 70MHz @ –1dBFS SNR = 60.6dB (61. 6dBFS)

–20

ENOB = 9.8 BITS SFDR = 84.0dBc

–40

–60

SECOND HARMONIC

–80

AMPLITUDE ( dBFS)

–100

–120

0 10203040506070

FREQUE NCY (MHz )

Figure 18. AD9600-150 Single-Tone FFT with f

THIRD HARMONIC

IN

= 70 MHz

06909-118

Rev. 0 | Page 17 of 72

0

150MSPS 337MHz @ –1dBFS SNR = 60.2dB (61. 2dBFS)

–20

ENOB = 9.7 BITS SFDR = 74.0dBc

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

0 10203040506070

FREQUE NCY (MHz )

Figure 21. AD9600-150 Single-Tone FFT with f

THIRD HARMONIC

SECOND HARMONIC

IN

= 337 MHz

06909-121

AD9600

www.BDTIC.com/ADI

0

–20

–40

SECOND HARMONIC

–60

–80

AMPLITUDE ( dBFS)

THIRD HARMONIC

150MSPS 440MHz @ –1dBFS SNR = 60.0dB (61. 0dBFS) ENOB = 9.6 BITS SFDR = 70.0dBc

0

125MSPS

70.1MHz @ –1dBF S SNR = 60.6dB (61. 6dBFS)

–20

ENOB = 9.8 BITS SFDR = 85.0dBc

–40

–60

–80

AMPLITUDE ( dBFS)

THIRD HARMONIC

SECOND HARMONIC

–100

–120

0 10203040506070

Figure 22. AD9600-150 Single-Tone FFT with f

0

–20

–40

–60

SECOND HARMONIC

–80

AMPLITUDE ( dBFS)

–100

–120

THIRD HARMONIC

0 102030405060

Figure 23. AD9600-125 Single-Tone FFT with f

FREQUENCY (MHz)

125MSPS

2.3MHz @ –1dBFS SNR = 60.6dB (61. 6dBFS) ENOB = 9.8 BITS SFDR = 86.5dBc

FREQUENCY (MHz)

= 440 MHz

IN

= 2.3 MHz

IN

–100

–120

0 102030405060

06909-122

Figure 25. AD9600-125 Single-Tone FFT with f

0

–20

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

0 102030405060

06909-123

Figure 26. AD9600-125 Single-Tone FFT with f

FREQUENCY (MHz)

125MSPS

140.1MHz @ –1dBF S SNR = 60.6dB (61. 6dBFS) ENOB = 9.8 BITS SFDR = 84.0dBc

SECOND HARMONIC

FREQUENCY (MHz)

= 70.1 MHz

IN

THIRD HARMONIC

= 140.1 MHz

IN

06909-125

06909-126

0

125MSPS

30.3MHz @ –1dBF S SNR = 60.6dB (61. 6dBFS)

–20

ENOB = 9.8 BITS SFDR = 85.0dBc

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

0 102030405060

FREQUENCY (MHz)

Figure 24. AD9600-125 Single-Tone FFT with f

THIRD HARMONIC

SECOND HARMONIC

= 30.3 MHz

IN

06909-124

Rev. 0 | Page 18 of 72

0

125MSPS

220.1MHz @ –1dBF S SNR = 60.5dB (61. 5dBFS)

–20

ENOB = 9.7 BITS SFDR = 81.0dBc

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

0 102030405060

Figure 27. AD9600-125 Single-Tone FFT with f

THIRD HARMONIC

FREQUENCY (MHz)

SECOND HARMONIC

= 220.1 MHz

IN

06909-127

AD9600

–

www.BDTIC.com/ADI

120

95

100

80

60

85dB REFERENCE L INE

40

SNR/SFDR (dBc AND d Bm)

20

0

–60 –10–20–30–40–50 0

SNR (dBFS)

SNR (dBc)

AMPLITUDE (dBm)

Figure 28. AD9600-150 Single-Tone S

= 2.4 MHz

f

IN

100

80

SNR (dBFS)

60

85dB REFERENCE L INE

40

SNR/SFDR (dBc AND dBm)

20

SFDR (dBc)

0

–60 –10–20–30–40–50 0

AMPLI TUDE (d Bm)

Figure 29. AD9600-150 Single-Tone S

= 98.12 MHz

f

IN

SFDR (dBFS)

SFDR (dBc)

NR/SFDR vs. Input Amplitude (A

SFDR (dBFS)

SNR (dBc)

NR/SFDR vs. Input Amplitude (A

) with

IN

) with

IN

90

85

80

75

70

SNR/SFDR (d Bc)

65

60

55

0 50 100 150 200 250 300 350 400 450

06909-031

INPUT FREQUENCY (MHz)

Figure 31. AD9600-150 Single-Tone SNR/SFDR vs. Input Frequency (f

SFDR +25°C

SFDR +85°C

SNR +25°C SNR +85°C SNR –40°C

SFDR –40°C

) and

IN

06909-034

Temperature with12 V p-p Full Scale

2.5

–3.0

–3.5

–4.0

GAIN ERROR (%F SR)

–4.5

–5.0

–40 806040

06909-032

TEMPERATURE (°C)

GAIN

OFFSET

200–20

0.5

0.4

0.3

0.2

0.1

0

OFFSET ERROR (%FSR)

06909-132

Figure 32. AD9600-150 Gain and Offset vs. Temperature

95

90

85

80

75

70

SNR/SFDR (d Bc)

65

60

55

0 50 100 150 200 250 300 350 400 450

SFDR –40°C

INPUT FREQUENCY (MHz)

Figure 30. AD9600-150 Single-Tone SNR/SFDR vs. Input Frequency (f

SNR +25°C SNR +85°C SNR –40°C

SFDR +85°C

SFDR +25°C

) and

IN

06909-033

Temperature with 2 V p-p Full Scale

Rev. 0 | Page 19 of 72

0

–20

–40

–60

–80

SFDR/IMD3 ( dBc AND dBFS)

–100

–120

–60 –12–24–36–48

IMD3 (dBc)

SFDR (dBc)

SFDR (dBFS)

IMD3 (dBFS )

INPUT AMPLITUDE (dBF S)

Figure 33. AD9600-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (A

= 29.1 MHz, f

f

IN1

= 32.1 MHz, fS = 150 MSPS

IN2

) with

IN

06909-133

AD9600

www.BDTIC.com/ADI

–20

0

150MSPS

169.1MHz @ –7dBF S

172.1MHz @ –7dBF S SFDR = 83.1dBc (90.1dBFS )

0

SFDR (dBc)

–20

–40

IMD3 (dBc)

–60

SFDR (dBFS)

–80

SFDR/IMD3 ( dBc AND dBFS)

–100

–120

IMD3 (dBFS)

–60 –12–24–36–48

INPUT AMPLITUDE (dBFS)

Figure 34. AD9600-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (A

= 169.1 MHz, f

f

IN1

0

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

= 172.1 MHz, fS = 150 MSPS

IN2

) with

IN

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

0 10203040506070

06909-134

Figure 37. AD9600-150 Two-Tone SFDR/IMD3 vs. Input Frequency (f

= 169.1 MHz, f

f

IN1

0

–20

–40

–60

–80

AMPLITUDE (dBFS)

–100

INPUT FREQUENCY (MHz)

= 172.1 MHz, fS = 150 MSPS

IN2

NPR = 54.3dBc NOTCH @ 18. 5MHz NOTCH WIDTH = 3M Hz

) with

IN

06909-137

–120

0 15.36 30.72 46.08 61. 44

FREQUENCY (MHz)

Figure 35. AD9600-125 Two 64k WCDMA Carriers with

= 170 MHz, fS = 125 MSPS

f

IN

0

–20

–40

–60

–80

AMPLITUDE ( dBFS)

–100

–120

0 10203040506070

INPUT FREQUENCY (MHz)

150MSPS

29.1MHz @ –7dBF S

32.1MHz @ –7dBF S SFDR = 86.1dBc (93.1dBFS )

Figure 36. AD9600-150 Two-Tone SFDR/IMD3 vs. Input Frequency (f

= 29.1 MHz, f

f

IN1

= 32.1 MHz, fS = 150 MSPS

IN2

) with

IN

–120

07605040302010

06909-135

FREQUENCY (MHz)

0

06909-138

Figure 38. AD9600-150 Noise Power Ratio (NPR)

100

90

80

70

SNR/SFDR (dBc)

06909-136

SNR—SIDE A

60

50

0 25 50 75 100 125 150

Figure 39. AD9600-150 Single-Tone SNR/SFDR vs. Clock Frequency (f

f

SFDR—SIDE B

SFDR—SIDE A

SNR—SIDE B

ENCODE (MSPS)

= 2.3 MHz

IN1

) with

S

06909-035

Rev. 0 | Page 20 of 72

AD9600

www.BDTIC.com/ADI

12

10

8

0.10 LSB rms

100

95

SFDR DCS ON

90

85

6

4

NUMBER OF HIT S (1M)

2

0

OUTPUT CODE

Figure 40. AD9600 Grounded Input Histogram

0.10

0.05

0

INL ERROR (LSB)

–0.05

–0.10

0 128 256 384 512 640 768 896 1024

Figure 41. AD9600 INL with f

OUTPUT CODE

= 10.3 MHz

IN1

80

75

SNR/SFDR (d Bc)

SNR DCS ON

70

65

N + 3N + 2N + 1NN – 1N – 2N – 3

06909-140

60

20 806040

Figure 43. AD9600-150 SNR/SFDR vs. Duty Cycle with f

95

90

85

80

75

70

SNR/SFDR (d Bc)

65

60

55

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1. 1 1.2 1.3

06909-036

INPUT COMMON-MODE VOLTAGE (V)

Figure 44. AD9600-150 SNR/SFDR vs. Input

f

IN1

SFDR DCS OFF

SNR DCS OFF

DUTY CYCLE (%)

SFDR

SNR

Common-Mode Voltage (V

= 30 MHz

= 10.3 MHz

IN1

CM

06909-143

06909-144

) with

0.100

0.075

0.050

0.025

0

–0.025

DNL ERROR (LSB)

–0.050

–0.075

–0.100

0 128 256 384 512 640 768 896 1024

Figure 42. AD9600 DNL with f

OUTPUT CO DE

= 10.3 MHz

IN1

06909-037

Rev. 0 | Page 21 of 72

AD9600

www.BDTIC.com/ADI

THEORY OF OPERATION

The AD9600 dual ADC design can be used for diversity reception of signals, where the ADCs are operating identically on the same carrier but from two separate antennae. The ADCs can also be operated with independent analog inputs. The user can sample any f

/2 frequency segment from dc to 200 MHz

S

using appropriate low-pass or band-pass filtering at the ADC inputs with little loss in ADC performance. Although operation of up to 450 MHz analog input is permitted, ADC distortion increases at frequencies toward the higher end of this range.

In nondiversity applications, the AD9600 can be used as a

eband receiver where one ADC is used for I input data and

bas the other used for Q input data.

Synchronization capability is provided to allow synchronized

g among multiple channels or multiple devices.

timin

Programming and control of the AD9600 is accomplished using a 3-b

it SPI-compatible serial interface.

ADC ARCHITECTURE

The AD9600 architecture consists of a dual front-end sampleand-hold amplifier (SHA) followed by a pipelined switchedcapacitor ADC. The quantized outputs from each stage are combined into a final 10-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the clock.

Each stage of the pipeline excluding the last consists of a low

esolution flash ADC connected to a switched-capacitor digital-

r to-analog converter (DAC) and an interstage residue amplifier (a multiplying digital-to-analog converter (MDAC)). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC.

The input stage of each channel contains a differential SHA that ca

n be ac- or dc-coupled in differential or single-ended modes. The output-staging block aligns the data, corrects errors, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. During power-down, the output buffers go into a high impedance state.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9600 is a differential switchedcapacitor SHA that has been designed for optimum performance while processing a differential input signal.

The clock signal alternatively switches the SHA between sample

ode and hold mode (see Figure 45). When the SHA is

m swi

tched into sample mode, the signal source must be capable

of charging the sample capacitors and settling within one-half

Rev. 0 | Page 22 of 72

of a clock cycle. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. A shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC’s input; therefore, the precise values are dependent on the application.

In undersampling (IF sampling) applications, any shunt capacitors

ould be reduced. In combination with the driving source

sh impedance, the shunt capacitors limit the input bandwidth. See the

AN-742 Application Note, F

requency Domain Response of

Switched-Capacitor ADCs; the AN-827 Application Note, A

esonant Approach to Interfacing Amplifiers to Switched-Capacitor

R ADCs; and the Analog Dialogue article “Tr an s fo r me r- C o up le d

F

ront-End for Wideband A/D Converters” (Volume 39, April

2005

) for more information. In general, the precise values are

dependent on the application.

S

C

H

C

H

S

06909-013

VIN+

C

PIN, PAR

VIN–

C

PIN, PAR

Figure 45. Switched-Capac

S

C

S

H

C

S

itor SHA Input

For best dynamic performance, the source impedances driving VIN+ and VIN− should be matched.

An internal differential reference buffer creates positive and nega

tive reference voltages that define the input span of the ADC core.

The span of the ADC core is set by the buffer to 2 × VREF.

Input Common Mode

The analog inputs of the AD9600 are not internally dc-biased. Therefore, in ac-coupled applications, the user must provide this bias externally. Setting the device so that V

= 0.55 × AVDD is

CM

recommended for optimum performance, but the device can function over a wider range with reasonable performance (see Figure 44). An on-board common-mode voltage reference is

cluded in the design and is available from the CML pin.

in Optimum performance is achieved when the common-mode voltage of the analog input is set by the CML pin voltage (typically

0.55 × AVDD). The CML pin must be decoupled to ground by a

0.1 F capacitor as described in the

Applications section.

Differential Input Configurations

Optimum performance is achieved while driving the AD9600 in a differential input configuration. For baseband applications, the AD8138, ADA4937-2, and ADA4938-2 differential drivers p

rovide excellent performance and a flexible interface to the

ADC. The output common-mode voltage of the AD8138 is

ANALOG DEVICES AD9600 Service Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

SPECIFICATIONS

DC SPECIFICATIONS

AC SPECIFICATIONS

DIGITAL SPECIFICATIONS

SWITCHING SPECIFICATIONS

TIMING CHARACTERISTICS

TIMING DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

EQUIVALENT CIRCUITS

TYPICAL PERFORMANCE CHARACTERISTICS

THEORY OF OPERATION

ADC ARCHITECTURE

ANALOG INPUT CONSIDERATIONS

Input Common Mode

Differential Input Configurations