ANALOG DEVICES AD 9573 ARUZ Datasheet

PCI-Express Clock Generator IC,

V

FEATURES

Fully integrated VCO/PLL core

0.54 ps rms jitter from 12 kHz to 20 MHz

Input crystal frequency of 25 MHz
Preset divide ratios for 100 MHz, 33.33 MHz
LVDS/LVCMOS output format
Integrated loop filter
Space saving 4.4 mm × 5.0 mm TSSOP

0.235 W power dissipation

3.3 V operation

APPLICATIONS

Line cards, switches, and routers
CPU/PCIe applications
Low jitter, low phase noise clock generation

PLL Core, Dividers, Two Outputs

AD9573

GENERAL DESCRIPTION

The AD9573 provides a highly integrated, dual output clock
generator function including an on-chip PLL core that is
optimized for PCI-e applications. The integer-N PLL design
is based on the Analog Devices, Inc., proven portfolio of high
performance, low jitter frequency synthesizers to maximize line
card performance. Other applications with demanding phase
noise and jitter requirements also benefit from this part.

The PLL section consists of a low noise phase frequency
detector (PFD), a precision charge pump, a low phase noise
voltage controlled oscillator (VCO), and a preprogrammed
feedback divider and output divider.

By connecting an external 25 MHz crystal, output frequencies
of 100 MHz and 33.33 MHz can be locked to the input reference.
The output divider and feedback divider ratios are prepro­grammed for the required output rates. No external loop filter
components are required, thus conserving valuable design time
and board space.

The AD9573 is available in a 16-lead 4.4 mm × 5.0 mm TSSOP
and can be operated from a single 3.3 V supply. The temperature
range is −40°C to +85°C.

FUNCTIONAL BLOCK DIAGRAM

DD × 5

XTAL

OSC

AD9573

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

PFD/CP

3RD ORDER

LPF

Figure 1.

LDO

VCO

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2009 Analog Devices, Inc. All rights reserved.

OEGND × 5

LVDS

LVCMOS

DIVIDERS

100MHz

33.33MHz

07500-001

AD9573

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

PLL Characteristics ...................................................................... 3

Clock Output Jitter ....................................................................... 3

Clock Outputs ............................................................................... 3

Timing Characteristics ................................................................ 4

Control Pins .................................................................................. 4

Power .............................................................................................. 4

Crystal Oscillator .......................................................................... 4

Timing Diagrams .......................................................................... 4

Absolute Maximum Ratings ............................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution...................................................................................5

Pin Configuration and Function Descriptions ..............................6

Typical Performance Characteristics ..............................................7

Terminology .......................................................................................8

Theory of Operation .........................................................................9

Outputs ...........................................................................................9

Phase Frequency Detector (PFD) and Charge Pump ..........9

Power Supply ..................................................................................9

LVDS Clock Distribution .......................................................... 10

CMOS Clock Distribution ........................................................ 10

Power and Grounding Considerations and Power Supply

Rejection ...................................................................................... 10

Outline Dimensions ....................................................................... 11

Ordering Guide .......................................................................... 11



REVISION HISTORY

7/09—Revision 0: Initial Version

Rev. 0 | Page 2 of 12

AD9573

SPECIFICATIONS

Typical (typ) is given for VDD = 3.3 V ± 10%, TA = 25°C, unless otherwise noted. Minimum (min) and maximum (max) values are given
over full V

PLL CHARACTERISTICS

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

NOISE CHARACTERISTICS

PLL Noise (100 MHz Output)

@ 1 kHz −121 dBc/Hz

@ 10 kHz −128 dBc/Hz

@ 100 kHz −131 dBc/Hz

@ 1 MHz −144 dBc/Hz

@ 10 MHz −150 dBc/Hz

@ 30 MHz −151 dBc/Hz

PLL Noise (33.33 MHz Output)

@ 1 kHz −131 dBc/Hz

@ 10 kHz −137 dBc/Hz

@ 100 kHz −140 dBc/Hz

@ 1 MHz −150 dBc/Hz

@ 5 MHz −151 dBc/Hz

Spurious Content −70 dBc

PLL Figure of Merit −217.5 dBc/Hz

and TA (−40°C to +85°C) variation.

DD

CLOCK OUTPUT JITTER

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

LVDS OUTPUT ABSOLUTE TIME JITTER

RMS Jitter (100 MHz Output) 540 fsec 12 kHz to 20 MHz

CLOCK OUTPUTS

Table 3.

Parameter Min Typ Max Unit Test Conditions/Comments

LVDS CLOCK OUTPUT Termination = 100 Ω differential

Output Frequency 100 MHz

Differential Output Voltage (VOD) 500 640 700 mV

Delta VOD 25 mV

Output Offset Voltage (VOS) 1.125 1.25 1.375 V

Delta VOS 25 mV

Short-Circuit Current (ISA, ISB) 14 24 mA Output shorted to GND

Duty Cycle 45 55 %

LVCMOS CLOCK OUTPUT

Output Frequency 33.33 MHz

Output High Voltage (VOH) VS − 0.1 V Sourcing 1.0 mA current

Output Low Voltage (VOL) 0.1 V Sinking 1.0 mA current

Duty Cycle 45 55 %

Rev. 0 | Page 3 of 12

AD9573

TIMING CHARACTERISTICS

Table 4.

Parameter Min Typ Max Unit Test Conditions/Comments

LVDS Termination = 100 Ω differential; C

Output Rise Time, tRL 140 200 260 ps 20% to 80%, measured differentially
Output Fall Time, tFL 140 200 260 ps 80% to 20%, measured differentially

LVCMOS Termination = open

Output Rise Time, tRC 0.25 0.60 2.5 ns 20% to 80%; C
Output Fall Time, tFC 0.25 0.80 2.5 ns 80% to 20%; C

CONTROL PINS

Table 5.

Parameter Min Typ Max Unit Test Conditions/Comments

INPUT CHARACTERISTICS

OE Pin

OE has a 50 kΩ pull-down resistor.
Logic 1 Voltage 2.5 V
Logic 0 Voltage 0.8 V
Logic 1 Current 120 μA
Logic 0 Current 1.0 μA

POWER

LOAD

LOAD

= 5 pF
= 5 pF

LOAD

= 0 pF

Table 6.

Parameter Min Typ Max Unit Test Conditions/Comments

Power Supply 3.0 3.3 3.6 V
Power Dissipation 235 285 mW

CRYSTAL OSCILLATOR

Table 7.

Parameter Min Typ Max Unit Test Conditions/Comments

CRYSTAL SPECIFICATION Parallel resonant/fundamental mode

Frequency 25 MHz
ESR 40 Ω
Load Capacitance 18 pF
Phase Noise −138 dBc/Hz @ 1 kHz offset
Stability −30 +30 ppm

TIMING DIAGRAMS

DIFFERENTIAL
SIGNAL

80%

50%

20%

V

OD

SINGLE-E NDED

80%

20%

CMOS

5pF LO AD

t

RL

Figure 2. LVDS Timing, Differential

t

FL

07500-003

t

RC

Figure 3. LVCMOS Timing

t

FC

7500-004

Rev. 0 | Page 4 of 12

AD9573

A

ABSOLUTE MAXIMUM RATINGS

Table 8.

Parameter Rating

VDD, VDDA, VDDX, and VDD33 to GND −0.3 V to +3.6 V
XO1, XO2 to GND −0.3 V to VS + 0.3 V
100M, 100M, 33M to GND

−0.3 V to V

+ 0.3 V

S

Junction Temperature1 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (10 sec) 300°C

1

See Table 9 for θ

JA.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Thermal impedance measurements were taken on a 4-layer
board in still air in accordance with EIA/JESD51-7.

Table 9. Thermal Resistance

Package Type θJA Unit

16-Lead TSSOP 90.3 °C/W

ESD CAUTION

D9573

VS

VS

Cx

Cx

VS

CRYSTAL :
KYOCERA CX -49G
Cx = 33pF

0.1µF

1

1nF0.1µF

0.1µF

GNDA

2

VDDA

3

VDDX

4

XO1

5

XO2

6

GNDX

7

GNDA

8

VDDA

GND

100M

100M

VDD

VDD3

GND3

OE

33M

16

15

0.1µF

50Ω

50Ω

VS

VS

1µF

0.

R

T

100Ω

=

07500-002

14

13

12

11

3

10

9

3

Figure 4. Typical Application

Rev. 0 | Page 5 of 12

AD9573

G

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

GNDA

VDDA

VDDX

XO1

XO2

GNDX

NDA

VDDA

Table 10. Pin Function Descriptions

Pin No. Mnemonic Description

1, 7 GNDA Analog Ground.
2, 8 VDDA Analog Power Supply (3.3 V).
3 VDDX
4, 5 XO1, XO2
6 GNDX
9 GND33
10 33M
11 VDD33
12 VDD
13

100M
14 100M
15 GND
16

OE Output Enable (Active Low). Places both outputs in a high impedance state when high. This pin has a 50 kΩ

Crystal Oscillator Power Supply.
External 25 MHz Crystal.
Crystal Oscillator Ground.
Ground for LVCMOS Output.
LVCMOS Output at 33.33 MHz.
Power Supply for LVCMOS Output.
Power Supply for LVDS Output.
Complementary LVDS Output at 100 MHz.

LVDS Output at 100 MHz.
Ground for LVDS Output.

internal pull-down resistor.

1

2

3

4

5

6

7

8

AD9573

TOP VIEW

(Not to Scale)

16

15

14

13

12

11

10

9

OE

GND

100M

100M

VDD

VDD33

33M

GND33

Figure 5. Pin Configuration

07500-005

Rev. 0 | Page 6 of 12

AD9573

–

–

TYPICAL PERFORMANCE CHARACTERISTICS

115

–120

120

–125

–130

–135

–140

PHASE NOISE (d Bc/Hz)

–145

–150

–155

1k 10k 10 0k 1M 10M 100M

FREQUENCY OF FSET (Hz)

Figure 6. 100 MHz Phase Noise

07500-006

–130

–140

PHASE NOISE (d Bc/Hz)

–150

–160

1k 10k 10 0k 1M 10M 100M

FREQUENCY OF FSET (Hz)

Figure 7. 33.33 MHz Phase Noise

0-007
0750

Rev. 0 | Page 7 of 12

AD9573

TERMINOLOGY

Phase Jitter

An ideal sine wave can be thought of as having a continuous
and even progression of phase with time from 0 degrees to
360 degrees for each cycle. Actual signals, however, display a
certain amount of variation from ideal phase progression over
time. This phenomenon is called phase jitter. Although many
causes can contribute to phase jitter, one major cause is random
noise, which is characterized statistically as gaussian (normal)
in distribution.

This phase jitter leads to a spreading out of the energy of the
sine wave in the frequency domain, producing a continuous
power spectrum. This power spectrum is usually reported as
a series of values whose units are dBc/Hz at a given offset in
frequency from the sine wave (carrier). The value is a ratio
(expressed in dB) of the power contained within a 1 Hz
bandwidth with respect to the power at the carrier frequency.
For each measurement, the offset from the carrier frequency is
also given.

Phase Noise

When the total power contained within some interval of offset
frequencies (for example, 12 kHz to 20 MHz) is integrated, it is
called the integrated phase noise over that frequency offset
interval, and it can be readily related to the time jitter due to the
phase noise within that offset frequency interval.

Phase noise has a detrimental effect on error rate performance
by increasing eye closure at the transmitter output and reducing
the jitter tolerance/sensitivity of the receiver.

Time Jitter

Phase noise is a frequency domain phenomenon. In the time
domain, the same effect is exhibited as time jitter. When observing
a sine wave, the time of successive zero crossings is seen to vary.
In a square wave, the time jitter is seen as a displacement of the
edges from their ideal (regular) times of occurrence. In both
cases, the variations in timing from the ideal are the time jitter.
Because these variations are random in nature, the time jitter is
specified in units of seconds root mean square (rms) or 1 sigma
of the gaussian distribution.

Additive Phase Noise

Additive phase noise is the amount of phase noise that is
attributable to the device or subsystem being measured. The
phase noise of any external oscillators or clock sources has been
subtracted. This makes it possible to predict the degree to which
the device impacts the total system phase noise when used in
conjunction with the various oscillators and clock sources, each
of which contributes its own phase noise to the total. In many
cases, the phase noise of one element dominates the system
phase noise.

Additive Time Jitter

Additive time jitter is the amount of time jitter that is
attributable to the device or subsystem being measured. The
time jitter of any external oscillators or clock sources has been
subtracted. This makes it possible to predict the degree to which
the device impacts the total system time jitter when used in
conjunction with the various oscillators and clock sources, each
of which contributes its own time jitter to the total. In many
cases, the time jitter of the external oscillators and clock sources
dominates the system time jitter.

Rev. 0 | Page 8 of 12

AD9573

V

V

THEORY OF OPERATION

DD,

GND,

VDD33

DIVIDE

BY 3

GND33

CMOS

33.33MHz

LVDS

100MHz

33M

OE

100M

100M

07500-011

VDDA GNDA VDDA GNDA

XTAL

OSC

AD9573

PHASE

FREQUENCY

DETECTOR

CHARGE

PUMP

V

LDO

LDO

2.5GHz
VCO

Figure 8. Detailed Block Diagram

DIVIDE

BY 4

DIVIDE

BY 25

Figure 8 shows a block diagram of the AD9573. The chip
features a PLL core, which is configured to generate the specific
clock frequencies required for PCI-express, without any user
programming. This PLL is based on proven Analog Devices
synthesizer technology, noted for its exceptional phase noise
performance. The AD9573 is highly integrated and includes the
loop filter, a regulator for supply noise immunity, all the
necessary dividers, output buffers, and a crystal oscillator. A
user need only supply a 25 MHz external crystal to implement
an entire PCIe clocking solution, which does not require any
processor intervention.

OUTPUTS

Tabl e 11 provides a summary of the outputs available.

Table 11. Output Formats

Frequency Format Copies

100 MHz LVDS 1

33.33 MHz LVCMOS 1

The simplified equivalent circuit of the LVDS output is shown
in Figure 9. The 100 MHz output is described as LVDS because
it uses an LVDS driver topology. However, the levels are HCSL
compatible, and therefore do not meet the LVDS standard. The
output current has been increased to provide a larger output
swing than standard LVDS.

6.5mA

OUT

OUTB

6.5mA

Figure 9. LVDS Output Simplified Equivalent Circuit

Both outputs can be placed in a high impedance state by
connecting the

OE

pin according to . This pin has

a 50 kΩ pull-down resistor.

Tabl e 12

07500-012

Table 12. Output Enable Pin Function

State

OE

Output State

0 Enabled
1 High impedance

Phase Frequency Detector (PFD) and Charge Pump

The PFD takes inputs from the reference clock and feedback
divider to produce an output proportional to the phase and
frequency difference between them. Figure 10 shows a
simplified schematic.

3.3

CHARGE

GND

PUMP

CP

7500-013

HIGH

REFCLK

HIGH

FEEDBACK

DIVIDER

D1 Q 1

CLR1

CLR2

D2 Q 2

UP

DOWN

Figure 10. PFD Simplified Schematic and Timing (in Lock)

POWER SUPPLY

The AD9573 requires a 3.3 V ± 10% power supply for VDD.
The tables in the Specifications section give the performance
expected from the AD9573 with the power supply voltage
within this range. The absolute maximum range of (−0.3 V) −
(+3.6 V), with respect to GND, must never be exceeded on
the VDD or VDDA pins.

Good engineering practice should be followed in the layout of
power supply traces and the ground plane of the PCB. The
power supply should be bypassed on the PCB with adequate
capacitance (>10 μF). The AD9573 should be decoupled with
adequate capacitors (0.1 μF) at all power pins as close as
possible to these power pins. The layout of the AD9573

Rev. 0 | Page 9 of 12

AD9573

Ω

V

V

evaluation board shows a good example (see the Ordering
Guide for information about the evaluation board).

LVDS CLOCK DISTRIBUTION

Low voltage differential signaling (LVDS) is the differential
output for the AD9573. LVDS uses a current mode output stage
with a factory programmed current level. The normal value
(default) for this current is 6.5 mA, which yields a 650 mV
output swing across a 100 Ω resistor.

The typical termination circuit for the LVDS outputs is shown
in Figure 11.

50Ω

50Ω

50Ω

50Ω

100Ω

200Ω200Ω

7500-014

7500-015

LVDS LVDS

Figure 11. LVDS Output Termination

An alternative method of terminating the output to preserve output
swing but also minimize reflections is shown in Figure 12.

LVDS LVDS

Figure 12. Alternative LVDS Output Termination

CMOS CLOCK DISTRIBUTION

The AD9573 provides a 33.33 MHz clock output, which is a
dedicated CMOS level. Whenever single-ended CMOS clocking
is used, some of the following general guidelines should be
followed.

Point-to-point nets should be designed such that a driver has
one receiver only on the net, if possible. This allows for simple
termination schemes and minimizes ringing due to possible
mismatched impedances on the net. Series termination at the
source is generally required to provide transmission line
matching and/or to reduce current transients at the driver. The
value of the resistor is dependent on the board design and
timing requirements (typically 10 Ω to 100 Ω is used). CMOS

outputs are limited in terms of the capacitive load or trace
length that they can drive. Typically, trace lengths less than
6 inches are recommended to preserve signal rise/fall times
and preserve signal integrity.

60.4

1.0 INCH

CMOS

Figure 13. Series Termination of CMOS Output

10Ω

MICROSTRIP

5pF

GND

7500-016

Termination at the far end of the PCB trace is a second option.
The CMOS output of the AD9573 does not supply enough
current to provide a full voltage swing with a low impedance
resistive, far end termination, as shown in Figure 14. The far
end termination network should match the PCB trace
impedance and provide the desired switching point.

The reduced signal swing may still meet receiver input require­ments in some applications. This can be useful when driving
long trace lengths on less critical nets.

= 3.3

PULLUP

10Ω

CMOS

Figure 14. CMOS Output with Far-End Termination

50Ω

100Ω

100Ω

3pF

7500-017

POWER AND GROUNDING CONSIDERATIONS AND POWER SUPPLY REJECTION

Many applications seek high speed and performance under
less than ideal operating conditions. In these application
circuits, the implementation and construction of the PCB is as
important as the circuit design. Proper RF techniques must be
used for device selection, placement, and routing, as well as for
power supply decoupling and grounding to ensure optimum
performance.

Rev. 0 | Page 10 of 12

AD9573

OUTLINE DIMENSIONS

5.10

5.00

4.90

0.15

0.05

4.50

4.40

4.30

PIN 1

16

0.65
BSC

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153-AB

0.10

0.30

0.19

9

81

1.20
MAX

SEATING
PLANE

6.40
BSC

0.20

0.09
8°

0°

0.75

0.60

0.45

Figure 15. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9573ARUZ
AD9573-EVALZ

1

Z = RoHS Compliant Part.

1

−40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16

1

Evaluation Board

Rev. 0 | Page 11 of 12

AD9573

NOTES

©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07500-0-7/09(0)

Rev. 0 | Page 12 of 12