ANALOG DEVICES AD9558 Service Manual

Quad Input Multiservice Line Card Adaptive

Data Sheet

FEATURES

Supports GR-1244 Stratum 3 stability in holdover mode Supports smooth reference switchover with virtually

no disturbance on output phase

Supports Telcordia GR-253 jitter generation, transfer, and

tolerance for SONET/SDH up to OC-192 systems Supports ITU-T G.8262 synchronous Ethernet slave clocks Supports ITU-T G.823, G.824, G.825, and G.8261 Auto/manual holdover and reference switchover 4 reference inputs (single-ended or differential) Input reference frequencies: 2 kHz to 1250 MHz Reference validation and frequency monitoring (1 ppm) Programmable input reference switchover priority 20-bit programmable input reference divider 6 pairs of clock output pins with each pair configurable as

a single differential LVDS/HSTL output or as 2 single-ended

CMOS outputs Output frequencies: 352 Hz to 1250 MHz Programmable 17-bit integer and 24-bit fractional

feedback divider in digital PLL Programmable digital loop filter covering loop bandwidths

from 0.1 Hz to 5 kHz (2 kHz maximum for <0.1 dB of

peaking) Low noise system clock multiplier Frame sync support Adaptive clocking Optional crystal resonator for system clock input On-chip EEPROM to store multiple power-up profiles

Clock Translator with Frame Sync

AD9558

Pin program function for easy frequency translation

configuration Software controlled power-down 64-lead, 9 mm × 9 mm, LFCSP package

APPLICATIONS

Network synchronization, including synchronous Ethernet

and SDH to OTN mapping/demapping Cleanup of reference clock jitter SONET/SDH clocks up to OC-192, including FEC Stratum 3 holdover, jitter cleanup, and phase transient

control Wireless base station controllers Cable infrastructure Data communications

GENERAL DESCRIPTION

The AD9558 is a low loop bandwidth clock multiplier that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). The

AD9558 generates an output clock synchronized to up to four

external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9558 continuously generates a low jitter output clock even when all reference inputs have failed.

The AD9558 operates over an industrial temperature range of

−40°C to +85°C. If a smaller package is required, refer to the

AD9557 for the two-input/two-output version of the same part.

STABLE

FUNCTIONAL BLOCK DIAGRAM

SOURCE

CLOCK

MULTIPLIER

DIGITAL

REFERENCE INPUT

AND

MONITOR MUX

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

PLL

SERIAL I NTERFACE

AD9558

ANALOG

PLL

FRAME SYNC

(SPI OR I

Figure 1.

CHANNEL 0

DIVIDER

CHANNEL 1

÷3 TO ÷11

HF DIVIDER 0

÷3 TO ÷11

HF DIVIDER 1

2

C)

EEPROM

DIVIDER

CHANNEL 2

DIVIDER

CHANNEL 3

DIVIDER

STATUS AND

CONTROL P INS

09758-001

AD9558 Data Sheet

REVISION HISTORY

4/12—Rev 0 to Rev. A

Changed 3 Hz to 352 kHz in Output Frequencies List Item,

Features Section................................................................................. 1

Change to Output Frequency Range Parameter, Min; and System Clock Input Doubler Duty Cycle Parameter Description, Table 6... 6

Changes to Test Conditions/Comments Column, Table 9 .......... 8

Changes to Output Frequency Parameters, Min, Table 10.......... 9

Changes to Pin 4 and Pin 42, Table 20 .........................................17

Changes to Device Register Programming When Using a Register Setup File and Register Programming Overview

Sections............................................................................................. 26

Changed APLL VCO Lower Frequency and OUT5 Frequency Range, Figure 35; Changed 225 MHz to 200 MHz and 3.45 GHz

to 3.35 GHz in Overview Section...................................................29

Changes to Reference Profiles Section .........................................30

Changes to Programmable Digital Loop Filter Section ............. 32

Changes to System Clock Inputs Section..................................... 35

Changes to Output PLL (APLL) Section; Changes to Figure 39.... 37

Changes to Figure 40; Changed 1024 to 1023 in Clock Dividers Section; Changes to Clock Distribution Synchronization

Section ..............................................................................................38

Changes to Multifunction Pins (M7 to M0) and IRQ Pin

Sections............................................................................................. 42

Changes to Figure 44 ......................................................................43

Changes to EEPROM Conditional Processing Section and

Figure 45............................................................................................ 46

Added Programming the EEPROM to Configure an M Pin

to Control Synchronization of Clock Distribution Section ......... 48

Changes to the Power Supply Partitions Section ........................58

Changed 89.5° to 88.5° in DPLL Phase Margin Section ............59

Changes to Address 0x0006, Address 0x0007, and

Address 0x000A, Table 35 ..............................................................62

Changes to Address 0x0304, Table 35 ..........................................63

Changes to Address 0x0405, Table 35 ..........................................64

Rev. A | Page 3 of 104



Frame Synchronization (Register 0x0640 to

Register 0x0641)..........................................................................86

DPLL Profile Registers (Register 0x0700 to

Register 0x07E6) .........................................................................87

Operational Controls (Register 0x0A00 to

Register 0x0A10).........................................................................89

Quick In/Out Frequency Soft Pin Configuration

(Register 0x0C00 to Register 0x0C08) .....................................92

Status ReadBack (Register 0x0D00 to Register 0x0D14).......93

EEPROM Control (Register 0x0E00 to Register 0x0E03).....97

EEPROM Storage Sequences (Register 0x0E10 to

Register 0x0E3C).........................................................................98

Outline Dimensions......................................................................104

Ordering Guide.........................................................................104

Changes to Address 0x071A and Address 0x071D, Table 35 ....65

Changes to Address 0x0780, Address 0x0785 to Address 0x078A, Address 0x079A, Address 0x079D, Table 35 ...67 Changes to Address 0x07C0, Address 0x07DA, and

Address 0x07DD, Table 35 ............................................................. 68

Change to Address 0x0A01, Bit 7, Table 35................................. 69

Added Address 0x0E3D to Address 0x0E45, Table 35............... 71

Change to Table 38; Added Table 40, Renumbered Sequentially;

Changes to Table 41 ........................................................................72

Change to Bit 0, Address 0x0101, Table 43 .................................. 73

Changes to Address 0x0304, Table 55 .......................................... 76

Deleted Address 0x0305, Table 55 ................................................76

Changes to Table Title, Table 63; Changes to Address 0x0400

and Address 0x0403, Table 64........................................................ 79

Changes to Address 0x0405, Table 64 .......................................... 80

Changes to Descriptions, Address 0x0500, Table 67 ..................81

Changes to Bit 0, Address 0x0501, Table 68 ................................ 82

Changes to Bits[6:4], Address 0x0505 and Changes to

Address 0x0506, Table 70............................................................... 83

Changes to Bits[6:4] and Bit 0, Address 0x050F, Table 73......... 84

Change to Address 0x0704, Table 78; Changes to Bits[3:0] in Address 0x0707 and Address 070A, Table 79; and Changes to

Address 0x070E, Table 82................................................................87

Changes to Address 0x0710, Table 83; and Changes to Bits[3:0],

Address 0x0714, Table 84................................................................. 88

Changes to Bits[1:0], Address 0x0A01, Table 90...........................89

Changes to Descriptions, Address 0x0A0B, Table 99................. 91

Changes to Bit 4, Address 0x0C06, Table 100 ............................. 93

Changes to Bit 6 and Bit 1, Address 0x0D01, Table 102 ............94

Changes to Table Summary, Table 114......................................... 98

Added Table 128............................................................................ 101

Changes to Table 129 ....................................................................102

Changes to Table 130 ....................................................................103

10/11—Revision 0: Initial Version



AD9558 Data Sheet

SPECIFICATIONS

Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ) values apply for AVDD3 = DVDD_I/O = 3.3 V; AVDD = DVDD

SUPPLY VOLTAGE

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

SUPPLY VOLTAGE

DVDD3 3.135 3.30 3.465 V DVDD 1.71 1.80 1.89 V AVDD3 3.135 3.30 3.465 V AVDD 1.71 1.80 1.89 V

SUPPLY CURRENT

The test conditions for the maximum (max) supply current are the same as the test conditions for the All Blocks Running parameter of Tabl e 3. The test conditions for the typical (typ) supply current are the same as the test conditions for the Typical Configuration parameter of Tabl e 3 .

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

SUPPLY CURRENT FOR TYPICAL

CONFIGURATION I

12 19 26 mA Pin 45, Pin 46, Pin 51, Pin 52, Pin 64

DVDD3

I

12 20 28 mA Pin 6, Pin 55, Pin 56

DVDD

I

50 70 92 mA Pin 25, Pin 26, Pin 31

AVDD3

I

152 230 305 mA

AVDD

SUPPLY CURRENT FOR THE ALL BLOCKS

RUNNING CONFIGURATION I

23 34 46 mA Pin 45, Pin 46, Pin 51, Pin 52, Pin 64

DVDD3

I

11 22 32 mA Pin 6, Pin 55, Pin 56

DVDD

I

73 108 143 mA Pin 25, Pin 26, Pin 31

AVDD3

I

168 250 331 mA

AVDD

= 1.8 V; TA= 25°C, unless otherwise noted.

Typical numbers are for the typical configuration listed in Table 3

Pin 7, Pin 10, Pin 12, Pin 17, Pin 22, Pin 29, Pin 30, Pin 35, Pin 37, Pin 38

Maximum numbers are for all blocks running configuration in Table 3

Pin 7, Pin 10, Pin 12, Pin 17, Pin 22, Pin 29, Pin 30, Pin 35, Pin 37, Pin 38

Rev. A | Page 4 of 104

Data Sheet AD9558

POWER DISSIPATION

Table 3.

Parameter Min Typ Max Unit Test Conditions/Comments

POWER DISSIPATION

Typical Configuration 0.47 0.74 1.02 W

All Blocks Running 0.6 1.0 1.32 W

Full Power-Down 44 125 mW

Incremental Power Dissipation

Input Reference On/Off

Differential Without Divide-by-2 20 25 32 mW Additional current draw is in the DVDD3 domain only Differential With Divide-by-2 26 32 40 mW Additional current draw is in the DVDD3 domain only Single-Ended (Without Divide-by-2) 5 7 9 mW Additional current draw is in the DVDD3 domain only

Output Distribution Driver On/Off

LVDS (at 750 MHz) 12 17 22 mW Additional current draw is in the AVDD domain only HSTL (at 750 MHz) 14 21 28 mW Additional current draw is in the AVDD domain only

1.8 V CMOS (at 250 MHz) 14 21 28 mW A single 1.8 V CMOS output with an 80 pF load

3.3 V CMOS (at 250 MHz) 18 27 36 mW A single 3.3 V CMOS output with an 80 pF load

Other Blocks On/Off

Second RF Divider 36 51 64 mW Additional current draw is in the AVDD domain only

Channel Divider Bypassed 10 17 23 mW Additional current draw is in the AVDD domain only

System clock: 49.152 MHz crystal; DPLL active; both 19.44 MHz input references in differential mode; one HSTL driver at 644.53125 MHz; one 3.3 V CMOS driver at 161.1328125 MHz and 80 pF capacitive load on CMOS output

System clock: 49.152 MHz crystal; DPLL active; both input references in differential mode; four HSTL drivers at 750 MHz; four 3.3 V CMOS drivers at 250 MHz and 80 pF capacitive load on CMOS outputs

Typical configuration with no external pull-up or pulldown resistors; about 2/3 of this power is on AVDD3

Conditions = typical configuration; table values show the change in power due to the indicated operation

LOGIC INPUTS (SYNC, RESET, PINCONTROL, M7 TO M0)

Table 4.

Parameter Min Typ Max Unit Test Conditions/Comments

LOGIC INPUTS (SYNC, RESET, PINCONTROL)

Input High Voltage (VIH) 2.1 V Input Low Voltage (VIL) 0.8 V Input Current (I

, I

) ±50 ±100 µA

INH

INL

Input Capacitance (CIN) 3 pF

LOGIC INPUTS (M7 to M0)

Input High Voltage (VIH) 2.5 V Input ½ Level Voltage (VIM) 1.0 2.2 V Input Low Voltage (VIL) 0.6 V Input Current (I

, I

) ±60 ±100 µA

INH

INL

Input Capacitance (CIN) 3 pF

Rev. A | Page 5 of 104

AD9558 Data Sheet

LOGIC OUTPUTS (M7 TO M0, IRQ)

Table 5.

Parameter Min Typ Max Unit Test Conditions/Comments

LOGIC OUTPUTS (M7 to M0, IRQ)

Output High Voltage (VOH) DVDD3 − 0.4 V IOH = 1 mA Output Low Voltage (VOL) 0.4 V IOL = 1 mA IRQ Leakage Current Open-drain mode

Active Low Output Mode −200 A VOH = 3.3 V Active High Output Mode 100 A VOL = 0 V

SYSTEM CLOCK INPUTS (XOA, XOB)

Table 6.

Parameter Min Typ Max Unit Test Conditions/Comments

SYSTEM CLOCK MULTIPLIER

Output Frequency Range 750 805 MHz

Phase Frequency Detector (PFD) Rate 150 MHz Frequency Multiplication Range 2 255

SYSTEM CLOCK REFERENCE INPUT PATH

Input Frequency Range 10 600 MHz Minimum Input Slew Rate 20 V/s

Common-Mode Voltage 1.05 1.16 1.25 V Internally generated Differential Input Voltage Sensitivity 250 mV p-p

System Clock Input Doubler Duty Cycle

System Clock Input = 50 MHz 45 50 55 % System Clock Input = 20 MHz 46 50 54 %

System Clock Input = 16 MHz to 20 MHz 47 50 53 % Input Capacitance 3 pF Single-ended, each pin Input Resistance 4.2 kΩ

CRYSTAL RESONATOR PATH

Crystal Resonator Frequency Range 10 50 MHz Fundamental mode, AT cut crystal Maximum Crystal Motional Resistance 100 Ω

The VCO range may place limitations on nonstandard system clock input frequencies

Assumes valid system clock and PFD rates

Minimum limit imposed for jitter performance

Minimum voltage across pins required to ensure switching between logic states; the instantaneous voltage on either pin must not exceed the supply rails; can accommodate single-ended input by ac grounding of complementary input; 1 V p-p recommended for optimal jitter performance

This is the amount of duty cycle variation that can be tolerated on the system clock input to use the doubler

Rev. A | Page 6 of 104

Data Sheet AD9558

REFERENCE INPUTS

Table 7.

Parameter Min Typ Max Unit Test Conditions/Comments

DIFFERENTIAL OPERATION

Frequency Range

Sinusoidal Input 10 750 MHz LVPECL Input 0.002 1250 MHz

LVDS Input 0.002 750 MHz

Minimum Input Slew Rate 40 V/s Minimum limit imposed for jitter performance Common-Mode Input Voltage

AC-Coupled 1.9 2 2.2 V Internally generated DC-Coupled 1.0 2.4 V

Differential Input Voltage Sensitivity mV

fIN < 800 MHz 240 mV fIN = 800 to 1050 MHz 320 mV

fIN = 1050 to 1250 MHz 400 mV Differential Input Voltage Hysteresis 58 100 mV Input Resistance 21 kΩ Input Capacitance 3 pF

Minimum Pulse Width High

LVPECL 390 ps

LVDS 640 ps Minimum Pulse Width Low

LVPECL 390 ps

LVDS 640 ps

SINGLE-ENDED OPERATION

Frequency Range (CMOS) 0.002 300 MHz Minimum Input Slew Rate 40 V/s Minimum limit imposed for jitter performance Input Voltage High (VIH)

1.2 V to 1.5 V Threshold Setting 1.0 V

1.8 V to 2.5 V Threshold Setting 1.4 V

3.0 V to 3.3 V Threshold Setting 2.0 V

Input Voltage Low (VIL)

1.2 V to 1.5 V Threshold Setting 0.35 V

1.8 V to 2.5 V Threshold Setting 0.5 V

3.0 V to 3.3 V Threshold Setting 1.0 V Input Resistance 47 kΩ Input Capacitance 3 pF Minimum Pulse Width High 1.5 ns Minimum Pulse Width Low 1.5 ns

The reference input divide-by-2 block must be engaged for fIN > 705 MHz

The reference input divide-by-2 block must be engaged for f

Minimum differential voltage across pins is required to ensure switching between logic levels; instantaneous voltage on either pin must not exceed the supply rails

> 705 MHz

IN

Rev. A | Page 7 of 104

AD9558 Data Sheet

REFERENCE MONITORS

Table 8.

Parameter Min Typ Max Unit Test Conditions/Comments

REFERENCE MONITORS

Reference Monitor

Loss of Reference Detection Time 1.1

DPLL PFD

Nominal phase detector period = R/f

period

Frequency Out-of-Range Limits <2 105

∆f/f

REF

(ppm)

Programmable (lower bound is subject to quality of the system clock (SYSCLK)); SYSCLK accuracy must be better than the lower bound

Validation Timer 0.001 65.535 sec Programmable in 1 ms increments

1

f

is the frequency of the active reference; R is the frequency division factor determined by the R-divider.

REF

REFERENCE SWITCHOVER SPECIFICATIONS

Table 9.

Parameter Min Typ Max Unit Test Conditions/Comments

REFERENCE SWITCHOVER SPECIFICATIONS

Maximum Output Phase Perturbation

(Phase Build-Out Switchover)

50 Hz DPLL Loop Bandwidth Valid for automatic and manual reference switching

Peak 0 ±100 ps Steady State 0 ±100 ps

2 kHz DPLL Loop Bandwidth Valid for automatic and manual reference switching

Peak 0 ±250 ps Steady State 0 ±100 ps

Time Required to Switch to

a New Reference Phase Build-Out Switchover 1.1

Assumes a jitter-free reference; satisfies Telcordia GR-1244-CORE requirements; select high PM base loop filter bit (Register 0x070E, Bit 0) is set to 1 for all active references

DPLL PFD period

Calculated using the nominal phase detector period (NPDP = R/f equal to the time plus the reference validation time and the time required to lock to the new reference

); the total time required is

REF

1

Rev. A | Page 8 of 104

Data Sheet AD9558

DISTRIBUTION CLOCK OUTPUTS

Table 10.

Parameter Min Typ Max Unit Test Conditions/Comments

HSTL MODE

Output Frequency 0.000352 1250 MHz

Rise/Fall Time (20% to 80%)1 140 250 ps 100 Ω termination across output pins Duty Cycle

Up to f Up to f Up to f

= 700 MHz 45 48 52 %

OUT

= 750 MHz 42 48 53 %

OUT

= 1250 MHz 43 %

OUT

Differential Output Voltage Swing 700 950 1200 mV Magnitude of voltage across pins; output driver static Common-Mode Output Voltage 700 870 960 mV Output driver static

LVDS MODE

Output Frequency 0.000352 1250 MHz

Rise/Fall Time (20% to 80%)1 185 280 ps 100 Ω termination across the output pair Duty Cycle

Up to f Up to f Up to f

= 750 MHz 44 48 53 %

OUT

= 800 MHz 43 47 53 %

OUT

= 1250 MHz 43 %

OUT

Differential Output Voltage Swing

Balanced, VOD 247 454 mV

Unbalanced, ∆VOD 50 mV

Offset Voltage

Common-Mode, VOS 1.125 1.26 1.375 V Output driver static Common-Mode Difference, ∆VOS 50 mV Voltage difference between pins; output driver static

Short-Circuit Output Current 13 24 mA Output driver static

CMOS MODE

Output Frequency

1.8 V Supply 0.000352 150 MHz 10 pF load

3.3 V Supply (OUT0 and OUT5)

Strong Drive Strength Setting 0.000352 250 MHz 10 pF load Weak Drive Strength Setting 0.000352 25 MHz 10 pF load

Rise/Fall Time (20% to 80%)1

1.8 V Supply 1.5 3 ns 10 pF load

3.3 V Supply

Strong Drive Strength Setting 0.4 0.6 ns 10 pF load Weak Drive Strength Setting 8 ns 10 pF load

Duty Cycle

1.8 V Mode 50 % 10 pF load

3.3 V Strong Mode 47 % 10 pF load

3.3 V Weak Mode 51 % 10 pF load Output Voltage High (VOH) Output driver static; strong drive strength

AVDD3 = 3.3 V, IOH = 10 mA AVDD3 − 0.3 V AVDD3 = 3.3 V, IOH = 1 mA AVDD3 − 0.1 V AVDD3 = 1.8 V, IOH = 1 mA AVDD − 0.2 V

Output Voltage Low (VOL) Output driver static; strong drive strength

AVDD3 = 3.3 V, IOL = 10 mA 0.3 V AVDD3 = 3.3 V, IOL = 1 mA 0.1 V AVDD3 = 1.8 V, IOL = 1 mA 0.1 V

OUT5 only; OUT0 to OUT4 minimum output frequency is 360 kHz

Voltage swing between output pins; output driver static

Absolute difference between voltage swing of normal pin and inverted pin; output driver static

OUT5 only; OUT0 to OUT4 minimum output frequency is 360 kHz

Rev. A | Page 9 of 104

AD9558 Data Sheet

Parameter Min Typ Max Unit Test Conditions/Comments

OUTPUT TIMING SKEW 10 pF load

Between OUT0 and OUT1 10 70 ps

Between OUT0 and OUT3 105 222 ps

Between OUT0 and OUT5 1.39 1.76 ns

Between OUT1 and OUT2

1 12 ps (OUT1 and OUT2 Share the Same Divider)

Between OUT3 and OUT4

1 24 ps (OUT3 and OUT4 Share the Same Divider)

Across All OUT0 to OUT4 HSTL 105 235 ps

Across All OUT0 to OUT4 LVDS 100 235 ps

Additional Delay on One Driver by

Changing Its Logic Type HSTL to LVDS −5 +1 +5 ps

HSTL to 1.8 V CMOS −5 0 +5 ps

HSTL to 3.3 V CMOS, Strong Mode The CMOS edge is delayed relative to HSTL

OUT0 CMOS to OUT1 HSTL 3.53 3.59 ns OUT0 CMOS to OUT3 HSTL 3.55 3.65 ns OUT0 CMOS to OUT4 HSTL 3.56 3.68 ns OUT0 CMOS to OUT5 HSTL 4.84 5.1 ns

1

The listed values are for the slower edge (rise or fall).

HSTL mode on both drivers; rising edge only; any divide value

HSTL mode on all drivers; rising edge only; any divide value

LVDS mode on all drivers; rising edge only; any divide value

Positive value indicates that the LVDS edge is delayed relative to HSTL

Positive value indicates that the CMOS edge is delayed relative to HSTL

TIME DURATION OF DIGITAL FUNCTIONS

Table 11.

Parameter Min Typ Max Unit Test Conditions/Comments

TIME DURATION OF DIGITAL

FUNCTIONS EEPROM-to-Register Download

Time

Register-to-EEPROM Upload Time 138 145 ms

Minimum Power-Down Exit Time 1 ms

13 20 ms

Using default EEPROM storage sequence (see Register 0x0E10 to Register 0x0E3F)

Time from power-down exit to system clock lock detect

Rev. A | Page 10 of 104

Data Sheet AD9558

DIGITAL PLL

Table 12.

Parameter Min Typ Max Unit Test Conditions/Comments

DIGITAL PLL

Phase-Frequency Detector (PFD)

Input Frequency Range Loop Bandwidth 0.1 2000 Hz Programmable design parameter Phase Margin 30 89 Degrees Programmable design parameter Closed-Loop Peaking <0.1 dB

Reference Input (R) Division Factor 1 220 1, 2, …, 1,048,576 Integer Feedback (N1) Division Factor 180 217 180, 181, …, 131,072 Fractional Feedback Divide Ratio 0 0.999 Maximum value: 16,777,215/16,777,216

DIGITAL PLL LOCK DETECTION

Table 13.

Parameter Min Typ Max Unit Test Conditions/Comments

PHASE LOCK DETECTOR

Threshold Programming Range 0.001 65.5 ns Threshold Resolution 1 ps

FREQUENCY LOCK DETECTOR

Threshold Programming Range 0.001 16,700 ns Reference-to-feedback period difference Threshold Resolution 1 ps

2 100 kHz

Programmable design parameter ; part can be programmed for <0.1 dB peaking in accordance with Telcordia GR-253 jitter transfer

HOLDOVER SPECIFICATIONS

Table 14.

Parameter Min Typ Max Unit Test Conditions/Comments

HOLDOVER SPECIFICATIONS

Initial Frequency Accuracy <0.01 ppm

Excludes frequency drift of SYSCLK source; excludes frequency drift of input reference prior to entering holdover; compliant with GR-1244 Stratum 3

Rev. A | Page 11 of 104

AD9558 Data Sheet

SERIAL PORT SPECIFICATIONS—SPI MODE

Table 15.

Parameter Min Typ Max Unit Test Conditions/Comments

CS

Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 60 µA Input Logic 0 Current 100 µA Input Capacitance 2 pF

SCLK Internal 30 kΩ pull-down resistor

Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 200 µA Input Logic 0 Current 1 µA Input Capacitance 2 pF

SDIO

As an Input

Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 1 µA Input Logic 0 Current 1 µA

Input Capacitance 2 pF As an Output Output Logic 1 Voltage DVDD3 − 0.6 V 1 mA load current Output Logic 0 Voltage 0.4 V 1 mA load current

SDO

Output Logic 1 Voltage DVDD3 − 0.6 V 1 mA load current Output Logic 0 Voltage 0.4 V 1 mA load current

TIMING

SCLK

Clock Rate, 1/t

Pulse Width High, t

Pulse Width Low, t

40 MHz

CLK

10 ns

HIGH

13 ns

LOW

SDIO to SCLK Setup, tDS 3 ns SCLK to SDIO Hold, tDH 6 ns SCLK to Valid SDIO and SDO, tDV 10 ns CS to SCLK Setup (tS)

CS to SCLK Hold (tC) CS Minimum Pulse Width High

10 ns 0 ns 6 ns

Rev. A | Page 12 of 104

Data Sheet AD9558

SERIAL PORT SPECIFICATIONS—I2C MODE

Table 16.

Parameter Min Typ Max Unit Test Conditions/Comments

SDA, SCL (AS INPUT)

Input Logic 1 Voltage

0.7 × DVDD3

Input Logic 0 Voltage

Input Current −10 +10 µA For VIN = 10% to 90% DVDD3 Hysteresis of Schmitt Trigger Inputs

0.015 × DVDD3

Pulse Width of Spikes That Must Be Suppressed by

the Input Filter, t

SP

50 ns

SDA (AS OUTPUT)

Output Logic 0 Voltage 0.4 V IO = 3 mA Output Fall Time from V

IHmin

to V

ILmax

20 + 0.1

1

C

b

TIMING

SCL Clock Rate 400 kHz Bus-Free Time Between a Stop and Start

Condition, t

BUF

Repeated Start Condition Setup Time, t Repeated Hold Time Start Condition, t

Stop Condition Setup Time, t Low Period of the SCL Clock, t

SU; STO

LOW

High Period of the SCL Clock, t SCL/SDA Rise Time, t

R

HD; STA

0.6 µs

1.3 µs

0.6 µs

HIGH

SU; STA

0.6 µs

1.3 µs

0.6 µs

20 + 0.1 C SCL/SDA Fall Time, tF 20 + 0.1 C Data Setup Time, t Data Hold Time, t Capacitive Load for Each Bus Line, C

1

Cb is the capacitance (pF) of a single bus line.

100 ns

SU; DAT

100 ns

HD; DAT

1

400 pF

b

V

0.3 ×

V

DVDD3

250 ns 10 pF ≤ Cb ≤ 400 pF

After this period, the first clock pulse is generated

1

300 ns

b

1

300 ns

b

JITTER GENERATION

Jitter generation (random jitter) uses 49.152 MHz crystal for system clock input.

Table 17.

Parameter Min Typ Max Unit Test Conditions/Comments

JITTER GENERATION

f

= 19.44 MHz; f

REF

= 622.08 MHz; f

OUT

LOOP

= 50 Hz

HSTL Driver

Bandwidth: 5 kHz to 20 MHz 304 fs rms Bandwidth: 12 kHz to 20 MHz 296 fs rms Bandwidth: 20 kHz to 80 MHz 300 fs rms Bandwidth: 50 kHz to 80 MHz 266 fs rms Bandwidth: 16 MHz to 320 MHz 185 fs rms

Rev. A | Page 13 of 104

System clock doubler enabled; high phase margin mode enabled; Register 0x0405 = 0x20; Register 0x0403 = 0x07; Register 0x0400 = 0x81; in cases where multiple driver types are listed, both driver types were tested at those conditions, and the one with higher jitter is quoted, although there is usually not a significant jitter difference between the driver types

AD9558 Data Sheet

Parameter Min Typ Max Unit Test Conditions/Comments

f

= 19.44 MHz; f

REF

= 644.53 MHz; f

OUT

LOOP

= 50 Hz

HSTL and/or LVDS Driver

Bandwidth: 5 kHz to 20 MHz 334 fs rms Bandwidth: 12 kHz to 20 MHz 321 fs rms Bandwidth: 20 kHz to 80 MHz 319 fs rms Bandwidth: 50 kHz to 80 MHz 277 fs rms Bandwidth: 16 MHz to 320 MHz 185 fs rms

f

= 19.44 MHz; f

REF

= 693.48 MHz; f

OUT

LOOP

= 50 Hz

HSTL Driver

Bandwidth: 5 kHz to 20 MHz 298 fs rms Bandwidth: 12 kHz to 20 MHz 285 fs rms Bandwidth: 20 kHz to 80 MHz 286 fs rms Bandwidth: 50 kHz to 80 MHz 252 fs rms Bandwidth: 16 MHz to 320 MHz 183 fs rms

f

= 19.44 MHz; f

REF

= 174.703 MHz; f

OUT

LOOP

= 1 kHz

HSTL Driver

Bandwidth: 5 kHz to 20 MHz 354 fs rms Bandwidth: 12 kHz to 20 MHz 301 fs rms Bandwidth: 20 kHz to 80 MHz 321 fs rms Bandwidth: 50 kHz to 80 MHz 290 fs rms Bandwidth: 4 MHz to 80 MHz 177 fs rms

f

= 19.44 MHz; f

REF

= 174.703 MHz; f

OUT

= 100 Hz

LOOP

LVDS and/or 3.3 V CMOS Driver

Bandwidth: 5 kHz to 20 MHz 306 fs rms Bandwidth: 12 kHz to 20 MHz 293 fs rms Bandwidth: 20 kHz to 80 MHz 313 fs rms Bandwidth: 50 kHz to 80 MHz 283 fs rms Bandwidth: 4 MHz to 80 MHz 166 fs rms

f

= 25 MHz; f

REF

= 161.1328 MHz; f

OUT

= 100 Hz

LOOP

HSTL Driver

Bandwidth: 5 kHz to 20 MHz 316 fs rms Bandwidth: 12 kHz to 20 MHz 302 fs rms Bandwidth: 20 kHz to 80 MHz 324 fs rms Bandwidth: 50 kHz to 80 MHz 292 fs rms Bandwidth: 4 MHz to 80 MHz 171 fs rms

f

= 2 kHz; f

REF

= 70.656 MHz; f

OUT

= 100 Hz;

LOOP

HSTL and/or 3.3 V CMOS Driver

Bandwidth: 10 Hz to 30 MHz 3.22

Bandwidth: 5 kHz to 20 MHz 338 fs rms Bandwidth: 12 kHz to 20 MHz 324 fs rms Bandwidth: 10 kHz to 400 kHz 278 fs rms Bandwidth: 100 kHz to 10 MHz 210 fs rms

f

= 25 MHz; f

REF

= 1 GHz; f

OUT

= 500 Hz

LOOP

HSTL Driver

Bandwidth: 100 Hz to 500 MHz (Broadband) 1.71

Bandwidth: 12 kHz to 20 MHz 343 fs rms Bandwidth: 20 kHz to 80 MHz 338 fs rms

ps rms

Rev. A | Page 14 of 104

Data Sheet AD9558

Jitter generation (random jitter) uses 19.2 MHz TCXO for system clock input.

Table 18.

Parameter Min Typ Max Unit Test Conditions/Comments

JITTER GENERATION

f

= 19.44 MHz; f

REF

= 644.53 MHz; f

OUT

= 0.1 Hz

LOOP

HSTL Driver

Bandwidth: 5 kHz to 20 MHz 402 fs rms Bandwidth: 12 kHz to 20 MHz 393 fs rms Bandwidth: 20 kHz to 80 MHz 391 fs rms Bandwidth: 50 kHz to 80 MHz 347 fs rms Bandwidth: 16 MHz to 320 MHz 179 fs rms

f

= 19.44 MHz; f

REF

= 693.48 MHz; f

OUT

= 0.1 Hz

LOOP

HSTL Driver

Bandwidth: 5 kHz to 20 MHz 379 fs rms Bandwidth: 12 kHz to 20 MHz 371 fs rms Bandwidth: 20 kHz to 80 MHz 371 fs rms Bandwidth: 50 kHz to 80 MHz 335 fs rms Bandwidth: 16 MHz to 320 MHz 175 fs rms

f

= 19.44 MHz; f

REF

= 312.5 MHz; f

OUT

= 0.1 Hz

LOOP

HSTL Driver

Bandwidth: 5 kHz to 20 MHz 413 fs rms Bandwidth: 12 kHz to 20 MHz 404 fs rms Bandwidth: 20 kHz to 80 MHz 407 fs rms Bandwidth: 50 kHz to 80 MHz 358 fs rms Bandwidth: 4 MHz to 80 MHz 142 fs rms

f

= 25 MHz; f

REF

= 161.1328 MHz; f

OUT

LOOP

= 0.1 Hz

HSTL Driver

Bandwidth: 5 kHz to 20 MHz 399 fs rms Bandwidth: 12 kHz to 20 MHz 391 fs rms Bandwidth: 20 kHz to 80 MHz 414 fs rms Bandwidth: 50 kHz to 80 MHz 376 fs rms Bandwidth: 4 MHz to 80 MHz 190 fs rms

f

= 2 kHz; f

REF

= 70.656 MHz; f

OUT

= 0.1 Hz

LOOP

HSTL and/or 3.3 V CMOS Driver

Bandwidth: 10 Hz to 30 MHz 970 fs rms Bandwidth: 12 kHz to 20 MHz 404 fs rms Bandwidth: 10 kHz to 400 kHz 374 fs rms Bandwidth: 100 kHz to 10 MHz 281 fs rms

System clock doubler enabled; high phase margin mode enabled; Register 0x0405 = 0x20; Register 0x0403 = 0x07; Register 0x0400 = 0x81; in cases where multiple driver types are listed, both driver types were tested at those conditions, and the one with higher jitter is quoted, although there is usually not a significant jitter difference between the driver types

Rev. A | Page 15 of 104

AD9558 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 19.

Parameter Rating

Analog Supply Voltage (AVDD) 2 V Digital Supply Voltage (DVDD) 2 V Digital I/O Supply Voltage (DVDD3) 3.6 V Analog Supply Voltage (AVDD3) 3.6 V Maximum Digital Input Voltage −0.5 V to DVDD3 + 0.5 V Storage Temperature Range −65°C to +150°C Operating Temperature Range −40°C to +85°C Lead Temperature

(Soldering 10 sec)

Junction Temperature 150°C

300°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. A | Page 16 of 104

Data Sheet AD9558

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DVDD3M6M5M4M3M2M1M0DVDD

PIN 1

INDICATOR

IRQ

SDO

CS DVDD AVD D

XOA XOB

AVD D

NC AVD D OUT4 OUT4 OUT3 OUT3

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

SCLK/SCL SDIO/SDA

NOTES

1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND (VSS).

646362616059585756555453525150

(Not to Scale)

171819202122232425262728293031

OUT2

OUT1

AVD D

AD9558

TOP VIEW

OUT5

AVD D

AVD D3

DVDD

REFB

DVDD3

REFD

49

48

REFC

47

REFC

46

DVDD3

45

DVDD3

44

REFA

43

REFA

42

SYNC

41

M7

40

PINCONTROL

39

RESET

38

AVD D

37

AVD D

36

NC

35

AVD D

34

NC

33

LF_VCO2

32

OUT0

AVD D

AVD D3

LDO_VCO2

Figure 2. Pin Configuration

Table 20. Pin Function Descriptions

Input/

Pin No. Mnemonic

Output

Pin Type Description

1 IRQ O 3.3 V CMOS Interrupt Request Line. 2 SCLK/SCL I 3.3 V CMOS

Serial Programming Clock (SCLK) in SPI Mode. Data clock for serial programming. Open-Collector Serial Clock Pin (SCL) in I

2

C Mode. Requires a pull-up resistor, usually

2.2 kΩ; the resistor size depends on the number of I

3 SDIO/SDA I/O 3.3 V CMOS

Serial Data Input/Output (SDIO) in SPI Mode. When the device is in 4-wire SPI mode, data is written via this pin. In 3-wire SPI mode, both data reads and writes occur on this pin. There is no internal pull-up/pull-down resistor on this pin. Open-Collector Serial Data Pin (SDA) in I2C Mode. Requires a pull-up resistor, usually

2.2 kΩ; the resistor size depends on the number of I

4 SDO O 3.3 V CMOS

Serial Data Output. Use this pin to read data in 4-wire mode. There is no internal pull-up/ pull-down resistor on this pin. This pin is high impedance in the default 3-wire mode.

5

CS

I 3.3 V CMOS

Chip Select (SPI), Active Low. When programming a device, this pin must be held low. In systems where more than one AD9558 is present, this pin enables individual

programming of each AD9558. This pin has an internal 10 kΩ pull-up resistor. 6, 55, 56 DVDD I Power 1.8 V Digital Supply. 7 AVDD I Power 1.8 V Analog (SYSCLK) Power Supply. 8 XOA I

Differential input

System Clock Input. XOA contains internal dc biasing and should be ac-coupled with

a 0.01 F capacitor, except when using a crystal. If a crystal is used, connect the crystal

across XOA and XOB. Single-ended 1.8 V CMOS is also an option but can introduce

a spur if the duty cycle is not 50%. When using XOA as a single-ended input, connect

a 0.01 F capacitor from XOB to ground. 9 XOB I

Differential input

Complementary System Clock Input. Complementary signal to XOA. XOB contains

internal dc biasing and should be ac-coupled with a 0.01 F capacitor, except when

using a crystal. If a crystal is used, connect the crystal across XOA and XOB. 10 AVDD I Power 1.8 V Analog (VCO) Power Supply. 11 NC I No Connection. Do not connect to this pin. 12, 17,

AVDD I Power 1.8 V Analog (Output Driver) Power Supply. 22, 29, 30

09758-002

2

C devices on the bus.

2

C devices on the bus.

Rev. A | Page 17 of 104

AD9558 Data Sheet

Input/

Pin No. Mnemonic

13

14 OUT4 O

15

16 OUT3 O

18

19 OUT2 O

20

21 OUT1 O

23

24 OUT5 O

25, 26 AVDD3 I Power 3.3 V Analog (Output Driver) Power Supply. 27

28 OUT0 O

31 AVDD3 I Power 3.3V Analog (VCO 2) Power Supply. 32 LDO_VCO2 I LDO bypass

33 LF_VCO2 I/O Loop filter

34 NC No Connect. There is no internal connection for this pin. 35 AVDD I Power 1.8 V Analog (APLL) Power Supply. 36 NC No Connect. There is no internal connection for this pin. 37, 38 AVDD I Power 1.8 V Analog (DCO and TDC) Power Supplies. 39

40 PINCONTROL I 3.3 V CMOS

41 M7 I/O 3.3 V CMOS

42

OUT4

OUT3

OUT2

OUT1

OUT5

OUT0

RESET

SYNC

Output Pin Type Description

O

I 3.3 V CMOS

HSTL, LVDS, or

1.8 V CMOS HSTL, LVDS,

or 1.8 V CMOS

HSTL, LVDS, or

1.8 V CMOS HSTL, LVDS, or

1.8 V CMOS

HSTL, LVDS, or

1.8 V CMOS HSTL, LVDS, or

1.8 V CMOS

HSTL, LVDS, or

1.8 V CMOS HSTL, LVDS,

or 1.8 V CMOS

HSTL, LVDS,

1.8 V CMOS,

3.3 V CMOS HSTL, LVDS,

1.8 V CMOS,

3.3 V CMOS

HSTL, LVDS,

1.8 V CMOS,

3.3 V CMOS HSTL, LVDS,

1.8 V CMOS,

3.3 V CMOS

Complementary Output 4. This output can be configured as HSTL, LVDS, or single-ended

1.8 V CMOS. Output 4. This output can be configured as HSTL, LVDS, or single-ended 1.8 V CMOS.

LVPECL levels can be achieved by ac coupling and using the Thevenin-equivalent termination as described in the Input/Output Termination Recommendations section.

Complementary Output 3. This output can be configured as HSTL, LVDS, or single-ended 1.8 V CMOS.

Output 3. This output can be configured as HSTL, LVDS, or single-ended 1.8 V CMOS. LVPECL levels can be achieved by ac coupling and using the Thevenin-equivalent termination as described in the Input/Output Termination Recommendations section.

Complementary Output 2. This output can be configured as HSTL, LVDS, or single-ended 1.8 V CMOS.

Output 2. This output can be HSTL, LVDS, or single-ended 1.8 V CMOS. LVPECL levels can be achieved by ac coupling and using the Thevenin-equivalent termination as described in the Input/Output Termination Recommendations section.

Complementary Output 1. This output can be configured as HSTL, LVDS, or single-ended 1.8 V CMOS.

Output 1. This output can be configured as HSTL, LVDS, or single-ended 1.8 V CMOS. LVPECL levels can be achieved by ac coupling and using the Thevenin-equivalent termination as described in the Input/Output Termination Recommendations section.

Complementary Output 5. This output can be configured as HSTL, LVDS, or single-ended

1.8 V or 3.3 V CMOS.

Output 5. This output can be configured as HSTL, LVDS, or single-ended 1.8 V or 3.3 V CMOS. LVPECL levels can be achieved by ac coupling and by using the Theveninequivalent termination as described in the Input/Output Termination Recommendations section.

Complementary Output 0. This output can be configured as HSTL, LVDS, or singleended 1.8 V or 3.3 V CMOS.

Output 0. This output can be configured as HSTL, LVDS, or single-ended 1.8 V or 3.3 V CMOS. LVPECL levels can be achieved by ac coupling and by using the Theveninequivalent termination as described in the Input/Output Termination Recommendations section.

Output PLL Loop Filter Voltage Regulator. Connect a 0.47 F capacitor from this pin to ground. This pin is also the ac ground reference for the integrated output PLL external loop filter.

Loop Filter Node for the Output PLL. Connect an external 6.8 nF capacitor from this pin to Pin 32 (LDO_VCO2).

Chip Reset. When this active low pin is asserted, the chip goes into reset. This pin has an internal 50 kΩ pull-up resistor.

Pin Program Mode Enable Pin. When pulled high during startup, this pin enables pin programming of the AD9558 configuration during startup. If this pin is low during startup, the user must program the part via the serial port, or use values that are stored in the EEPROM.

Configurable I/O Pin. Along with pins M6 through M0, this pin is configured through the AD9558 register space.

Clock Distribution Synchronization Pin. When this pin is activated, output drivers are held static and then synchronized on a low-to-high transition of this pin. This pin is used to arm the frame sync function when frame sync mode is enabled and has an internal 60 kΩ pull-up resistor.

Rev. A | Page 18 of 104

Data Sheet AD9558

Input/

Pin No. Mnemonic

43 REFA I

44

45, 46, 51, 52

47 REFC I

48

49 REFD I

50

53 REFB I

54

57, 58, 59, 60, 61, 62, 63

64 DVDD3 I Power 3.3 V Digital Supply. EP VSS O Exposed pad The exposed pad must be connected to ground (VSS).

REFA

DVDD3 I Power 3.3 V Digital (Reference Input) Power Supply.

REFC

REFD

REFB

M0, M1, M2,

M3, M4, M5,

M6

Output Pin Type Description

Differential input

I

I/O 3.3 V CMOS

Differential input

Reference A Input. This internally biased input is typically ac-coupled and, when configured as such, can accept any differential signal with single-ended swing up to 3.3 V. If dc-coupled, input can be LVPECL, LVDS, or single-ended CMOS.

Complementary Reference A Input. This pin is the complementary input to Pin 43.

Reference C Input. This internally biased input is typically ac-coupled and, when configured as such, can accept any differential signal with single-ended swing up to 3.3 V. If dc-coupled, input can be LVPECL, LVDS, or single-ended CMOS.

Complementary Reference C Input. This pin is the complementary input to Pin 47.

Reference D Input. This internally biased input is typically ac-coupled and, when configured as such, can accept any differential signal with single-ended swing up to 3.3 V. If dc-coupled, input can be LVPECL, LVDS, or single-ended CMOS.

Complementary Reference D Input. This pin is the complementary input to Pin 49.

Reference B Input. This internally biased input is typically ac-coupled and, when configured as such, can accept any differential signal with single-ended swing up to 3.3 V. If dc-coupled, input can be LVPECL, LVDS, or single-ended CMOS.

Complementary Reference B Input. This pin is the complementary input to Pin 53.

Configurable I/O Pins. These pins are configured under program control. The M7 pin (Pin 41) is the last pin of this group.

Rev. A | Page 19 of 104

AD9558 Data Sheet

–

TYPICAL PERFORMANCE CHARACTERISTICS

fR = input reference clock frequency; f LF = SYSCLK PLL internal loop filter used. AVDD, AVDD3, and DVDD at nominal supply voltage; f

PHASE NOISE (dBc/Hz)

PHASE NOI SE (d Bc/Hz)

60

–70

–80

–90

–100

–110

–120

–130

–140

–150

–160

60

–70

–80

–90

–100

–110

–120

–130

–140

–150

–160

INTEGRATED RMS JIT TER (12kHz TO 20MHz) : 296fs

1k100 10k 100k 1M 10M 100M

FREQUENCY OFFSET (Hz)

Figure 3. Absolute Phase Noise (Output Driver = HSTL),

f

= 19.44 MHz, f

R

DPLL Loop BW = 50 Hz, f

INTEGRATED RMS JITT ER (12kHz TO 20MHz): 320fs

1k100

FREQUENCY OFFSET (Hz)

OUT

SYS

100k 1M 10M 100M

10k

Figure 4. Absolute Phase Noise (Output Driver = HSTL),

f

= 19.44 MHz, f

R

DPLL Loop BW = 50 Hz, f

= 644.53125 MHz,

OUT

SYS

= output clock frequency; f

OUT

= 622.08 MHz,

= 49.152 MHz Crystal

= SYSCLK input frequency; fS = internal system clock frequency;

SYS

= 786.432 MHz, unless otherwise noted.

S

60

–70

–80

–90

–100

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

–160

09758-003

INTEGRATED RMS JIT TER (12kHz TO 20MHz) : 285fs

1k100 10k 100k 1M 10M 100M

FREQUENCY OFFSET (Hz)

09758-005

Figure 5. Absolute Phase Noise (Output Driver = HSTL),

f

= 19.44 MHz, f

R

DPLL Loop BW = 50 Hz, f

70

–80

–90

–100

–110

–120

–130

PHASE NOI SE (d Bc/Hz)

–140

–150

–160

09758-004

INTEGRATED RMS JITTER (12kHz TO 20MHz): 301fs

1k100

10k

FREQUENCY OFFSET (Hz)

= 693.482991 MHz,

OUT

= 49.152 MHz Crystal

SYS

100k 1M 10M 100M

09758-006

Figure 6. Absolute Phase Noise (Output Driver = HSTL),

= 19.44 MHz, f

f

R

DPLL Loop BW = 1 kHz, f

= 174.703 MHz,

OUT

= 49.152 MHz Crystal

SYS

Rev. A | Page 20 of 104

Data Sheet AD9558

–

PHASE NOISE (dBc/Hz)

80

–90

–100

–110

–120

–130

–140

–150

–160

INTEGRATED RMS JITT ER (12kHz TO 20MHz): 302fs

1k100 10k 100k 1M 10M 100M

FREQUENCY OFFSET (Hz)

Figure 7. Absolute Phase Noise (Output Driver = 3.3.V CMOS),

PHASE NOISE ( dBc/Hz)

–80

–90

–100

–110

–120

–130

–140

–150

–160

= 19.44 MHz, f

f

R

DPLL Loop BW = 100 Hz, f

70

INTEGRATED RMS JI TTER (12kHz TO 20MHz): 308fs

1k100 10k 100k 1M 10M 100M

FREQUENCY OFFSET (Hz)

= 161.1328125 MHz,

OUT

= 49.152 MHz Crystal

SYS

Figure 8. Absolute Phase Noise (Output Driver = HSTL),

f

= 2 kHz, f

R

DPLL Loop BW = 100 Hz, f

= 125 MHz,

OUT

= 49.152 MHz Crystal

SYS

09758-007

09758-008

PHASE NOISE (dBc/Hz)

60

–70

–80

–90

–100

–110

–120

–130

–140

–150

–160

INTEGRATED RMS JITT ER (12kHz TO 20MHz): 393fs

1k10 100 10k 100k 1M 10M 100M

FREQUENCY OFFSET (Hz)

Figure 10. Absolute Phase Noise (Output Driver = HSTL),

PHASE NOISE (dBc/Hz)

–70

–80

–90

–100

–110

–120

–130

–140

–150

–160

= 19.44 MHz, f

f

R

DPLL Loop BW = 0.1 Hz, f

60

INTEGRATED RMS JITTER (12kHz TO 20MHz): 371s

1k10 100 10k 100k 1M 10M 100M

FREQUENCY O FFSET (Hz)

= 644.53 MHz,

OUT

= 19.2 MHz TCXO

SYS

Figure 11. Absolute Phase Noise (Output Driver = HSTL),

= 19.44 MHz, f

f

R

DPLL Loop BW = 0.1 Hz, f

= 693.482991 MHz,

OUT

= 19.2 MHz TCXO

SYS

09758-010

09758-011

PHASE NOISE (dBc/Hz)

60

–70

–80

–90

–100

–110

–120

–130

–140

–150

–160

INTEG RATED RMS JIT TER (12kHz TO 20MHz): 343fs

1k100 10k 100k 1M 10M 100M

FREQUENCY OF FSET (Hz )

Figure 9. Absolute Phase Noise (Output Driver = HSTL),

= 25 MHz, f

f

R

DPLL Loop BW = 500 Hz, f

= 1 GHz,

OUT

= 49.152 MHz Crystal

SYS

09758-009

PHASE NOI SE (dBc/Hz)

70

–80

–90

–100

–110

–120

–130

–140

–150

–160

INTEG RATED RMS JITT ER (12kHz TO 20MHz): 404fs

1k10 100 10k 100k 1M 10M 100M

FREQUENCY OFFSET (Hz)

Figure 12. Absolute Phase Noise (Output Driver = HSTL),

= 19.44 MHz, f

f

R

DPLL Loop BW = 0.1 Hz, f

= 312.5 MHz,

OUT

= 19.2 MHz TCXO

SYS

09758-012

Rev. A | Page 21 of 104

AD9558 Data Sheet

–

A

2.0

1.9

1.8

1.7

1.6

1.5

1.4

L PEAK-TO-PEAK AMPLITUDE (V)

1.3

1.2

1.1

DIFFERE NTI

1.0

0

100

200

300

400

500

600

700

800

900

1100

1000

1200

FREQUENC Y (MHz)

1300

09758-116

PHASE NOISE (dBc/Hz)

–80

–90

–100

–110

–120

–130

–140

–150

–160

70

INTEGRATED RMS JITTE R (12kHz TO 20MHz) : 391fs

1k10 100 10k 100k 1M 10M 100M

FREQUENCY OFFSET (Hz)

09758-013

Figure 13. Absolute Phase Noise (Output Driver = 3.3 V CMOS),

PHASE NOI SE (d Bc/Hz)

–80

–90

–100

–110

–120

–130

–140

–150

–160

f

R

DPLL Loop BW = 0.1 Hz, f

70

INTEGRATED RM S JITT ER (12kHz TO 20MHz): 395fs

= 19.44 MHz, f

1k10 100

FREQUENCY O FFSET (Hz)

=161.1328125 MHz,

OUT

= 19.2 MHz TCXO

SYS

100k 1M 10M 100M

10k

Figure 14. Absolute Phase Noise (Output Driver = 1.8 V CMOS),

f

PHASE NOISE (dBc/Hz)

–70

–80

–90

–100

–110

–120

–130

–140

–150

–160

DPLL Loop BW = 0.1 Hz, f

60

INTEGRATED RMS JITTE R (12kHz TO 20MHz) : 388fs

= 2 kHz, f

R

1k10 100 10k 100k 1M 10M 100M

FREQUENCY OFFSET (Hz)

= 70.656 MHz,

OUT

= 19.2 MHz TCXO

SYS

Figure 15. Absolute Phase Noise (Output Driver = HSTL),

= 19.44 MHz, f

f

R

= 644.53 MHz, f

OUT

= 19.2 MHz TCXO

SYS

Holdover Mode

Figure 16. Amplitude vs. Toggle Rate,

HSTL Mode (LVPECL-Compatible Mode)

1.0

0.9

0.8

0.7

0.6

0.5

DIFFERENTIAL PEAK-TO-PEAK AMPLITUDE (V)

0.4

0 100 200 300 400 500 600 700 800

09758-014

LVDS BOOST MODE

LVDS DEFAULT

FREQUE NCY (MHz)

09758-117

Figure 17. Amplitude vs. Toggle Rate, LVDS

3.5

3.0

2.5

2.0

PEAK-TO-PEAK AMPLITUDE (V)

1.5

1.0

0 50 100 150 200 250 300

09758-016

1.8V CMO S

FREQUENC Y (MHz)

3.3V CMO S

09758-118

Figure 18. Amplitude vs. Toggle Rate with 10 pF Load,

3.3 V (Strong Mode) and 1.8 V CMOS

Rev. A | Page 22 of 104

Data Sheet AD9558

A

3.5

3.0

2.5

70

1.8V CMOS MODE

60

50

3.3V CMOS STRONG MODE

3.3V CMOS WEAK MODE

2.0

1.5

1.0

PEAK-TO-PEAK AMPLITUDE (V)

0.5

0

0 1020304050607080

FREQUENCY (MHz)

09758-119

Figure 19. Amplitude vs. Toggle Rate with 10 pF Load,

3.3 V (Weak Mode) CMOS

110

105

100

95

90

85

80

75

70

65

POWER (mW)

60

55

50

45

40

35 30

OUTPUT CHANNEL 1 OR 2:

BOTH HSTL DRIVERS ENABLED

OUTPUT CHANNEL 1 OR 2:

ONE HSTL DRIVER ENABLED

OUTPUT CHANNEL 0 OR 3:

HSTL DRIVER ENABLED

0 250 500 750 1000 1250

FREQUENCY (MHz)

09758-120

Figure 20. Power Consumption vs. Frequency,

HSTL Mode (Single Channel) on 1.8 V Output Driver Power Supply Only

(Pin 12, Pin 17, Pin 22, and Pin29)

65

60

OUTPUT CHANNEL 1 OR 2:

55

BOTH LVDS DRIVERS ENABLED

50

45

40

35

30

25

POWER (mW)

OUTPUT CHANNEL 0 OR 3:

20

LVDS DRIVER ENABLED

15

10

5

0

0 100 200 300 400 500 600 700 800

OUTPUT CHANNEL 1 OR 2:

ONE LVDS DRIVER ENABLED

FREQUENCY (MHz)

9758-121

Figure 21. LVDS Power Consumption vs. Frequency on 1.8 V Output Driver

Power Supply Only (Pin 12, Pin 17, Pin 22, and Pin 29)

40

30

POWER (mW)

20

10

0

0 50 100 150 200

FREQUENCY (MHz)

09758-122

Figure 22. Power Consumption vs. Frequency, One CMOS Driver on Output

Driver Power Supply Only (Pin 12, Pin 17, Pin 22, and Pin 29) for 1.8 V CMOS Mode,

or on Pin 25 and Pin 26 for 3.3 V CMOS Mode

1.0

0.8

0.6

0.4

0.2

0

LAMPLITUDE (V)

–0.2

–0.4

DIFFERENTI

–0.6

–0.8

–1.0

–101234

TIME (ns)

5

09758-123

Figure 23. Output Waveform, HSTL (400 MHz)

0.4

0.3

0.2

0.1

0

–0.1

–0.2

DIFFERE NTIAL AMP LITUDE (V)

–0.3

–0.4

–101234

TIME (ns)

09758-124

Figure 24. Output Waveform, LVDS (400 MHz)

Rev. A | Page 23 of 104

AD9558 Data Sheet

O

3.4

3.0

2.6

2.2

1.8

1.4

AMPLIT UDE (V)

1.0

0.6

0.2

–0.2

–10123456789101112131415

2pF LOAD 10pF LOAD

TIME (ns)

Figure 25. Output Waveform,

3.3 V CMOS (100 MHz, Strong Mode)

1.9

1.7

1.5

1.3

1.1

0.9

0.7

AMPLIT UDE (V)

0.5

0.3

0.1

–0.1

–10123456789101112131415

2pF LOAD 10pF LOAD

TIME (ns)

Figure 26. Output Waveform, 1.8 V CMOS (100 MHz)

09758-126

09758-127

3

0

–3

–6

–9

–12

–15

P GAIN (dB)

–18

LO

LOOP BW = 100Hz;

–21

HIGH PHASE MARGIN; PEAKING: 0.06dB; –3dB: 69Hz

LOOP BW = 2kHz;

–24

HIGH PHASE MARGIN; PEAKING: 0.097dB; –3dB: 1.23kHz

–27

LOOP BW = 5kHz; HIGH PHASE MARGIN; PEAKING: 0.14dB; –3dB: 4.27kHz

–30

10 100 1k 10k 100k

FREQUENCY OFF SET (Hz)

09758-129

Figure 28. Closed-Loop Transfer Function for 100 Hz, 2 kHz, and 5 kHz Loop

Bandwidth Settings; High Phase Margin Loop Filter Setting

(This is compliant with Telcordia GR-253 jitter transfer test for loop

bandwidths < 2 kHz.)

3

0

–3

–6

–9

–12

–15

P GAIN (dB)

–18

LO

–21

LOOP BW = 100Hz; NORMAL PHASE MARGIN;

–24

PEAKING: 0.09dB; –3dB: 117Hz LOOP BW = 2k Hz;

NORMAL PHASE MARGIN;

–27

PEAKING: 1.6dB; –3dB: 2.69kHz

–30

10 100 1k

FREQUENCY OFF SET (Hz)

10k 100k

09758-230

Figure 29. Closed-Loop Transfer Function for 100 Hz and 2 kHz Loop

Bandwidth Settings; Normal Phase Margin Loop Filter Setting

3.2

2pF LOAD 10pF LOAD

2.8

2.4

2.0

1.6

AMPLITUDE (V)

1.2

0.8

0.4

0

–5 5 152535455565758595

TIME (ns)

09758-128

Figure 27. Output Waveform, 3.3 V CMOS (20 MHz, Weak Mode)

Rev. A | Page 24 of 104

Data Sheet AD9558

V

INPUT/OUTPUT TERMINATION RECOMMENDATIONS

0.1µF

DOWNSTREAM

DEVICE

AD9557/ AD9558

HSTL OR LVDS

100Ω

0.1µF

WITH HIGH

IMPEDANCE

INPUT AND INTERNAL

DC BIAS

09758-130

Figure 30. AC-Coupled LVDS or HSTL Output Driver

(100 Ω resistor can go on either side of decoupling capacitors and should be

as close as possible to the destination receiver.)

10MHz TO 50MHz F UNDAMENTAL

AT CUT CRYST AL WIT H

10pF LO AD CAPACITANCE

Figure 33. System Clock Input (XOA, XOB) in Crystal Mode

(The recommended C

= 10 pF is shown. The values of the 10 pF shunt

LOAD

capacitors shown here should equal the C

10pF

XOA

AD9557/ AD9558

XOB

of the crystal.)

LOAD

09758-133

Z0 = 50Ω

AD9557/ AD9558

HSTL OR LVDS

SINGLE-ENDED

(NOT COUPL ED)

= 50Ω

Z

0

100Ω

LVDS OR 1.8V HS TL

HIGH IMPEDANCE

DIFFERE NTIAL

RECEIVER

09758-131

Figure 31. DC-Coupled LVDS or HSTL Output Driver

= 3.3

S

82Ω82Ω

3.3V

LVPECL

127Ω127Ω

09758-132

AD9557/ AD9558

1.8V

HSTL

0.1µF

Z0 = 50Ω

SINGLE -ENDED

(NOT COUPLED)

= 50Ω

Z

0

Figure 32. Interfacing the HSTL Driver to a 3.3 V LVPECL Input

(This method incorporates impedance matching and dc biasing for bipolar

LVPECL receivers. If the receiver is self-biased, the termination scheme shown

in Figure 30 is recommended.)

150Ω

0.1µF

XOA

AD9557/ AD9558

XOB

09758-134

3.3V CMOS TCXO

300Ω

Figure 34. System Clock Input (XOA, XOB) When Using a TCXO/OCXO with

3.3 V CMOS Output

Rev. A | Page 25 of 104

AD9558 Data Sheet

GETTING STARTED

CHIP POWER MONITOR AND STARTUP

The AD9558 monitors the voltage on the power supplies at power-up. When DVDD3 is greater than 2.35 V ± 0.1 V and DVDD and AVDD are greater than 1.4 V ± 0.05 V, the device generates a 20 ms reset pulse. The power-up reset pulse is internal and independent of the sequence eliminates the need for the user to provide external power supply sequencing. Within 45 ns after the leading edge of the internal reset pulse, the M7 to M0 multifunction pins behave as high impedance digital inputs and continue to do so until programmed otherwise. The delay on the M7 to M0 pin function change is 45 ns for pin reset or soft reset.

During a device reset (either via the power-up reset pulse or the RESET

pin), the multifunction pins (M7 to M0) behave as high impedance inputs, but upon removal of the reset condition, level-sensitive latches capture the logic pattern present on the multifunction pins.

RESET

pin. This internal power-up reset

MULTIFUNCTION PINS AT RESET/POWER-UP

The AD9558 requires the user to supply the desired logic state to the PINCONTROL pin, as well as to the M7 to M0 pins. If PINCONTROL is high, the part is in hard pin programming mode. See the Pin Program Function Description section for details on hard pin programming.

At startup, there are three choices for the M7 to M0 pins: pullup, pull-down, and floating. If the PINCONTROL pin is low, the M7 to M0 pins determine the following configurations:

• Following a reset, the M1 and M0 pins determine whether

the serial port interface behaves according to the SPI or I protocol. Specifically, M0 = M1 = low selects the SPI interface, and any other value selects the I level logic of M1 and M0 allows the user to select eight possible I

• The M3 and M2 pins select which of the eight possible

EEPROM profiles are loaded, or if the EEPROM loading is bypassed. Leaving M3 and M2 floating at startup bypasses the EEPROM loading, and the factory defaults are used instead (see Tab l e 2 2 ).

2

C addresses (see Tabl e 24 ).

2

C port. The 3-

2

C

DEVICE REGISTER PROGRAMMING WHEN USING A REGISTER SETUP FILE

The evaluation software contains a programming wizard and a convenient graphical user interface that assists the user in determining the optimal configuration for the DPLL, APLL, and SYSCLK based on the desired input and output frequencies. It generates a register setup file with a .STP extension that is easily readable using a text editor.

After using the evaluation software to create the setup file, use the following sequence to program the AD9557 once:

1. Register 0x0A01 = 0x20 (set user free run mode).

2. Register 0x0A02 = 0x02 (hold outputs in static SYNC).

(Skip this step if using SYNC on DPLL phase lock or SYNC on DPLL frequency lock. See Register 0x0500[1:0].)

3. Register 0x0405 = 0x20 (clear APLL VCO calibration).

4. Write the register values in the STP file from Address 0x0000

to Address 0x032E.

5. Register 0x0005 = 0x01 (update all registers).

6. Write the rest of the registers in the STP file, starting at

Address 0x0400.

7. Register 0x0405 = 0x21 (calibrate APLLon next I/O update).

8. Register 0x0403 = 0x07 (configure APLL).

9. Register 0x0400 = 0x81 (configure APLL).

10. Register 0x0005 = 0x01 (update all registers).

11. Register 0x0A01[5] = 0b (clear user free run mode).

12. Register 0x0005 = 0x01 (update all registers).

REGISTER PROGRAMMING OVERVIEW

This section provides an overview of the register blocks in the

AD9558, describing what they do and why they are important.

Registers Differing from Defaults for Optimal Performance

Ensure that the following registers are programmed to the listed values for optimal performance:

• Register 0x0405[7:4] = 0x2

• Register 0x0403 = 0x07

• Register 0x0400 = 0x81

If the silicon revision (Register 0x000A) equals 0x21 or higher, the values listed here are already the default values.

Rev. A | Page 26 of 104

Data Sheet AD9558

Program the System Clock and Free Run Tuning Word

The system clock multiplier (SYSCLK) parameters are at Register 0x0100 to Register 0x0108, and the free run tuning word is at Register 0x0300 to Register 0x0303. Use the following steps for optimal performance:

1. Set the system clock PLL input type and divider values.

2. Set the system clock period.

It is essential to program the system clock period because many of the AD9558 subsystems rely on this value.

3. Set the system clock stability timer.

It is highly recommended that the system clock stability timer be programmed. This is especially important when using the system clock multiplier and also applies when using an external system clock source, especially if the external source is not expected to be completely stable when power is applied to the AD9558. The system clock stability timer specifies the amount of time that the system clock PLL must be locked before the part declares that the system clock is stable. The default value is 50 ms.

4. Program the free run tuning word.

The free run frequency of the digital PLL (DPLL) determines the frequency appearing at the APLL input when free run mode is selected. The free run tuning word is at Register 0x0300 to Register 0x0303. The correct free run frequency is required for the APLL to calibrate and lock correctly.

5. Set user free run mode (Register 0x0A01[5] = 1b).

Initialize and Calibrate the Output PLL (APLL)

The registers controlling the APLL are at Register 0x0400 to Register 0x0408. This low noise, integer-N PLL multiplies the DPLL output (which is usually 175 MHz to 200 MHz) to a frequency in the 3.35 GHz to 4.05 GHz range. After the system clock is configured and the free run tuning word is set in Register 0x0300 to Register 0x0303, the user can set the manual APLL VCO calibration bit (Register 0x0405[0]) and issue an I/O update (Register 0x0005[0]). This process performs the APLL VCO calibration. VCO calibration ensures that, at the time of calibration, the dc control voltage of the APLL VCO is centered in the middle of its operating range. It is important to remember the following points when calibrating the APLL VCO:

• The system clock must be stable.

• The APLL VCO must have the correct frequency from the

30-bit DCO (digitally controlled oscillator) during calibration.

• The APLL VCO must be recalibrated any time the APLL

frequency changes.

• APLL VCO calibration occurs on the low-to-high transition

of the manual APLL VCO calibration bit, and this bit is not autoclearing. Therefore, this bit must be cleared (and an I/O update issued) before another APLL calibration is started.

• The best way to monitor successful APLL calibration is to

monitor Bit 2 in Register 0x0D01 (APLL lock).

Program the Clock Distribution Outputs

The APLL output goes to the clock distribution block. The clock distribution parameters reside in Register 0x0500 to Register 0x0509. They include the following:

• Output power-down control

• Output enable (disabled by default)

• Output synchronization

• Output mode control

• Output divider functionality

See the Clock Distribution section for more information.

Generate the Output Clock

If Register 0x0500[1:0] is programmed for automatic clock distribution synchronization via the DPLL phase or frequency lock, the synthesized output signal appears at the clock distribution outputs. Otherwise, set and then clear the soft sync clock distribution bit (Register 0x0A02, Bit 1), or use a multifunction pin input (if programmed for use) to generate a clock distribution sync pulse, which causes the synthesized output signal to appear at the clock distribution outputs.

Program the Multifunction Pins (Optional)

This step is required only if the user intends to use any of the multifunction pins for status or control. The multifunction pin parameters are at Register 0x0200 to Register 0x0208.

Program the IRQ Functionality (Optional)

This step is required only if the user intends to use the IRQ feature. The IRQ monitor registers are at Register 0x0D02 to Register 0x0D09. If the desired bits in the IRQ mask registers at Register 0x020A to Register 0x020F are set high, the appropriate IRQ monitor bit at Register 0x0D02 to Register 0x0D07 is set high when the indicated event occurs.

Individual IRQ events are cleared by using the IRQ clearing registers at Register 0x0A04 to Register 0x0A09, or by setting the clear all IRQs bit (Register 0x0A03[1]) to 1b.

The default values of the IRQ mask registers are such that interrupts are not generated. The IRQ pin mode default is opendrain NMOS.

Program the Watchdog Timer (Optional)

This step is required only if the user intends to use the watchdog timer. The watchdog timer control is in Register 0x0210 and Register 0x0211 and is disabled by default.

The watchdog timer is useful for generating an IRQ after a fixed amount of time. The timer is reset by setting the clear watchdog timer bit (Register 0x0A03[0]) to 1b.

Rev. A | Page 27 of 104

AD9558 Data Sheet

Program the Digital Phase-Locked Loop (DPLL)

The DPLL parameters reside in Register 0x0300 to Register 0x032E. They include the following:

• Free run frequency

• DPLL pull-in range limits

• DPLL closed-loop phase offset

• Phase slew control (for hitless reference switching)

• Tuning word history control (for holdover operation)

Program the Reference Inputs

The reference input parameters reside in Register 0x0600 to Register 0x0602. See the Reference Clock Input section for details on programming these functions. They include the following:

• Reference power-down

• Reference logic family

• Reference priority

Program the Reference Profiles

The reference profile parameters reside in Register 0x0700 to Register 0x07E6. The AD9558 evaluation software contains a wizard that calculates these values based on the user’s input frequency. See the Reference Profiles section for details on programming these functions. They include the following:

• Reference period

• Reference period tolerance

• Reference validation timer

• Selection of high phase margin loop filter coefficients

• DPLL loop bandwidth

• Reference prescaler (R divider)

• Feedback dividers (N1, N2, N3, FRAC1, and MOD1)

• Phase and frequency lock detector controls

Generate the Reference Acquisition

After the registers are programmed, the user can clear the user freerun bit (Register 0x0A01[5]) and issue an I/O update, using Register 0x0005[0] to invoke all of the register settings that are programmed up to this point.

After the registers are programmed, the DPLL locks to the first available valid reference that has the highest priority.

Rev. A | Page 28 of 104

Data Sheet AD9558

X

THEORY OF OPERATION

SYNC RESET PINCONTROL M0 M1 M2 M3 IRQ

SPI/I

REFA

REFC

2kHz TO 1.25GHz

2

REFB

REFD

C

SERIAL PORT

REF MONITORING

SPI/I2C

EEPROM

÷2

AUTOMATIC

SWITCHING

REGISTER

SPACE

AD9558

1

OUT0, OUT1, OUT2, OUT3, O UT4: 360kHz TO 1.25GHz; O UT5: 352Hz TO 1.25GHz

ROM

AND FSM

R DIVIDER

(20-BIT)

17-BIT

INTEGER

FRAC1/

÷N1

24b/24b

RESOLUTION

2kHz TO 8kHz FRAME S YNC SIGNAL

MULTIFUNCTION I/O PINS

(CONTROL AND STATUS

DPFD

MOD1

OVERVIEW

The AD9558 provides clocking outputs that are directly related in phase and frequency to the selected (active) reference, but with jitter characteristics that are governed by the system clock, the DCO, and the output PLL (APLL). The AD9558 supports up to four reference inputs and input frequencies ranging from 2 kHz to 1250 MHz. The core of this product is a digital phaselocked loop (DPLL). The DPLL has a programmable digital loop filter that greatly reduces jitter that is transferred from the active reference to the output. The AD9558 supports both manual and automatic holdover. While in holdover, the AD9558 continues to provide an output as long as the system clock is present. The holdover output frequency is a time average of the output frequency history just prior to the transition to the holdover condition. The device offers manual and automatic reference switchover capability if the active reference is degraded or fails completely. The AD9558 also has adaptive clocking capability that allows the DPLL divider ratios to be changed while the DPLL is locked.

The AD9558 has a system clock multiplier, a digital PLL (DPLL), and an analog PLL (APLL). The input signal goes first to the DPLL, which performs the jitter cleaning and most of the frequency translation. The DPLL features a 30-bit digitally controlled oscillator (DCO) output that generates a signal in the 175 MHz to 200 MHz range. The DPLL output goes to an analog integer-N PLL (APLL), which multiplies the signal up to the 3.35 GHz to

4.05 GHz range. That signal is then sent to the clock distribution

M4 M5 M6 M7

READBACK)

DIGITAL

LOOP

FILTER

DIGITAL PLL (DPL L)

Figure 35. Detailed Block Diagram

FREE RUN

TW

SYSTEM

CLOCK

MULTIPLIER

TUNING

WORD

CLAMP

AND

HISTORY

O OR XTAL

÷2

PFD/CP

30-BIT

NCO

XO FREQUENCIES

10MHz TO 180MHz

XTAL: 10MHz TO 50MHz

×2

÷N3

LF

×2

FRAME SYNC PULSE

÷N2

RF DIVIDER 1 ÷3 TO ÷11

MAX 1.25GHz

RF DIVIDER 2 ÷3 TO ÷11

OUTPUT PLL (APLL)

PFD/CP

APLL

STATUS

LF

LF_VCO2

÷M0 TO ÷M3b ARE

10-BIT INTEGER

DIVIDERS

÷M0

FRAME SYNC

MODE ON LY

÷M1

÷M2

÷M3

÷M3b

×2

3.35GHz TO

4.05GHz

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

1

section, which has two divide-by-3 to divide-by-11 RF dividers that are cascaded with 10-bit integer (divide-by-1 to divide-by-

1024) channel dividers.

The XOA and XOB pins provide the input for the system clock. These pins accept a reference clock in the 10 MHz to 600 MHz range, or a 10 MHz to 50 MHz crystal connected directly across the XOA and XOB pins. The system clock provides the clocks to the frequency monitors, the DPLL, and internal switching logic.

The AD9558 has six output drivers, arranged into four channels. Each channel has a dedicated 10-bit programmable post divider. Channel 0 and Channel 3 have one driver each, and Channel 1 and Channel 2 have two drivers each. Each driver is programmable either as a single differential or dual single-ended CMOS output. The clock distribution section operates at up to 1250 MHz.

In differential mode, the output drivers run on a 1.8 V power supply to offer very high performance with minimal power consumption. There are two differential modes: LVDS and 1.8 V HSTL. In 1.8 V HSTL mode, the voltage swing is compatible with LVPECL. If LVPECL signal levels are required, the designer can ac-couple the AD9558 output and use Thevenin-equivalent termination at the destination to drive the LVPECL inputs.

In single-ended mode, each differential output driver can operate as two single-ended CMOS outputs. OUT0 and OUT5 support either 1.8 V or 3.3 V CMOS operation. OUT1 through OUT4 support only 1.8 V operation.

1

9758-135

Rev. A | Page 29 of 104

AD9558 Data Sheet

REFERENCE CLOCK INPUTS

Four pairs of pins provide access to the reference clock receivers. To accommodate input signals with slow rising and falling edges, both the differential and single-ended input receivers employ hysteresis. Hysteresis also ensures that a disconnected or floating input does not cause the receiver to oscillate.

When configured for differential operation, the input receivers accommodate either ac- or dc-coupled input signals. The input receivers are capable of accepting dc-coupled LVDS and 2.5 V and 3.3 V LVPECL signals. The receiver is internally dc biased to handle ac-coupled operation, but there is no internal 50 Ω or 100 Ω termination.

When configured for single-ended operation, the input receivers exhibit a pull-down load of 45 kΩ (typical). Three user-programmable threshold voltage ranges are available for each single-ended receiver.

REFERENCE MONITORS

The accuracy of the input reference monitors depends on a known and accurate system clock period. Therefore, the functioning of the reference monitors is not operable until the system clock is stable.

Reference Period Monitor

Each reference input has a dedicated monitor that repeatedly measures the reference period. The AD9558 uses the reference period measurements to determine the validity of the reference based on a set of user-provided parameters in the profile register area of the register map.

The monitor works by comparing the measured period of a particular reference input with the parameters stored in the profile register assigned to that same reference input. The parameters include the reference period, an inner tolerance, and an outer tolerance. A 40-bit number defines the reference period in units of femtoseconds (fs). The 40-bit range allows for a reference period entry of up to 1.1 ms. A 20-bit number defines the inner and outer tolerances. The value stored in the register is the reciprocal of the tolerance specification. For example, a tolerance specification of 50 ppm yields a register value of 1/(50 ppm) = 1/0.000050 = 20,000 (0x04E20).

The use of two tolerance values provides hysteresis for the monitor decision logic. The inner tolerance applies to a previously faulted reference and specifies the largest period tolerance that a previously faulted reference can exhibit before it qualifies as nonfaulted. The outer tolerance applies to an already nonfaulted reference. It specifies the largest period tolerance that a nonfaulted reference can exhibit before being faulted.

To produce decision hysteresis, the inner tolerance must be less than the outer tolerance. That is, a faulted reference must meet tighter requirements to become nonfaulted than a nonfaulted reference must meet to become faulted.

Reference Validation Timer

Each reference input has a dedicated validation timer. The validation timer establishes the amount of time that a previously faulted reference must remain unfaulted before the AD9558 declares it valid. The timeout period of the validation timer is programmable via a 16-bit register. The 16-bit number stored in the validation register represents units of milliseconds (ms), which yields a maximum timeout period of 65,535 ms.

It is possible to disable the validation timer by programming the validation timer to 0b. With the validation timer disabled, the user must validate a reference manually via the manual reference validation override controls register (Address 0x0A0B).

Reference Validation Override Control

The user also has the ability to override the reference validation logic and can either force an invalid reference to be treated as valid, or force a valid reference to be treated as an invalid reference. These controls are in Register 0x0A0B to Register 0x0A0D.

REFERENCE PROFILES

The AD9558 has an independent profile for each reference input. A profile consists of a set of device parameters such as the R divider and N divider, among others The profiles allow the user to prescribe the specific device functionality that should take effect when one of the input references becomes the active reference.

The AD9558 evaluation software includes a frequency planning wizard that can configure the profile parameters, given the input and output frequencies.

The user should not change a profile that is currently in use because unpredictable behavior may result. The user can either select free run or holdover mode or invalidate the reference input prior to changing it.

REFERENCE SWITCHOVER

An attractive feature of the AD9558 is its versatile reference switchover capability. The flexibility of the reference switchover functionality resides in a sophisticated prioritization algorithm that is coupled with register-based controls. This scheme provides the user with maximum control over the state machine that handles reference switchover.

The main reference switchover control resides in the loop mode register (Address 0x0A01). The REF switchover mode bits (Register 0x0A01, Bits[4:2]) allow the user to select one of the five operating modes of the reference switchover state machine, as follows:

• Automatic revertive mode

• Automatic non-revertive mode

• Manual with automatic fallback mode

• Manual with holdover mode

• Full manual mode (without auto-holdover)

Rev. A | Page 30 of 104

ANALOG DEVICES AD9558 Service Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

SUPPLY VOLTAGE

SUPPLY CURRENT

POWER DISSIPATION

LOGIC OUTPUTS (M7 TO M0, IRQ)

SYSTEM CLOCK INPUTS (XOA, XOB)

REFERENCE INPUTS

REFERENCE MONITORS

REFERENCE SWITCHOVER SPECIFICATIONS

DISTRIBUTION CLOCK OUTPUTS

TIME DURATION OF DIGITAL FUNCTIONS

DIGITAL PLL

DIGITAL PLL LOCK DETECTION

HOLDOVER SPECIFICATIONS

SERIAL PORT SPECIFICATIONS—SPI MODE

SERIAL PORT SPECIFICATIONS—I2C MODE

JITTER GENERATION

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

INPUT/OUTPUT TERMINATION RECOMMENDATIONS

GETTING STARTED

CHIP POWER MONITOR AND STARTUP

MULTIFUNCTION PINS AT RESET/POWER-UP

DEVICE REGISTER PROGRAMMING WHEN USING A REGISTER SETUP FILE

REGISTER PROGRAMMING OVERVIEW

Registers Differing from Defaults for Optimal Performance

Program the System Clock and Free Run Tuning Word

Initialize and Calibrate the Output PLL (APLL)

Program the Clock Distribution Outputs

Generate the Output Clock

Program the Multifunction Pins (Optional)

Program the IRQ Functionality (Optional)

Program the Watchdog Timer (Optional)

Program the Digital Phase-Locked Loop (DPLL)

Program the Reference Inputs

Program the Reference Profiles

Generate the Reference Acquisition

THEORY OF OPERATION

OVERVIEW

REFERENCE CLOCK INPUTS

REFERENCE MONITORS

Reference Period Monitor

Reference Validation Timer

Reference Validation Override Control

REFERENCE PROFILES

REFERENCE SWITCHOVER