ANALOG DEVICES AD9552 Service Manual

X

Oscillator Frequency Upconverter

FEATURES

Converts a low frequency input reference signal to a high

frequency output signal
Input frequencies from 6.6 MHz to 112.5 MHz
Output frequencies up to 900 MHz
Preset pin programmable frequency translation ratios
Arbitrary frequency translation ratios via SPI port
On-chip VCO
Accepts a crystal resonator and/or an external oscillator

as a reference frequency source
Secondary output (either integer-related to the primary

output or a copy of the reference input)
RMS jitter: <0.5 ps
SPI-compatible, 3-wire programming interface
Single supply (3.3 V)
Very low power: <400 mW (under most conditions)
Small package size (5 mm × 5 mm)

APPLICATIONS

Cost effective replacement of high frequency VCXO, OCXO,

and SAW resonators
Extremely flexible frequency translation with low jitter for

SONET/SDH (including FEC), 10 Gb Ethernet, Fibre

Channel, and DRFI/DOCSIS
High-definition video frequency translation
Wireless infrastructure
Test and measurement (including handheld devices)

AD9552

GENERAL DESCRIPTION

The AD9552 is a fractional-N phase locked loop (PLL) based
clock generator designed specifically to replace high frequency
crystal oscillators and resonators. The device employs a sigma­delta (Σ-) modulator (SDM) to accommodate fractional
frequency synthesis. The user supplies an input reference signal
by connecting a single-ended clock signal directly to the REF
pin or by connecting a crystal resonator across the XTAL pins.

The AD9552 is pin programmable, providing one of 64 standard
output frequencies based on one of eight common input
frequencies. The device also has a 3-wire SPI interface, enabling
the user to program custom input-to-output frequency ratios.

The AD9552 relies on an external capacitor to complete the loop
filter of the PLL. The output is compatible with LVPECL, LVDS,
or single-ended CMOS logic levels, although the AD9552 is
implemented in a strictly CMOS process.

The AD9552 is specified to operate over the extended industrial
temperature range of −40°C to +85°C.

BASIC BLOCK DIAGRAM

REF

TAL

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

INPUT

FREQUENCY

SOURCE

SELECTOR

PIN-DEFINE D AND SERIAL PROGRAM MING

AD9552

PLL

Figure 1.

OUTPUT

CIRCUITRY

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2009–2011 Analog Devices, Inc. All rights reserved.

OUT2

OUT1

07806-001

AD9552

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Basic Block Diagram ........................................................................ 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Crystal Input Characteristics ...................................................... 4

Output Characteristics................................................................. 4

Jitter Characteristics..................................................................... 5

Serial Control Port ....................................................................... 6

Serial Control Port Timing .........................................................6

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ............................................. 9

Input/Output Termination Recommendations.......................... 12

Theory of Operation ...................................................................... 13

Preset Frequency Ratios ............................................................ 13

Component Blocks..................................................................... 15

Part Initialization and Automatic Power-On Reset............... 17

Output/Input Frequency Relationship .................................... 17

Calculating Divider Values ....................................................... 17

Low Dropout (LDO) Regulators.............................................. 18

Applications Information.............................................................. 19

Thermal Performance................................................................ 19

Serial Control Port ......................................................................... 20

Serial Control Port Pin Descriptions....................................... 20

Operation of the Serial Control Port....................................... 20

Instruction Word (16 Bits)........................................................ 21

MSB/LSB First Transfers ........................................................... 21

Register Map ................................................................................... 24

Register Map Descriptions........................................................ 25

Outline Dimensions....................................................................... 31

Ordering Guide .......................................................................... 31

REVISION HISTORY

7/11—Rev. C to Rev. D

Changes to Table 1, Reference Clock Input Characteristics,
Input High Voltage and Input Low Voltage Parameter Values... 4

Changes to Table 8, Added Endnote for Pin 9 and Pin 10.......... 8

Changes to Part Initialization Automatic Power-On Reset

Section, Second Paragraph............................................................ 17

Changes to Thermal Performance Section , First Paragraph ... 19

Changes to Serial Port Control Section, First Paragraph.......... 20

Changes to Table 20, Added Endnote to Bit 2 Description ...... 27

Updated Outline Dimensions....................................................... 31

7/10—Rev. B to Rev. C

Changed Crystal Load Capacitance to 15 pF............. Throughout

Added Conditions Statement to Specifications Section, Supply

Voltage Specifications, and Input Voltage Specifications............ 3

Reformatted Specifications Section (Renumbered Sequentially).....3

Added Input/Output Termination Recommendations Section,

Figure 17, and Figure 18 (Renumbered Sequentially)............... 13

Moved Preset Frequency Ratios Section ..................................... 13

Changes to Component Blocks Section ...................................... 15

Added Part Initialization and Automatic Power-On

Reset Section ................................................................................... 17

4/10—Rev. A to Rev. B

Changes to Preset Frequency Ratios Section.............................. 12

Moved Table 15 and Changes to Table 15................................... 13

Changes to Figure 17...................................................................... 14

Changes to PLL Section, Output Dividers Section, and

Input-to-OUT2 Option Section............................................... 15

Changes to Output/Input Frequency Relationship Section...... 16

Changes to Table 22 ....................................................................... 23

Changes to Table 26 ....................................................................... 26

9/09—Rev. 0 to Rev. A

Changes to Table 4.............................................................................3

Changes to Table 5.............................................................................4

Added Table 6; Renumbered Sequentially .....................................4

Changes to Figure 5...........................................................................9

Changes to PLL Section................................................................. 14

Changes to Table 22 ....................................................................... 21

Changes to Table 25 ....................................................................... 24

7/09—Revision 0: Initial Version

Rev. D | Page 2 of 32

AD9552

SPECIFICATIONS

Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ)
values apply for VDD = 3.3 V; T

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

SUPPLY VOLTAGE 3.135 3.30 3.465 V Pin 7, Pin 18, Pin 21, Pin 28
POWER CONSUMPTION

Total Current 149 169 mA At maximum output frequency with both output channels active
VDD Current By Pin

Pin 7 2 3 mA
Pin 18 77 86 mA
Pin 21 35 41 mA
Pin 28 35 41 mA

LVPECL Output Driver 36 41 mA

LOGIC INPUT PINS

INPUT CHARACTERISTICS1

Logic 1 Voltage, VIH 1.0 V

Logic 0 Voltage, VIL 0.8 V
Logic 1 Current, IIH 3 µA
Logic 0 Current, IIL 17 µA

LOGIC OUTPUT PINS

Output Characteristics

Output Voltage High, VOH 2.7 V
Output Voltage Low, VOL 0.4 V

RESET PIN

Input Characteristics2

Input Voltage High, VIH 1.8 V
Input Voltage Low, VIL 1.3 V
Input Current High, I
Input Current Low, I

INH

INL

Minimum Pulse Width High 2 ns

REFERENCE CLOCK
INPUT CHARACTERISTICS

Frequency Range 7.94 MHz N3 = 255; 2× frequency multiplier enabled; valid for all VCO bands

6.57 MHz

93.06 MHz SDM4 disabled; N3 = 365; valid for all VCO bands

71.28 MHz SDM4 enabled; N3 = 476; valid for all VCO bands

112.5 MHz

86.17 MHz

= 25°C, unless otherwise noted.

A

900 MHz with 100 Ω termination between both pins of the output
driver

For the CMOS inputs, a static Logic 1 results from either a pull-up
resistor or no connection

0.3 12.5 µA

31 43 µA

3

= 255; 2× frequency multiplier enabled; f

N
strains the frequency at OUT1 to be an integer sub-multiple of 3.35 GHz
(that is, f
output divider values)

4

SDM
frequency at OUT1 to be an integer sub-multiple of 4.05 GHz (that is,
f

= 4.05÷M GHz, where M is the product of the P0 and P1 output

OUT1

divider values)

4

SDM
at OUT1 to be an integer sub-multiple of 4.05 GHz (that is, f

4.05÷M GHz, where M is the product of the P
values)

= 3.35 GHz, which con-

VCO

= 3.35 ÷ M GHz, where M is the product of the P0 and P1

OUT1

disabled; N3 = 365; f

enabled; N3 = 476; f

= 4.05 GHz, which constrains the

VCO

= 4.05 GHz, which constrains the frequency

VCO

and P1 output divider

0

OUT1

=

Rev. D | Page 3 of 32

AD9552

Parameter Min Typ Max Unit Test Conditions/Comments

Input Capacitance 3 pF
Input Resistance 130 kΩ
Duty Cycle 40 60 %
Input Voltage
Input High Voltage, VIH 1.62 V
Input Low Voltage, VIL 0.52 V
Input Threshold Voltage 1.0 V

VCO CHARACTERISTICS

Frequency Range

Upper Bound 4050 MHz
Lower Bound 3350 MHz

VCO Gain 45 MHz/V

VCO Tracking Range ±300 ppm
VCO Calibration Time 140 s

1

The A[2:0], Y[5:0], and OUTSEL pins have 100 kΩ internal pull-up resistors.

2

The RESET pin has a 100 kΩ internal pull-up resistor, so the default state of the device is reset.

3

N is the integer part of the feedback divider.

4

Sigma-delta modulator.

5

The minimum allowable feedback divider value with the SDM disabled.

6

The minimum allowable feedback divider value with the SDM enabled.

7

The frequency at the input to the phase-frequency detector.

When ac coupling to the input receiver, the user must dc bias the input
to 1 V

7

= 77.76 MHz; time between completion of the VCO calibration

f

PFD

command (the rising edge of CS

(Pin 12)) to the rising edge of LOCKED

(Pin 20).

CRYSTAL INPUT CHARACTERISTICS

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

CRYSTAL FREQUENCY

Range 10 26 52 MHz

Tolerance 20 ppm
CRYSTAL MOTIONAL RESISTANCE 100 Ω
CRYSTAL LOAD CAPACITANCE 15 pF

Using a crystal with a specified load capacitance other than
15 pF (8 pF to 24 pF) is possible, but necessitates using the
SPI port to configure the AD9552 crystal input capacitance.

OUTPUT CHARACTERISTICS

Table 3.

Parameter Min Typ Max Unit Test Conditions/Comments

LVPECL MODE

Differential Output Voltage Swing 690 765 889 mV Output driver static

Common-Mode Output Voltage VDD − 1.77 VDD − 1.66 VDD − 1.20 V Output driver static

Frequency Range 0 900 MHz

Duty Cycle 40 60 % Up to 805 MHz output frequency

Rise/Fall Time1 (20% to 80%) 255 305 ps

100 Ω termination between both pins of
the output driver

Rev. D | Page 4 of 32

AD9552

Parameter Min Typ Max Unit Test Conditions/Comments

LVDS MODE

Differential Output Voltage Swing

Balanced, VOD 247 454 mV

Unbalanced, ∆VOD 25 mV

Offset Voltage

Common Mode, VOS 1.125 1.375 V Output driver static
Common-Mode Difference, ∆VOS 25 mV

Short-Circuit Output Current 17 24 mA
Frequency Range 0 900 MHz
Duty Cycle 40 60 % Up to 805 MHz output frequency
Rise/Fall Time1 (20% to 80%) 285 355 ps

CMOS MODE

Output Voltage High, VOH

IOH = 10 mA 2.8 V
IOH = 1 mA 2.8 V

Output Voltage Low, VOL

IOL = 10 mA 0.5 V
IOL = 1 mA 0.3 V

Frequency Range 0 200 MHz

Duty Cycle 45 55 % At maximum output frequency
Rise/Fall Time1 (20% to 80%) 500 745 ps

1

The listed values are for the slower edge (rise or fall).

Voltage swing between output pins;
output driver static

Absolute difference between voltage
swing of normal pin and inverted pin;
output driver static

Voltage difference between output pins;
output driver static

100 Ω termination between both pins of
the output driver

Output driver static; standard drive
strength setting

Output driver static; standard drive
strength setting

3.3 V CMOS; standard drive strength
setting

3.3 V CMOS; standard drive strength
setting; 15 pF load

JITTER CHARACTERISTICS

Table 4.

Parameter Min Typ Max Unit Test Conditions/Comments

JITTER GENERATION Input = 19.44 MHz crystal resonator

12 kHz to 20 MHz 0.64 ps rms f

0.70 ps rms f

50 kHz to 80 MHz 0.47 ps rms f

0.50 ps rms f

4 MHz to 80 MHz 0.11 ps rms f

0.12 ps rms f
JITTER TRANSFER BANDWIDTH 100 kHz See the Typical Performance Characteristics section
JITTER TRANSFER PEAKING 0.3 dB See the Typical Performance Characteristics section

Rev. D | Page 5 of 32

= 622.08 MHz (integer mode)

OUT

= 625 MHz (fractional mode)

OUT

= 622.08 MHz (integer mode)

OUT

= 625 MHz (fractional mode)

OUT

= 622.08 MHz (integer mode)

OUT

= 625 MHz (fractional mode)

OUT

AD9552

SERIAL CONTROL PORT

Table 5.

Parameter Min Typ Max Unit Test Conditions/Comments

CS

Input Logic 1 Voltage 1.6 V
Input Logic 0 Voltage 0.5 V
Input Logic 1 Current 0.03 µA
Input Logic 0 Current 2 µA
Input Capacitance 2 pF

SCLK

Input Logic 1 Voltage 1.6 V
Input Logic 0 Voltage 0.5 V
Input Logic 1 Current 2 µA
Input Logic 0 Current 0.03 µA
Input Capacitance 2 pF

SDIO

Input

Input Logic 1 Voltage 1.6 V
Input Logic 0 Voltage 0.5 V
Input Logic 1 Current 1 µA
Input Logic 0 Current 1 µA
Input Capacitance 2 pF

Output

Output Logic 1 Voltage 2.8 V 1 mA load current
Output Logic 0 Voltage 0.3 V 1 mA load current

SERIAL CONTROL PORT TIMING

Table 6.

Parameter Limit Unit

SCLK

Clock Rate, 1/t
Pulse Width High, t

Pulse Width Low, t
SDIO to SCLK Setup, tDS 4 ns min
SCLK to SDIO Hold, tDH 0 ns min
SCLK to Valid SDIO, tDV 13 ns max
CS to SCLK Setup (tS) and Hold (tH)
CS Minimum Pulse Width High

50 MHz max

CLK

3 ns min

HIGH

3 ns min

LOW

0 ns min

6.4 ns min

Rev. D | Page 6 of 32

AD9552

ABSOLUTE MAXIMUM RATINGS

Table 7.

Parameter Rating

Supply Voltage (VDD) 3.6 V
Maximum Digital Input Voltage −0.5 V to VDD + 0.5 V
Storage Temperature −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. D | Page 7 of 32

AD9552

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VDD

OUT1

OUT1

Y1

Y0

Y3

Y2

31

30

32

GND

29

28

27

26

25

1Y4

PIN 1

2Y5

INDICATOR

3A0
4A1

AD9552

5A2

TOP VIEW

6RESET

(Not to Scale)

7VDD
8LDO

9

11

10

12

13

CS

REF

XTAL

XTAL

NOTES

1. EXPOSE D DIE PAD MUST BE
CONNECTED TO GND.

SCLK

24 GND

23 O UT2
22

OUT2
21 V DD
20 L OCKED
19 L DO
18 V DD
17 L DO

14

15

16

SDIO

FILTER

OUTSEL

07806-002

Figure 2. Pin Configuration

Table 8. Pin Function Descriptions

Pin No. Mnemonic Type1 Description

29, 30, 31,
32, 1, 2

Y0, Y1, Y2, Y3, Y4,
Y5

I

Control Pins. These pins select preset values for the PLL feedback divider and the OUT1
dividers based on the input reference frequency selected via the A[0:2] pins and have
internal 100 kΩ pull-up resistors.

3, 4, 5 A0, A1, A2 I

Control Pins. These pins select the input reference frequency and have internal 100 kΩ pull­up resistors.

6 RESET I

Digital Input, Active High. Resets internal logic to default states. This pin has an internal

100 kΩ pull-up resistor, so the default state of the device is reset.
7, 18, 21, 28 VDD P Power Supply Connection: 3.3 V Analog Supply.
8, 17, 19 LDO P/O

LDO Decoupling Pins. Connect a 0.47 F decoupling capacitor from each of these pins to

ground.
9, 10 XTAL I Crystal Resonator Input. Connect a crystal resonator across these pins.2
11 REF I

Reference Clock Input. Connect this pin to an active clock input signal, or connect it to VDD

when using a crystal resonator across the XTAL pins.
12

CS

I Digital Input, Active Low, Chip Select.

13 SCLK I Serial Data Clock.
14 SDIO I/O Digital Serial Data Input/Output.
15 OUTSEL I

Logic 0 selects LVDS and Logic 1 selects LVPECL-compatible levels for both OUT1 and OUT2

when the outputs are not under SPI port control. Can be overridden via the programming

registers. This pin has an internal 100 kΩ pull-up resistor.
16 FILTER I/O Loop Filter Node for the PLL. Connect an external 12 nF capacitor from this pin to Pin 17 (LDO).
20 LOCKED O Active High Locked Status Indicator for the PLL.
26, 22

OUT1

, OUT2

O Complementary Square Wave Clocking Outputs.

27, 23 OUT1, OUT2 O Square Wave Clocking Outputs.
24, 25 GND P Analog Ground.
EP Exposed Die Pad The exposed die pad must be connected to GND.

1

I = input, I/O = input/output, O = output, P = power, P/O = power/output.

2

When no crystal is in use, leave these pins floating. The terminations are handled by internal circuitry.

Rev. D | Page 8 of 32

AD9552

m

m

m

m

TYPICAL PERFORMANCE CHARACTERISTICS

–20

–30
–40

–50

–60
–70

–80
–90

–100

–110
–120

PHASE NOISE (dB)

–130
–140

–150

–160

–170
–180

100 1k 10k 100k 1M 10M 100M

CARRIER 624.988784MHz 0.4009dB

FREQUENCY (Hz)

Figure 3. Phase Noise, Fractional-N, Pin Programmed

= 19.44 MHz, f

(f

XTAL

= 625 MHz)

OUT1

–20

–30
–40

–50

–60
–70

–80
–90

–100

–110
–120

PHASE NOISE (dB)

–130
–140

–150

–160

–170
–180

100 1k 10k 100k 1M 10M 100M

07806-014

Figure 6. Phase Noise, Integer, SDM Off

(f

XTAL

CARRIER 622.068199MHz 0.5831dB

FREQUENCY (Hz)

= 19.44 MHz, f

= 622.08 MHz)

OUT1

07806-016

–20

–30
–40

–50

–60
–70

–80
–90

–100

–110
–120

PHASE NOISE (dB)

–130
–140

–150

–160

–170
–180

100 1k 10k 100k 1M 10M 100M

CARRIER 624.999995MHz 0.4057dB

FREQUENCY (Hz)

Figure 4. Phase Noise, Fractional-N, Pin Programmed

= 19.44 MHz, f

(f

REF

10

0

–10

1

–20

0

–30

–1

–40

JITTER T RANSFER (dB)

–2

–50

–3

–60

1k 10k 100k 1M 10M

JITTER PEAKI NG

1k 10k 100k

FREQUENCY OFFSET (Hz)

= 625 MHz)

OUT1

JITTER T RANSFER

Figure 5. Jitter Transfer and Jitter Peaking

–20

–30
–40

–50

–60
–70

–80
–90

–100

–110
–120

PHASE NOISE (dB)

–130
–140

–150

–160

–170
–180

100 1k 10k 100k 1M 10M 100M

07806-015

CARRIER 622.079986MHz 0.3798dB

FREQUENCY (Hz )

07806-017

Figure 7. Phase Noise, Integer, SDM Off

= 19.44 MHz, f

(f

REF

35

30

25

20

15

SUPPLY CURRENT (mA)

10

5

07806-018

100 1k

FREQUENCY (MHz)

= 622.08 MHz)

OUT1

LVPECL

LVDS (STRONG)

LVDS (WEAK)

07806-019

Figure 8. Supply Current vs. Output Frequency,

LVPECL and LVDS (15 pF Load)

Rev. D | Page 9 of 32

AD9552

V

25

20

15

10

SUPPLY CURRENT (mA)

5

0

0 50 100 150 200 250

FREQUENCY (MHz )

Figure 9. Supply Current vs. Output Frequency,

CMOS (15 pF Load)

4.0

3.5

3.0

2.5

2.0

20pF

10pF

5pF

07806-020

1.6

1.4

1.2

1.0

0.8

AMPLITUDE (V p-p)

0.6

0.4
0 200 400 600 800 1000

LVPECL

LVDS (STRONG)

LVDS (WEAK)

FREQUENCY (MHz )

Figure 12. Peak-to-Peak Output Voltage vs. Frequency,

LVPECL and LVDS (15 pF Load)

60

55

07806-023

1.5

AMPLITUDE (V p-p)

1.0

0.5

0

0 100 2 00 300 400 500

FREQUENCY (MHz)

Figure 10. Peak-to-Peak Output Voltage vs. Frequency,

CMOS

55

54

53

52

DUTY CYCL E (%)

51

50

0 100 200 300

FREQUENCY (MHz )

5pF
10pF
20pF

Figure 11. Duty Cycle vs. Output Frequency, CMOS

DUTY CYCLE (%)

LVDS (WEAK)
LVDS (STRONG)
LVPECL

50

07806-021

100 200 300 400 500 600 700 800 900 1000

FREQUENCY (MHz)

07806-024

Figure 13. Duty Cycle vs. Output Frequency,

LVPECL and LVDS (15 pF Load)

200mV/DI

500ps/DIV

07806-022

07806-025

Figure 14. Typical Output Waveform, LVPECL (805 MHz)

Rev. D | Page 10 of 32